JP4343727B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize miniaturization, regarding a semiconductor device referred to as SIP (System In Package). <P>SOLUTION: The semiconductor device is provided with a package substrate 5; a microcomputer chip 1 which is arranged on the core layer 5c of the package substrate 5 and equipped with calculation processing functions; a flash memory 2 and a DRAM 3 which were equipped with memory circuits, respectively, wires 6 which connect the flash memory 2 and the DRAM 3 to the package substrate 5, respectively, sealing body 7 which seals the flash memory 2 and the DRAM 3 on the package substrate 5; and a plurality of solder balls 8 which are connected to bump lands at a rear surface 5b side of the package substrate 5. The package substrate 5 is provided with a main surface side wiring layer 5d which is arranged at a main surface 5a side from the core layer 5c, and a rear surface side wiring layer 5e which is arranged at the rear surface 5b side from the core layer 5c. Wires 5j, 5k of the package substrate 5 are distributed on the upper side and the lower side of the microcomputer chip 1, the number of wiring layers of the package substrate 5 is reduced, to attain miniaturization of an SIP 4 (semiconductor device). <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a plurality of semiconductor chips.

  In a conventional semiconductor device (multi-chip module) having a plurality of semiconductor chips, among three chips mounted on the main surface of the package substrate, a chip in which a DRAM (Dynamic Random Access Memory) is formed and a flash Each chip on which the memory is formed is electrically connected to the wiring of the package substrate through Au bumps, and a chip on which a high-speed microprocessor is formed is mounted on the two chips. Are electrically connected to the bonding pads of the package substrate via Au wires (see, for example, Patent Document 1).

  Further, in a package in which a plurality of tape carriers are stacked, one end of a lead formed on one surface of the tape carrier is electrically connected to a connection terminal of a semiconductor chip, and the other end of the lead is formed on the tape carrier. The connection terminals common to the plurality of semiconductor chips are formed at the same location of the plurality of tape carriers, and are connected to the same through the plurality of through holes penetrating each other. It is pulled out to the external connection terminal (see, for example, Patent Document 2).

In addition, in a wiring board with an IC (Integrated Circuit) chip built-in, the manufacturing method of this board is such that a sheet material having an adhesive on the surface exposes one opening of the accommodating part to the inside of the accommodating part. A step of closing the IC chip so as to adhere to the sheet material, a step of placing the IC chip in the accommodating portion so that the IC chip is adhered to the sheet material, and a step of filling the accommodating portion with a fixing resin and curing to fix the IC chip in the core substrate. (For example, refer to Patent Document 3).
International Publication Number WO 02/103793 A1 (FIG. 2) International Publication Number WO 98/25304 A1 (FIG. 36) Japanese Patent Laying-Open No. 2003-309243 (FIG. 1)

  As an example of a semiconductor device having a plurality of semiconductor chips, a semiconductor chip having an arithmetic processing function (hereinafter referred to as a microcomputer chip) and a semiconductor chip having a memory circuit (hereinafter referred to as a memory chip) are mounted on a wiring board. A semiconductor device called SIP (System In Package) is known. In SIP, a plurality of memory chips are often mounted, and therefore, a chip stack type structure is often employed. However, downsizing of SIP is also required.

  As a result of studying a structure in which a semiconductor chip is embedded in a wiring board in order to reduce the SIP size, the present inventor has found the following problems.

  That is, if the wiring of the wiring in the connection between the microcomputer chip, the memory chip and the external terminal is not distributed to both the front and back sides of the embedded semiconductor chip, the number of wiring layers in the wiring board increases and the semiconductor device cannot be reduced in size. Problems arise.

  Note that Patent Document 1 (International Publication No. WO 02/103793 A1) does not describe a structure in which a semiconductor chip is embedded in a wiring board. Therefore, a wiring layer is formed on both front and back sides of a microcomputer chip. Such a structure is not described.

  Patent Document 2 (International Publication No. WO 98/25304 A1) describes a structure in which wirings are arranged on both front and back sides of a microcomputer chip, but all the balls (external terminals) are connected to the microcomputer chip. Since all the balls are connected to different through-hole wirings, at least the same number of through-hole wirings as all the balls must be arranged in the outer peripheral area of the microcomputer chip. In other words, the semiconductor device cannot be reduced in size.

  Patent Document 3 (Japanese Patent Laid-Open No. 2003-309243) describes a method for manufacturing a wiring board in which a semiconductor chip is embedded, but all external terminals that exchange signals with external devices are connected to the wiring board. The structure of the semiconductor device arranged on one side of the (package substrate) is not described at all.

  An object of the present invention is to provide a semiconductor device that can be reduced in size by reducing the number of wiring layers of a wiring board.

  Another object of the present invention is to provide a semiconductor device capable of improving electrical characteristics.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

That is, the present invention includes a first main surface, the first semiconductor element formed on the first main surface, is formed on the peripheral portion of the first main surface, is connected to the first semiconductor element and the electrical first pad, and have a first back surface opposite the first major surface includes a first semiconductor chip having an arithmetic processing function, the front surface, and a back surface of said surface opposite , before SL core layer which seals the first semiconductor chip, between the rear surface of the surface and the core layer of the core layer, the first through-hole is formed around the first semiconductor chip, the core A second through hole formed around the first semiconductor chip between the front surface of the layer and the back surface of the core layer, a first conductor portion formed in the first through hole, the first second conductor portion formed in the interior of the second through-hole, is connected to the first conductor portion, is formed on the surface of the core layer First wiring layer, which is connected to the second conductor portion, the 1GND plane having a reference potential formed in the first semiconductor chip opposite to a region at said upper surface of said core layer, connected to the first conductor portion And a second wiring layer formed on the back surface of the core layer and a reference connected to the second conductor and formed in a region facing the first semiconductor chip on the back surface of the core layer. a wiring substrate having a first 2GND plane having a potential, the second main surface, a second semiconductor element formed on the second main surface, is formed on the second major surface, said second semiconductor device electrically connected second pad, and having a second back surface of the second main surface opposite, comprising a memory circuit, the said first wiring layer of the wiring board second pad electrically connected And mounted on the first wiring layer. And the semiconductor chip, the second is wiring layer and electrically connected, a first external terminal formed on the second wiring layer, is intended to include.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a semiconductor device having a microcomputer chip and a memory chip, the microcomputer chip is embedded in the wiring board, and the wiring on the main surface side wiring layer on the upper side of the microcomputer chip and the wiring on the lower side wiring layer on the lower side are connected to the core layer. The back side wiring layer is connected to the external connection input / output circuit of the microcomputer chip and the back side external terminal mounting electrode, and is connected to the connecting conductor part and the main surface side. By having the first wiring that is not connected to the wiring of the wiring layer, the wiring connected to the microcomputer chip can be arranged only in the back surface side wiring layer. As a result, all the wirings in the wiring board can be distributed and arranged in the main surface side wiring layer and the back surface side wiring layer, and the number of wiring layers in the wiring board can be reduced. As a result, the wiring board can be thinned and the semiconductor device can be miniaturized.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a block diagram showing an example of the system of the semiconductor device shown in FIG. 1, and FIG. 3 is a semiconductor device shown in FIG. FIG. 4 is an enlarged partial plan view showing an enlarged portion A shown in FIG. 3, and FIG. 5 is incorporated in the semiconductor device shown in FIG. FIG. 6 is a plan view showing an example of the wiring pattern of the second wiring layer from the top of the wiring board. FIG. 6 shows an example of the wiring pattern of the third wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. FIG. 7 is a plan view showing an example of a wiring pattern of a fourth wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1, and FIG. 8 is a wiring incorporated in the semiconductor device shown in FIG. Wiring pattern of the fifth wiring layer from the top of the board FIG. 9 is a plan view showing an example of a wiring pattern of a sixth wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1, and FIG. 10 is a diagram of the wiring pattern shown in FIG. FIG. 11 is an enlarged partial plan view showing a plane wiring of a ground potential (reference potential) and a wiring pattern around it, and FIG. 11 is an enlarged portion showing an example of wiring between a microcomputer chip and a memory chip in the wiring pattern of the uppermost wiring layer shown in FIG. FIG. 12 is an enlarged partial plan view showing an example of wiring between the microcomputer chip and the memory chip in the wiring pattern of the second wiring layer shown in FIG. 5, and FIG. 13 is a third wiring layer shown in FIG. FIG. 14 is an enlarged partial plan view showing an example of wiring between the microcomputer chip and the memory chip in the wiring pattern of FIG. 14, and FIG. 14 is a microcomputer chip in the wiring pattern of the fourth wiring layer shown in FIG. FIG. 15 is an enlarged partial plan view showing an example of wiring between memory chips, and FIG. 15 is an example of wiring between a microcomputer chip and a memory chip and wiring between microcomputer chips and solder balls in the wiring pattern of the fifth wiring layer shown in FIG. FIG. 16 is an enlarged partial plan view showing an example of the wiring between the microcomputer chip and the memory chip and the wiring between the microcomputer chip and the solder ball in the wiring pattern of the sixth wiring layer shown in FIG. FIG. 17 is a cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 1 cut on the ground potential plane wiring. FIG. 18 is an example of the structure of the semiconductor device shown in FIG. 1 cut on the ground potential through-hole wiring. FIG.

  The semiconductor device according to the first embodiment shown in FIG. 1 includes a microcomputer chip 1 that is a semiconductor chip (CPU (Central Processing Unit)) having an arithmetic processing function, and a memory chip that is a semiconductor chip having a memory circuit. In the first embodiment, as an example of the semiconductor device, a description will be given of a SIP (System In Package) 4 in which one microcomputer chip 1 and three memory chips are incorporated.

  In the SIP 4 of the first embodiment, the microcomputer chip 1 is arranged in the wiring board by face-down mounting, and further, three memory chips are arranged on the main surface 5a of the wiring board, and these three memory chips are These are arranged on the wiring board by face-up mounting and are electrically connected to the wiring board by wire connection.

  In addition, a plurality of solder balls 8 as external terminals are provided in a matrix arrangement on the back surface 5b opposite to the main surface 5a of the wiring board, and memory chips and fine metal wires are placed on the main surface 5a side. A sealing body 7 to be sealed is formed.

  That is, the SIP 4 is a BGA (Ball Grid Array) type semiconductor device.

  The detailed structure of the SIP 4 shown in FIG. 1 will be described. A microcomputer chip 1 which is a first semiconductor chip having a semiconductor element and a pad 1c as a plurality of electrodes on its main surface 1a and having an arithmetic processing function. And a flash memory 2 and a DRAM (Dynamic Random Access), which are second semiconductor chips each having a semiconductor element and pads 2c and 3c as a plurality of electrodes on the main surfaces 2a and 3a, respectively. Memory) 3, package substrate 5 as a wiring substrate, sealing body 7 for sealing the flash memory 2 and DRAM 3 on the main surface 5 a of the package substrate 5, and external terminal mounting on the back surface 5 b side of the package substrate 5 It consists of a plurality of solder balls 8 connected to bump lands 5h shown in FIG.

  The package substrate 5 includes a main surface 5a, a back surface 5b, an insulating core layer 5c disposed between the main surface 5a and the back surface 5b, and a main surface disposed on the main surface 5a side from the core layer 5c. A side wiring layer 5d, a back surface side wiring layer 5e disposed on the back surface 5b side from the core layer 5c, and a through-hole wiring (connection conductor portion for connection) disposed in a through hole 5f formed through the core layer 5c. ) 5g and a plurality of bump lands 5h arranged only on the back surface 5b, and the wiring 5j of the main surface side wiring layer 5d and the wiring 5k of the back surface side wiring layer 5e are electrically connected by the through-hole wiring 5g. It is connected to the.

  Further, in each of the main surface side wiring layer 5d and the back surface side wiring layer 5e, the wirings 5j and the wirings 5k are arranged via the insulating layer 5i, and the wirings 5j of the adjacent layers and the wirings 5k are connected to the via wiring 5t. It is electrically connected via.

  Further, the microcomputer chip 1 which is the first semiconductor chip is arranged on the core layer 5c of the package substrate 5 with the main surface 1a facing the back surface 5b side of the package substrate 5, and the microcomputer chip 1 has a pad 1c and a back surface. The wiring 5k of the side wiring layer 5e is electrically connected through the gold bump 1d. That is, the microcomputer chip 1 is disposed on the core layer 5c with its main surface 1a facing downward and the back surface 1b facing upward. Therefore, the main surface 1a and the back surface side wiring layer 5e face each other.

  In the core layer 5c, a plurality of through-hole wirings 5g are formed around the microcomputer chip 1.

  Further, the flash memory 2 and the DRAM 3 which are the second semiconductor chips and the memory chips are arranged on the main surface 5a of the package substrate 5, and further, the pads 2c of the flash memory 2 and the main surface side wiring layer 5d. The wiring 5j of the DRAM 3 is electrically connected to the pad 3c of the DRAM 3 and the wiring 5j of the main surface side wiring layer 5d by a wire (metal thin wire) 6 such as a gold wire.

  Further, the SIP 4 is equipped with one flash memory 2 and two DRAMs 3, and each memory chip has its back surface 2b, 3b bonded to the main surface 5a of the package substrate 5 with a bonding material, Resin-sealed together with a plurality of wires 6 by a sealing body 7.

  Note that a pad 1c connected to the external connection input / output circuit 1e shown in FIG. 2 in the microcomputer chip 1 and a bump land 5h corresponding thereto are electrically connected to the back surface side wiring layer 5e of the package substrate 5. In addition, a plurality of first wirings 5m that are not connected to the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d are provided.

  That is, the first wiring 5m is not disposed in the main surface side wiring layer 5d, but is disposed only in the back surface side wiring layer 5e, and any of the through-hole wirings 5g provided in the core layer 5c and the main wiring layer 5c. The wiring 5j of the surface side wiring layer 5d is not connected, and the pad 1c connected to the external connection input / output circuit 1e of the microcomputer chip 1 to the corresponding bump land 5h is routed only by the back surface side wiring layer 5e. In the SIP 4, a large number of such first wirings 5 m are provided only on the back surface side wiring layer 5 e in the package substrate 5.

  Further, on the back surface side wiring layer 5e, the pad 1c connected to the memory connection input / output circuit 1f of the microcomputer chip 1 and the pad 2c of the flash memory 2 are connected to the through hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d. A second wiring 5n that is electrically connected via the wiring is arranged. Further, the second wiring 5n is connected to the third wiring 5p connected to the bump land 5h in the back surface side wiring layer 5e.

  Next, the configuration of the SIP4 system will be described with reference to FIG.

  The microcomputer chip 1 controls the input / output of data via the flash memory 2 and the DRAM 3 provided outside the system and inside the system. Therefore, the external connection input / output circuit 1e and the memory connection input / output circuit 1f are provided, and the logical address for the external connection input / output circuit 1e is converted into the address for the flash memory 2 or the DRAM 3.

  That is, information such as an address, a command, and a clock is exchanged with the flash memory 2 and the DRAM 3.

  In the SIP 4 of the first embodiment, the pad 1c connected to the external connection input / output circuit 1e of the microcomputer chip 1 and the bump land 5h (solder ball 8) corresponding thereto are arranged only on the back surface side wiring layer 5e. Further, they are connected by the first wiring 5m. Further, the pad 1c connected to the memory connection input / output circuit 1f of the microcomputer chip 1 and the pad 2c of the flash memory 2 are the second wiring 5n, the through-hole wiring 5g and the main surface side wiring of the back surface side wiring layer 5e. They are connected via the wiring 5j of the layer 5d. Further, a third wiring 5p that connects the second wiring 5n and the bump land 5h (solder ball 8) is formed on the back surface side wiring layer 5e.

  As described above, the SIP 4 according to the first embodiment arranges the microcomputer chip 1 in the core layer 5c of the package substrate 5 and arranges the main surface 1a of the microcomputer chip 1 toward the external terminal side. Three memory chip-related wirings 5j are arranged on the upper main-surface-side wiring layer 5d, and a plurality of first wirings directly connected to the bump land 5h from the microcomputer chip 1 are connected to the lower-side wiring layer 5e on the lower side of the microcomputer chip 1. The second wiring 5m, the pad 1c connected to the memory connection input / output circuit 1f of the microcomputer chip 1 and the pad 2c of the flash memory 2 are connected via the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d. By arranging the third wiring 5p connected to the bump land 5h and connected to the second wiring 5n and the second wiring 5n, the top of the microcomputer chip 1 is arranged. Therefore, the number of wiring layers of the package substrate 5 can be reduced as compared with a semiconductor device having a structure in which all semiconductor chips are mounted on a conventional wiring substrate. be able to.

  The SIP 4 is provided with, for example, 116 external terminals (solder balls 8) connected to the external connection input / output circuit 1e, and the external terminals (solder) connected to the memory connection input / output circuit 1f. For example, 67 balls 8) are provided. That is, the number of external terminals connected to the external connection input / output circuit 1e (116)> the number of external terminals connected to the memory connection input / output circuit 1f (67).

  Next, details of the wiring pattern of each wiring layer of the package substrate 5 incorporated in the SIP 4 will be described.

  3 is the uppermost wiring layer of the package substrate 5, FIG. 5 is the second wiring layer from the top (main surface 5a side), FIG. 6 is the third wiring layer from the top, and FIG. 7 is the fourth wiring layer from the top. The wiring layer, FIG. 8 shows the fifth wiring layer from the top, and FIG. 9 shows the sixth wiring layer from the top, each showing the wiring pattern in each layer.

  The uppermost wiring layer, the second wiring layer from the top, and the third wiring layer from the top are the main surface side wiring layer 5d, and the fourth, fifth and sixth wiring layers from the top are the back surface side. This is the wiring layer 5e. As shown in the enlarged views of FIGS. 3 and 4, the uppermost wiring layer includes a plurality of terminals 5u connected to the pads 2c and 3c of the flash memory 2 and the DRAM 3 via wires 6, and these terminals 5u. A wiring 5j to be connected is provided.

  In addition, as shown in FIG. 5, the second wiring layer is provided with a plurality of wirings 5j serving as relay wirings to the uppermost wiring layer and the third wiring layer. As shown in FIG. 6, the wiring layer is provided with a GND plane 5q which is a plane wiring having a ground (GND) potential over substantially the entire surface. That is, the third wiring layer is a GND layer that extends almost over the entire surface. However, in the third wiring layer, a plurality of through-hole wirings 5g for signals and the like are provided in a state insulated from the GND plane 5q. The GND plane 5q is provided with a plurality of GND through holes 5s, which are first connection conductor portions having a ground potential, along the outer peripheral portion thereof.

  In the fourth wiring layer, as shown in FIG. 7, a power supply plane 5r and a power supply wiring 5v, which are plane wirings of the power supply potential, are provided. That is, the fourth wiring layer is a power supply layer. However, the fourth wiring layer is provided with a plurality of through-hole wirings 5g for signals and the like in a state insulated from the power supply plane 5r. The fourth wiring layer is provided with a plurality of GND through holes 5s along the outer peripheral portion thereof and insulated from the power supply plane 5r. Further, since the main surface 1a of the microcomputer chip 1 is disposed near the center of the fourth wiring layer, a wiring prohibited area 5w is formed.

  Further, as shown in FIG. 8, the fifth wiring layer includes a plurality of terminals 5x connected to the pads 1c of the microcomputer chip 1 through the gold bumps 1d, wirings 5k connected to the terminals 5x, and a rectangular shape. A GND plane 5q, which is a plane wiring having a GND potential, is provided in an inner region of the plurality of arranged terminals 5x. In other words, the GND plane 5q of the GND potential is provided at a location facing the main surface 1a of the microcomputer chip 1 of the fifth wiring layer in the back surface side wiring layer 5e. This makes it possible to shield EMI noise emitted from the SIP chip, particularly from the microcomputer chip 1, and improve the EMI characteristics of the SIP 4. As shown in FIG. 10, the GND plane 5q is connected to the GND terminal 5y connected to the GND pad 1c of the microcomputer chip 1 by the wiring 5k. By leaving a gap enough to allow one wiring 5k to pass through to the GND plane 5q, it is possible to improve the routing performance of the wiring 5k without impairing the shielding performance against EMI.

  Further, as shown in FIG. 9, the sixth wiring layer is provided with a plurality of bump lands 5h connected to the solder balls 8 as external terminals and wiring 5k connected to each bump land 5h. . The plurality of bump lands 5h are provided in a matrix arrangement except for the central portion, and the arrangement of the bump lands 5h is the arrangement of the solder balls 8 which are external terminals.

  In the SIP 4 according to the first embodiment, on the package substrate 5, a plurality of first wirings 5 m connected directly from the microcomputer chip 1 to the bump land 5 h are formed on the back-side wiring layer 5 e below the microcomputer chip 1. A second wiring 5n for connecting the pad 1c connected to the memory connection input / output circuit 1f and the pad 2c of the flash memory 2 via the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d; And a third wiring 5p connected to the bump land 5h.

  The first to third wirings 5m, 5n, and 5p will be specifically described by way of an example. A wiring 5j connected to the flash memory terminal 5u of the C portion of the uppermost wiring layer shown in FIG. The wiring 5j connected to the DRAM terminal 5u is connected via the wiring 5j and via wiring 5t in the second wiring layer shown in FIG. 12, and further, the wiring 5j in the D part in FIG. It is connected to the wiring 5j of the F section shown in FIG. 12 via the via wiring 5t at the end.

  The wiring 5j in the F part shown in FIG. 12 is connected to the wiring 5j in the G part of the third wiring layer shown in FIG. 13 via the via wiring 5t, and further passes through the core layer 5c via the through-hole wiring 5g. Then, the second wiring 5n in the H portion connected to the through hole wiring 5g in the H portion of the fourth wiring layer shown in FIG. 14 and further connected to the through hole wiring 5g is shown in FIG. 15 via the via wiring 5t. The second wiring 5n of the I part of the fifth wiring layer shown is connected, and the second wiring 5n of the I part is connected to the terminal 5x for the microcomputer chip.

  Since the insulating layer of the core layer 5c is larger than the insulating layer 5i of the buildup layer, the through hole (through hole 5f) formed in the core layer 5c is larger than the via hole formed in the buildup layer. Become. Therefore, to reduce the size of the semiconductor device (SIP4), it is effective to reduce the number of through-hole wirings 5g.

  Further, in the I portion, the second wiring 5n is connected to the third wiring 5p, and the J portion of the sixth wiring layer shown in FIG. 16 is connected to the end of the third wiring 5p via the via wiring 5t. The third wiring 5p is connected to the bump land 5h. In this way, the wiring between the microcomputer chip, the memory chip, and the bump land is formed.

  In addition, in the K portion of the fifth wiring layer shown in FIG. 15, the microcomputer chip terminal 5x and the first wiring 5m are connected, and the first wiring 5m is connected to the FIG. 16 via the via wiring 5t. The first wiring 5m is connected to the bump land 5h, which is connected to the first wiring 5m in the L portion of the sixth wiring layer shown. Thus, the wiring between the microcomputer chip and the bump land is formed, and a plurality of the first wirings 5m of the wiring between the microcomputer chip and the bump land are formed only on the back surface side wiring layer 5e, and the through-hole wiring is formed. 5g and the wiring 5j of the main surface side wiring layer 5d are not connected.

  As described above, in the SIP 4 according to the first embodiment, the microcomputer chip 1 is embedded in the core layer 5c of the package substrate 5, and the wiring 5j of the main surface side wiring layer 5d disposed on the upper side of the microcomputer chip 1; The wiring 5k of the back surface side wiring layer 5e disposed on the lower side is connected through the through hole wiring 5g of the core layer 5c, and the back surface side wiring layer 5e is connected to the external connection input / output circuit 1e of the microcomputer chip 1. The microcomputer includes the first wiring 5m that connects the pad 1c to be connected to the bump land 5h on the back surface 5b side and is not connected to the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d. The wiring 5k connected to the chip 1 can be disposed only on the back surface side wiring layer 5e.

  With such a configuration, of the wirings 5j and 5k formed on the package substrate 5, the wiring for connecting the external connection input / output circuit 1e of the microcomputer chip 1 and the bump land 5h constituting the external terminal ( The first wiring 5m) can be configured without being connected to the through-hole wiring 5g having a large diameter, and the number of through-hole wirings 5g formed on the package substrate 5 can be reduced. Therefore, the package substrate 5 can be reduced in size.

  Further, the wirings 5j and 5k on the package substrate 5 can be distributed and arranged in the main surface side wiring layer 5d and the back surface side wiring layer 5e, thereby reducing the number of wiring layers on the package substrate 5. it can.

  Therefore, the package substrate 5 can be reduced in thickness, whereby the semiconductor device such as the SIP 4 can be reduced in size.

  Furthermore, since the number of wiring layers in the package substrate 5 can be reduced, the cost of the package substrate 5 can be reduced. As a result, the cost of a semiconductor device such as SIP 4 can be reduced.

  Further, as shown in FIGS. 10, 15 and 17, a GND plane 5q which is a plane wiring of the ground potential is formed at a location facing the main surface 1a of the microcomputer chip 1 in the back surface side wiring layer 5e of the package substrate 5. As a result, the shielding effect can be improved and EMI can be reduced. As a result, the electrical characteristics of SIP 4 can be improved.

  In the SIP 4 of the first embodiment, the GND plane 5q is formed over the entire surface of the package substrate 5 on the third wiring layer on the back surface 1b side (upper side) of the microcomputer chip 1 as shown in FIG. In addition, since the power plane 5r is formed in the fourth wiring layer, the microcomputer chip 1 can be surrounded by the GND plane 5q and the power plane 5r. Thereby, the shielding effect can be further improved. As a result, EMI can be further reduced.

  In SIP4, the wiring (first wiring 5m) for connecting the external connection input / output circuit 1e of the microcomputer chip 1 and the bump land 5h constituting the external terminal is not connected to the through-hole wiring 5g. By configuring, the number of through-hole wirings 5g for configuring connection wirings other than GND in the package substrate 5 can be reduced. Therefore, a plurality of GND through-holes having a GND potential in the core layer 5c of the package substrate 5 ( The first connecting conductor portion 5s can be formed. At this time, EMI can be reduced by forming a plurality of GND through holes 5s around the microcomputer chip 1, preferably along the outer periphery of the GND plane 5q as shown in FIGS. As a result, the electrical characteristics of SIP 4 can be improved.

Here, an example of the arrangement pitch of the GND through holes 5s formed in the core layer 5c will be described. For example, when the SIP 4 is mounted on a mobile phone or the like, the noise wavelength (L) is L = C / (ε _r ^1/2 × f), C is the speed of light, C = 3 × 10 ¹¹ mm / s, ε _r is the dielectric constant of the resin, ε _r ≈4, f is the frequency of the noise to be cut, and f = When calculated as 2.5 × 10 ⁹ Hz, L≈50 mm. Furthermore, L is set to 1/10 of the calculated value including a sufficient margin for preventing noise from passing. That is, by setting the interval (arrangement pitch) between adjacent GND through holes 5s in the core layer 5c to 5 mm or less, noise can be reliably cut in the mobile phone, and the electrical characteristics of the SIP 4 can be improved. Thus, the reliability of the portable telephone can be improved.

  An example of a method for manufacturing a wiring board in which a semiconductor chip such as the microcomputer chip 1 is embedded is described in Patent Document 3 (Japanese Patent Laid-Open No. 2003-309243).

(Embodiment 2)
FIG. 19 is a sectional view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention, and FIG.
FIG. 9 is a block configuration diagram showing an example of a system of the semiconductor device shown in FIG.

  The semiconductor device according to the second embodiment shown in FIG. 19 has a semiconductor chip embedded in a package substrate 5 which is a wiring substrate. The microcomputer chip 1 is embedded in the package substrate 5 and the main surface of the package substrate 5 is also embedded. The structure is such that another semiconductor device having a semiconductor chip such as a memory chip can be connected to the 5a side, and another semiconductor device having a memory chip is connected on the user side after shipment, which will be described in the first embodiment. The semiconductor device (System In Package) similar to the SIP 4 can be manufactured.

  The detailed structure of the semiconductor device shown in FIGS. 19 and 20 will be described. The main surface 1a has a semiconductor element and a plurality of pads 1c, and has an arithmetic processing function, a memory connection input / output circuit 1f, and an external connection. A microcomputer chip (first semiconductor chip) 1 which is a CPU (Central Processing Unit) having an input / output circuit 1e, a package substrate 5 which is a wiring substrate, and external terminal mounting electrodes on the back surface 5b side of the package substrate 5. This is a BGA (Ball Grid Array) type semiconductor device 9 including a plurality of solder balls 8 connected to a certain bump land 5h (see FIG. 9).

  The package substrate 5 is disposed on the main surface 5a side with respect to the main surface 5a, the opposite back surface 5b, the insulating core layer 5c disposed between the main surface 5a and the back surface 5b, and the core layer 5c. The main surface side wiring layer 5d, the back surface side wiring layer 5e disposed on the back surface 5b side from the core layer 5c, and the through-hole wiring disposed in the through hole 5f formed through the core layer 5c ( And a plurality of bump lands 5h (see FIG. 9) disposed only on the back surface 5b. The wiring 5j of the main surface side wiring layer 5d and the wiring 5k of the back surface side wiring layer 5e are provided. Are electrically connected by through-hole wiring 5g.

  Further, in each of the main surface side wiring layer 5d and the back surface side wiring layer 5e, the wirings 5j and the wirings 5k are arranged via the insulating layer 5i, and the wirings 5j of the adjacent layers and the wirings 5k are connected to the via wiring 5t. It is electrically connected via.

  Further, the microcomputer chip 1 which is the first semiconductor chip is arranged on the core layer 5c of the package substrate 5 with the main surface 1a facing the back surface 5b side of the package substrate 5, and the microcomputer chip 1 has a pad 1c and a back surface. The wiring 5k of the side wiring layer 5e is electrically connected through the gold bump 1d. That is, the microcomputer chip 1 is disposed on the core layer 5c with its main surface 1a facing downward and the back surface 1b facing upward. Therefore, the main surface 1a and the back surface side wiring layer 5e face each other.

  In the core layer 5c, a plurality of through-hole wirings 5g are formed around the microcomputer chip 1.

  Further, a pad 1c connected to the external connection input / output circuit 1e shown in FIG. 20 in the microcomputer chip 1 and a bump land 5h corresponding thereto are electrically connected to the back surface side wiring layer 5e of the package substrate 5. In addition, a plurality of first wirings 5m that are not connected to the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d are provided.

  That is, the first wiring 5m is not arranged in the main surface side wiring layer 5d, but only in the back surface side wiring layer 5e, as in the SIP 4 of the first embodiment, and is provided in the core layer 5c. Between any of the through-hole wirings 5g and the wiring 5j of the main-surface-side wiring layer 5d, the pad 1c connected to the external connection input / output circuit 1e of the microcomputer chip 1 to the corresponding bump land 5h Are connected only on the back surface side wiring layer 5 e, and also in the BGA type semiconductor device 9, many such first wirings 5 m are provided only on the back surface side wiring layer 5 e of the package substrate 5.

  Furthermore, the main surface 5a of the package substrate 5 of the BGA type semiconductor device 9 of the second embodiment is electrically connected to other semiconductor devices such as a CSP (Chip Size Package) 10 having a semiconductor chip provided with a memory circuit. A plurality of connection electrodes 5z that can be connected are provided.

  Further, on the back surface side wiring layer 5e, a pad 1c connected to the memory connection input / output circuit 1f of the microcomputer chip 1 and a connection electrode 5z of the main surface side wiring layer 5d are connected to the through-hole wiring 5g and the main surface side wiring. A second wiring 5n that is electrically connected via the wiring 5j of the layer 5d is disposed. Further, the second wiring 5n is connected to the third wiring 5p connected to the bump land 5h in the back surface side wiring layer 5e.

  The plurality of solder balls 8 that are external terminals for exchanging signals with the outside of the BGA type semiconductor device 9 are all arranged only on the back surface 5b side of the package substrate 5.

  The other semiconductor device connected on the package substrate 5 on the user side may be a package product in which a semiconductor chip or the like is sealed, or a bare chip product in which the semiconductor chip is exposed. Good. Further, the electrical connection to the package substrate 5 of another semiconductor device via the connection electrode 5z may be flip-chip connection or wire connection.

  Therefore, the connection electrode 5z of the package substrate 5 has a gold plating layer or a solder plating layer formed on the surface thereof.

  However, if the solder ball 8 is provided on the back surface 5b side of the package substrate 5 as in the BGA type semiconductor device 9 shown in FIG. 19, it is difficult to perform wire bonding on the main surface 5a side. The connection of another semiconductor device on the side of the surface 5a is preferably flip-chip connection via the bump electrode 11, and as a result, the connection electrode 5z is preferably a flip-chip connection electrode.

  Next, the system configuration of the BGA type semiconductor device 9 shown in FIG. 20 will be described. The microcomputer chip 1 inputs / outputs data between the outside of the system and a memory chip connected later to the system. Is controlling. Therefore, the external connection input / output circuit 1e and the memory connection input / output circuit 1f are provided, and the logical address for the external connection input / output circuit 1e is converted into an address for the memory chip.

  That is, information such as an address, a command, and a clock is exchanged with the memory chip.

  Also in the BGA type semiconductor device 9 of the second embodiment, like the SIP 4 of the first embodiment, the pad 1c connected to the external connection input / output circuit 1e of the microcomputer chip 1 and the bump land 5h ( The solder ball 8) is connected to the first wiring 5m disposed only on the back surface side wiring layer 5e. Furthermore, the pad 1c connected to the memory connection input / output circuit 1f of the microcomputer chip 1 and the connection electrode 5z of the main surface side wiring layer 5d are the second wiring 5n and the through hole wiring 5g of the back surface side wiring layer 5e. The main surface side wiring layer 5d is connected via the wiring 5j. Further, a third wiring 5p that connects the second wiring 5n and the bump land 5h (solder ball 8) is formed on the back surface side wiring layer 5e.

  As for the wiring pattern of each wiring layer of the package substrate 5 of the BGA type semiconductor device 9, only the terminal 5u in the wiring pattern of the uppermost wiring layer shown in FIG. The wiring pattern of each wiring layer from the first layer to the sixth layer is the same as that of the package substrate 5 of the SIP 4 of the first embodiment.

  Thus, in the BGA type semiconductor device 9 of the second embodiment, by connecting another semiconductor device such as the CSP 10 to the main surface 5a of the package substrate 5 on the user side, similarly to the SIP 4 of the first embodiment, The microcomputer chip 1 is arranged in the core layer 5c of the package substrate 5, the main surface 1a of the microcomputer chip 1 is arranged toward the external terminal side, and the memory chip is further connected to the main surface side wiring layer 5d on the upper side of the microcomputer chip 1. The related wiring 5j is arranged, and a plurality of first wirings 5m connected directly from the microcomputer chip 1 to the bump land 5h are connected to the lower-side wiring layer 5e on the lower side of the microcomputer chip 1, and input / output for memory connection of the microcomputer chip 1 The pad 1c connected to the circuit 1f is connected to the connection electrode 5z of the main surface side wiring layer 5d through the through-hole wiring 5g and the wiring 5j of the main surface side wiring layer 5d. The second wiring 5n and the third wiring 5p connected to the bump land 5h and the second wiring 5n can be arranged. Therefore, all the wiring is provided on the upper side and the lower side of the microcomputer chip 1. It can be distributed.

  As a result, the number of wiring layers of the package substrate 5 can be reduced as compared with a semiconductor device having a structure in which all semiconductor chips are mounted on a conventional wiring substrate, thereby reducing the size of the BGA type semiconductor device 9. Can be achieved.

  Since the other structure of the BGA type semiconductor device 9 of the second embodiment and the other effects obtained thereby are the same as those of the SIP 4 of the first embodiment, a duplicate description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first and second embodiments, the case where the package substrate 5 has six wiring layers has been described as an example. However, the number of wiring layers is the first number embedded in the package substrate 5. Any number of layers may be used as long as the main surface side wiring layer 5d and the back surface side wiring layer 5e are arranged separately on the upper side and the lower side of the semiconductor chip.

  In the first and second embodiments, the case where the semiconductor device has the solder ball 8 as an external terminal has been described as an example. However, the external terminal is connected to one surface of the package substrate 5 (for example, As long as they are all provided on the back surface 5b) side, they may be other than the solder balls 8, and the semiconductor device may be, for example, an LGA (Land Grid Array) type.

  The present invention is suitable for electronic devices and semiconductor devices.

It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. It is a block block diagram which shows an example of the system of the semiconductor device shown in FIG. FIG. 2 is a plan view showing an example of a wiring pattern of an uppermost wiring layer of a wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 4 is an enlarged partial plan view showing an A portion shown in FIG. 3 in an enlarged manner. FIG. 2 is a plan view showing an example of a wiring pattern of a second wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 2 is a plan view showing an example of a wiring pattern of a third wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing an example of a wiring pattern of a fourth wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing an example of a wiring pattern of a fifth wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 2 is a plan view showing an example of a wiring pattern of a sixth wiring layer from the top of the wiring board incorporated in the semiconductor device shown in FIG. 1. FIG. 9 is an enlarged partial plan view showing a plane wiring of a ground potential in the wiring pattern shown in FIG. 8 and a wiring pattern around it. FIG. 4 is an enlarged partial plan view showing an example of wiring between a microcomputer chip and a memory chip in the wiring pattern of the uppermost wiring layer shown in FIG. 3. FIG. 6 is an enlarged partial plan view showing an example of wiring between a microcomputer chip and a memory chip in the wiring pattern of the second wiring layer shown in FIG. 5. FIG. 7 is an enlarged partial plan view showing an example of wiring between a microcomputer chip and a memory chip in the wiring pattern of the third wiring layer shown in FIG. 6. FIG. 8 is an enlarged partial plan view showing an example of wiring between a microcomputer chip and a memory chip in the wiring pattern of the fourth wiring layer shown in FIG. 7. FIG. 9 is an enlarged partial plan view showing an example of a wiring between a microcomputer chip and a memory chip and a wiring between a microcomputer chip and a solder ball in the wiring pattern of the fifth wiring layer shown in FIG. 8. FIG. 10 is an enlarged partial plan view showing an example of a wiring between a microcomputer chip and a memory chip and a wiring between a microcomputer chip and a solder ball in the wiring pattern of the sixth wiring layer shown in FIG. 9. FIG. 2 is a cross-sectional view illustrating an example of a structure in which the semiconductor device illustrated in FIG. 1 is cut on a ground wiring having a ground potential. FIG. 2 is a cross-sectional view showing an example of a structure obtained by cutting the semiconductor device shown in FIG. 1 on a through-hole wiring having a ground potential. It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. FIG. 20 is a block configuration diagram illustrating an example of a system of the semiconductor device illustrated in FIG. 19.

Explanation of symbols

1 Microcomputer chip (first semiconductor chip)
1a main surface 1b back surface 1c pad (electrode)
1d Gold bump 1e Input / output circuit for external connection 1f Input / output circuit for memory connection 2 Flash memory (second semiconductor chip)
2a Main surface 2b Back surface 2c Pad (electrode)
3 DRAM (second semiconductor chip)
3a main surface 3b back surface 3c pad (electrode)
4 SIP (semiconductor device)
5 Package board (wiring board)
5a Main surface 5b Back surface 5c Core layer 5d Main surface side wiring layer 5e Back surface side wiring layer 5f Through hole 5g Through-hole wiring (connection conductor)
5h Bump land (external terminal mounting electrode)
5i Insulating layer 5j, 5k wiring 5m first wiring 5n second wiring 5p third wiring 5q GND plane (plane wiring)
5r power plane (plane wiring)
5s GND through hole (first connecting conductor)
5t via wiring 5u terminal 5v power supply wiring 5w wiring prohibited area 5x terminal 5y GND terminal 5z connection electrode 6 wire (metal fine wire)
7 Sealing body 8 Solder ball (external terminal)
9 BGA type semiconductor device 10 CSP (other semiconductor devices)
11 Bump electrode

Claims (22)

A first main surface, the first semiconductor element formed on the first main surface, is formed on the peripheral portion of the first major surface, the first semiconductor element and electrically connected to the first pad, and have a first back surface opposite the first major surface, a first semiconductor chip having an arithmetic processing function,
Front surface, and has a back surface of said surface opposite the front SL core layer which seals the first semiconductor chip, between the rear surface of the surface and the core layer of the core layer, said first A first through- hole formed around the semiconductor chip; a second through-hole formed around the first semiconductor chip between the front surface of the core layer and the back surface of the core layer; A first conductor portion formed in the through hole, a second conductor portion formed in the second through hole, and a first conductor portion connected to the first conductor portion and formed on the surface of the core layer. 1 wiring layer, connected to the second conductor part, and connected to the first conductor part, a first GND plane having a reference potential formed in a region facing the first semiconductor chip on the surface of the core layer. the second wiring layer formed on the back surface of the core layer, and the second Is connected to the conductor portion, a wiring board having a first 2GND plane having a reference potential formed in the first semiconductor chip opposite to the region on the back surface of the core layer,
Second main surface, a second semiconductor element formed on the second main surface, is formed on the second major surface, said second semiconductor element and electrically connected to the second pad, and the second a second back surface of the main surface opposite, comprising a memory circuit, the second pad and the first wiring layer of the wiring substrate are electrically connected, it mounted on the first wiring layer A second semiconductor chip;
Said second wiring layer and is electrically connected, a first external terminal formed on the second wiring layer,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising: a first insulating film formed on the first wiring layer; a first insulating film formed on the first wiring layer; and a portion of the first wiring layer formed on the first wiring layer. An exposed second through hole, a second conductor portion formed in the second through hole, and a third wiring layer connected to the second conductor portion and formed on the first insulating film. And the second pad of the second semiconductor chip is electrically connected to the third wiring layer.   3. The semiconductor device according to claim 2, wherein a diameter of the first through hole is larger than a diameter of the second through hole.   3. The semiconductor device according to claim 2, wherein the second pad of the second semiconductor chip and the third wiring layer of the wiring substrate are electrically connected through a fine metal wire. .   2. The semiconductor device according to claim 1, wherein the first semiconductor chip further includes a third pad formed on the first main surface and electrically connected to the first semiconductor element. The substrate is formed on the fourth wiring layer connected to the third pad, the second insulating film formed on the second wiring layer and the fourth wiring layer, and the second insulating film, A third through hole exposing a part of the fourth wiring layer, a third conductor portion formed inside the third through hole, and connected to the third conductor portion and formed on the second insulating film And the first external terminal is formed on the fifth wiring layer and electrically connected to the fourth wiring layer via the fifth wiring layer and the third conductor portion. A semiconductor device which is connected.   6. The semiconductor device according to claim 5, wherein the diameter of the first through hole is larger than the diameter of the third through hole.   6. The semiconductor device according to claim 5, wherein the first pad of the first semiconductor chip is electrically connected to the second wiring layer through a first gold bump, and the third pad of the first semiconductor chip. Is electrically connected to the fourth wiring layer via a second gold bump.   6. The semiconductor device according to claim 5, further comprising: a fourth through hole formed in the second insulating film and exposing a part of the second wiring layer, and an inside of the fourth through hole. A fourth conductor portion formed; and a sixth wiring layer connected to the fourth conductor portion and formed on the second insulating film; and a second external terminal formed on the sixth wiring layer. The semiconductor device is electrically connected to the second wiring layer through the sixth wiring layer and the fourth conductor portion. 2. The semiconductor device according to claim 1, wherein the first semiconductor element of the first semiconductor chip is electrically connected to the input / output circuit for memory connection electrically connected to the first pad and to the third pad. wherein a is closed and the external connection input-output circuits.   9. The semiconductor device according to claim 8, wherein each of the first external terminal and the second external terminal is a solder ball.   2. The semiconductor device according to claim 1, wherein the second semiconductor chip is sealed with a sealing body. 2. The semiconductor device according to claim 1, wherein the first semiconductor chip is disposed in the core layer such that the first main surface of the first semiconductor chip faces the back surface.
The semiconductor device according to claim 1, wherein the first pad of the first semiconductor chip is electrically connected to the first conductor portion through the second wiring layer . 13. The semiconductor device according to claim 12, wherein the core layer is made of an insulating material,
The semiconductor device, wherein the core layer is disposed between the first back surface of the first semiconductor chip and the first GND plane .   2. The semiconductor device according to claim 1, wherein the third main surface, the third semiconductor element formed on the third main surface, and the third semiconductor element are formed on the third main surface and electrically connected to the third semiconductor element. A third pad of a third semiconductor chip having a third pad and a third back surface opposite to the third main surface is electrically connected to the first wiring layer of the wiring substrate; A semiconductor device mounted on one wiring layer next to the second semiconductor chip.   15. The semiconductor device according to claim 14, wherein the third pad of the third semiconductor chip and the first wiring layer of the wiring board are electrically connected through a fine metal wire. .   15. The semiconductor device according to claim 14, wherein the third semiconductor element of the third semiconductor chip includes a second memory circuit electrically connected to the third pad.   15. The semiconductor device according to claim 14, wherein the third semiconductor chip is a DRAM. 2. The semiconductor device according to claim 1, wherein the first semiconductor chip is a microcomputer chip, and the second semiconductor chip is a flash memory.   5. The semiconductor device according to claim 4, wherein the second semiconductor chip and the fine metal wire are sealed with a sealing body.   6. The semiconductor device according to claim 5, wherein data input from outside the semiconductor device includes the first external terminal, the fifth wiring layer, the third conductor portion, the fourth wiring layer, and the third pad. The first pad, the second wiring layer, the first conductor part, the first wiring layer, and the second data are supplied to the first semiconductor element through the first semiconductor element and converted by the first semiconductor element. A semiconductor device, wherein the semiconductor device is supplied to the second semiconductor element through a pad. The semiconductor device according to claim 1, wherein the second through hole is formed in an outer peripheral portion of the wiring board rather than the first through hole. 2. The semiconductor device according to claim 1, wherein the first wiring layer is not formed between the first semiconductor chip and the first GND plane.
The semiconductor device, wherein the second wiring layer is not formed between the first semiconductor chip and the second GND plane.

Images