JP3033662B2 - Semiconductor element mounting film and semiconductor element mounting structure - Google Patents
Semiconductor element mounting film and semiconductor element mounting structureInfo
- Publication number
- JP3033662B2 JP3033662B2 JP6086646A JP8664694A JP3033662B2 JP 3033662 B2 JP3033662 B2 JP 3033662B2 JP 6086646 A JP6086646 A JP 6086646A JP 8664694 A JP8664694 A JP 8664694A JP 3033662 B2 JP3033662 B2 JP 3033662B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- film
- insulating film
- circuit pattern
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を実装する絶
縁性フィルムの構成およびこれを利用した半導体素子の
実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an insulating film for mounting a semiconductor device and a mounting structure of the semiconductor device using the same.
【０００２】[0002]
【従来の技術】半導体素子の集積度の向上、および半導
体素子のサイズの増大に伴って、入出力端子数も増大し
ている。図７に示されるように、従来の半導体素子の実
装構造では、半導体素子の入出力端子数の増大に対応す
るため、半導体素子９の周囲四辺に入出力端子用リード
２４が設けられたＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃ
ｋａｇｅ）と呼ばれる構造が一般的に採用されている。
しかしながら、入出力端子数の増大に伴い端子間のリー
ドピッチが狭くなり、基板への高度な実装技術が要求さ
れてきている。2. Description of the Related Art As the degree of integration of semiconductor devices and the size of semiconductor devices increase, the number of input / output terminals also increases. As shown in FIG. 7, in the conventional mounting structure of a semiconductor device, in order to cope with an increase in the number of input / output terminals of the semiconductor device, a QFP ( Quad Flat Pac
A structure called “kage” is generally adopted.
However, as the number of input / output terminals increases, the lead pitch between the terminals becomes narrower, and a sophisticated mounting technique on a substrate is required.
【０００３】このような半導体素子の入出力端子数の増
大に対応して入出力端子のリードピッチを緩和する構造
として、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と
呼ばれる実装構造がある。図６に示されるように、ＢＧ
Ａはプラスチック基板１８の両面に回路パターン２０お
よび２１が形成されている。半導体素子９が搭載された
面にある、半導体素子９の外部接続用電極とプラスチッ
ク基板１８に設けられた回路パターン２０は細線の金線
２２などによってワイヤーボンディングされ電気的に接
続されている。プラスチック基板１８の他方の面には、
２次元のアレイ状に配置された球状半田８が回路パター
ン２１の先端に設けられており、プラスチック基板１８
に設けられたスルーホール１９により半導体素子９の外
部接続用電極と球状半田８が電気的に接続されている。
さらに、ＢＧＡ構造の半導体装置と親基板とは、球状半
田８を介して電気的に接続される。ＢＧＡ構造では、面
内に球状半田８が配列されるので、周囲に配置されるよ
りも面積を大きくとることができ、従来の周囲四辺に入
出力端子を設けるＱＦＰのリードピッチに比較して、接
続のピッチをかなり緩和することができる。As a structure for reducing the lead pitch of the input / output terminals in response to the increase in the number of input / output terminals of the semiconductor element, there is a mounting structure called a BGA (Ball Grid Array). As shown in FIG.
In A, circuit patterns 20 and 21 are formed on both surfaces of a plastic substrate 18 . The external connection electrode of the semiconductor element 9 on the surface on which the semiconductor element 9 is mounted and the circuit pattern 20 provided on the plastic substrate 18 are wire-bonded by a thin gold wire 22 or the like and are electrically connected. On the other surface of the plastic substrate 18,
The spherical solder 8 arranged in a two-dimensional array is provided at the tip of the circuit pattern 21, and a plastic substrate 18 is provided.
The electrodes for external connection of the semiconductor element 9 and the spherical solder 8 are electrically connected by through holes 19 provided in the semiconductor device 9.
Further, the semiconductor device having the BGA structure and the mother board are electrically connected via the spherical solder 8. In the BGA structure, since the spherical solders 8 are arranged in the plane, the area can be larger than that arranged around the periphery, and compared with the conventional lead pitch of the QFP in which the input / output terminals are provided on the four sides of the periphery, The pitch of the connection can be considerably reduced.
【０００４】[0004]
【発明が解決しようとする課題】上述のようなＢＧＡ構
造の半導体装置では以下のような課題がある。The semiconductor device having the above-described BGA structure has the following problems.
【０００５】まず第１に、ＢＧＡ全体の寸法を小型化す
る場合、半導体素子の寸法に対してプラスチック基板へ
の電気的な接続を行うワイヤーボンディングの領域と裏
面に電気的に接続するためのスルーホールの領域が必要
であるため、小型化に限界がある。First, when the size of the entire BGA is reduced, the size of the semiconductor element is reduced by a wire bonding area for making an electrical connection to a plastic substrate and a through-hole for electrically connecting to the back surface. Since a hole area is required, there is a limit to miniaturization.
【０００６】また、ワイヤーボンディングが行えるピッ
チは現状２００μｍ程度であるため、端子数が多くなる
ほど半導体素子の周囲に設けられたワイヤーボンディン
グ領域が大きくなり、小型化の支障となる。Further, since the pitch at which wire bonding can be performed is currently about 200 μm, as the number of terminals increases, the wire bonding area provided around the semiconductor element increases, which hinders miniaturization.
【０００７】さらに、裏面への電気的接続のスルーホー
ルは球状半田を構成した部分に設けることができないた
め周囲に配置することになり、小型化の支障となる。Further, since a through hole for electrical connection to the back surface cannot be provided in a portion where the spherical solder is formed, the through hole is disposed around, which hinders miniaturization.
【０００８】第２に、ＢＧＡの構造で構成した場合の電
気的な試験に工夫が必要なことである。すなわち、半導
体素子が実装された後に行う電気的試験は信頼性を確保
するために不可欠であるが、球状半田に対し変形を起こ
さないように接触し、かつ電気特性を図るには測定用の
ソケットに工夫が必要であり、狭ピッチになるほど測定
が困難になるという問題がある。球状半田を変形させた
場合、半田高さがばらつくことにより、半導体素子が実
装された基板が親基板に搭載された際に接続不良を起こ
すという問題がある。Secondly, it is necessary to devise an electrical test in the case of a BGA structure. That is, the electrical test performed after the semiconductor element is mounted is indispensable to ensure the reliability, but it is necessary to make contact with the spherical solder so as not to deform and to measure the electrical characteristics by using a measuring socket. Therefore, there is a problem that the narrower the pitch, the more difficult the measurement becomes. When the spherical solder is deformed, there is a problem that, due to the variation in solder height, a connection failure occurs when the substrate on which the semiconductor element is mounted is mounted on the parent substrate.
【０００９】第３に、半導体素子から発熱する熱に対す
る放熱構造に関する課題である。ＢＧＡ構造では、ＢＧ
Ａを搭載する親基板に対して半導体素子の回路面が上向
きとなるため、半導体素子から発生する熱は半導体素子
の裏面から親基板へ放熱するしか手段がない。このた
め、電気的接続以外に放熱用の球状半田を設ける必要性
があり、また親基板の熱伝導率を考慮しなければなら
ず、十分な放熱をとることが困難であるという問題があ
る。Third, there is a problem relating to a heat dissipation structure for heat generated from the semiconductor element. In the BGA structure, BG
Since the circuit surface of the semiconductor element faces upward with respect to the parent substrate on which A is mounted, there is no alternative but to radiate the heat generated from the semiconductor element to the parent substrate from the back surface of the semiconductor element. For this reason, it is necessary to provide a spherical solder for heat dissipation in addition to the electrical connection, and it is necessary to consider the thermal conductivity of the parent board, and there is a problem that it is difficult to obtain sufficient heat dissipation.
【００１０】本発明の半導体素子実装用フィルムと半導
体素子の実装構造は、上記欠点に鑑みて、小型で放熱に
優れ、しかも良好な接続が得られる半導体素子実装用フ
ィルムと半導体素子実装構造を提供することにある。In view of the above-mentioned drawbacks, the semiconductor element mounting film and the semiconductor element mounting structure of the present invention provide a semiconductor element mounting film and a semiconductor element mounting structure which are small in size, have excellent heat dissipation, and can obtain good connection. Is to do.
【００１１】[0011]
【課題を解決するための手段】上述の課題を解決するた
めに、本発明の半導体素子実装用フィルムは、第１の絶
縁性フィルムに第２の絶縁性フィルムが積層された構成
を備えている。第１の絶縁性フィルムは、第１の面の中
央の領域に配列された半田を含む複数の端子と、端子に
接続され第１の絶縁性フィルムの外周から突出して形成
されたリード部を含む第１の回路パターンとを有してい
る。そして、第１の絶縁性フィルムの第２の面、又はこ
の第２の面に固着される第２の絶縁性フィルムの第１の
面に、第２の回路パターンが形成されており、第１の回
路パターンと前記第２の回路パターンとが電気的に接続
されていることを特徴としている。In order to solve the above-mentioned problems, a semiconductor element mounting film of the present invention has a first
Configuration in which a second insulating film is laminated on an edge film
It has. The first insulating film is in the first surface
Multiple terminals including solder arranged in the center area, and terminals
Connected and formed projecting from the outer periphery of the first insulating film
A first circuit pattern including a lead portion
You. Then, the second surface of the first insulating film or
Of the second insulating film fixed to the second surface of the first
The second circuit pattern is formed on the surface, and the first circuit pattern is formed.
The circuit pattern is electrically connected to the second circuit pattern
It is characterized by being.
【００１２】また、本発明の半導体素子実装構造は、上
記半導体素子実装用フィルムに半導体素子を実装する半
導体素子実装構造であって、半導体素子は第２の絶縁性
フィルムの第２の面の側に配置され、リード部は半導体
素子の表面に形成された外部接続用電極に相対する位置
に形成されており、リード部と外部接続用電極が接触さ
れて半導体素子と半導体素子実装用フィルムが接続され
ていることを特徴としている。 The semiconductor device mounting structure of the present invention
The semiconductor element is mounted on the semiconductor element mounting film in half.
A semiconductor element mounting structure, wherein the semiconductor element has a second insulating property.
The semiconductor device is disposed on the side of the second surface of the film, and the lead portion is a semiconductor.
Position corresponding to the external connection electrode formed on the surface of the device
Contact between the lead and the external connection electrode.
The semiconductor device and the film for mounting the semiconductor device are connected
It is characterized by having.
【００１３】さらに、本発明の半導体素子実装構造は、
上記端子と親基板の表面に形成された基板電極が接続さ
れて半導体実装用フィルムが親基板に固定され、半導体
素子には外部接続用電極が形成された面とは反対の面に
放熱部材が固着されていることを特徴としている。 Further, the semiconductor element mounting structure according to the present invention comprises:
The terminal and the substrate electrode formed on the surface of the parent substrate are connected.
The film for semiconductor mounting is fixed to the mother board
The device has a surface opposite to the surface on which the external connection electrodes are formed.
The heat radiating member is fixed.
【００１４】[0014]
【実施例】次に、本発明を図面を参照して詳細に説明す
る。Next, the present invention will be described in detail with reference to the drawings.
【００１５】図１乃至４は、本発明に用いる半導体素子
実装用フィルムを説明するための参考図である。本発明
の半導体素子実装用フィルムは上述したように、第１及
び第２の絶縁性フィルムの積層構造よりなるが、図１乃
至４はいずれも理解を容易にするために、単層の絶縁性
フィルムから構成された実装用フィルムを示している。
図２は、図３で示される半導体素子実装用フィルムに半
導体素子が接続された状態の縦断面図であり、図１は半
導体素子が実装された半導体素子実装用フィルムが親基
板に搭載する際に、所定の寸法に切断された状態を示す
正面図および縦断面図である。図５は、本発明の半導体
素子実装構造の一実施例の構造を示す縦断面図である。 FIGS. 1 to 4 show a semiconductor device used in the present invention.
It is a reference drawing for explaining a film for mounting. The present invention
As described above, the semiconductor device mounting film of
And a laminated structure of the second insulating film.
Toshiba 4 has a single-layer insulation for easy understanding.
3 shows a mounting film composed of a film.
FIG. 2 is a longitudinal sectional view showing a state in which the semiconductor element is connected to the semiconductor element mounting film shown in FIG. 3, and FIG. 1 shows a state where the semiconductor element mounting film on which the semiconductor element is mounted is mounted on a parent substrate. 2 is a front view and a vertical cross-sectional view showing a state of being cut to a predetermined size. FIG. 5 is a longitudinal sectional view showing the structure of one embodiment of the semiconductor element mounting structure of the present invention .
【００１６】図２においては半導体素子実装用フィルム
１は単層に描かれているが、図５を参照するとわかるよ
うに、本発明の実装用フィルムは、第１の絶縁性フィル
ムと第２の絶縁性フィルムの積層構造からなる。第１の
絶縁性フィルム２の片面には銅箔が貼合わされ、エッチ
ングなどにより回路パターン４が形成されている。図３
では半導体素子実装用フィルム１を長尺として想定して
いるが長尺でなくてもよい。半導体素子実装用フィルム
１の上下には位置合わせや巻き取りに使用する孔（スプ
ロケットホール）３と半導体素子実装用フィルム１の中
央部周囲には回路パターン４の銅箔部の一部をリード部
５として露出させるための孔６が設けられている。ここ
で、リード部５は半導体素子９の外部接続用電極１０の
上に設けた金属突起１１との接続のためにＮｉメッキと
Ａｕメッキなどを施すことが必要であるが、図面上では
省略している。In FIG . 2, the semiconductor element mounting film 1 is depicted as a single layer.
As described above, the mounting film of the present invention comprises a first insulating film.
And a laminated structure of a second insulating film. A copper foil is bonded to one surface of the first insulating film 2, and a circuit pattern 4 is formed by etching or the like. FIG.
Although the semiconductor device mounting film 1 is assumed to be long, the film 1 need not be long. Holes in the top and bottom of the semiconductor element mounting film 1 to be used for aligning and winding (sprocket holes) 3 and the lead portion of the part of the copper foil portion of the semiconductor element mounting film 1 central circuit pattern 4 on the periphery A hole 6 for exposing as 5 is provided. Here, the lead portion 5 needs to be plated with Ni or Au for connection with the metal protrusion 11 provided on the external connection electrode 10 of the semiconductor element 9, but is omitted in the drawing. ing.
【００１７】リード部５の内側には、中央の領域に配置
された球状半田８がリード部５に接続される回路パター
ン４の先端部に設けられている。なお、球状半田８の形
成方法については、定量の半田をパターン上にのせ再溶
融させるなどの方法が一般的に知られている。また、半
田再溶融の時の流れ防止のためのレジストをキャリアフ
ィルム１の回路パターン面に施す必要があるが図面では
省略している。リード部５の外側の周囲にはリード部５
に対応した測定用回路パターン７が配置されている。Inside the lead portion 5, a spherical solder 8 disposed in a central region is provided at the tip of the circuit pattern 4 connected to the lead portion 5. As a method of forming the spherical solder 8, a method of placing a fixed amount of solder on a pattern and re-melting the solder is generally known. Further, a resist for preventing the flow at the time of remelting the solder needs to be applied to the circuit pattern surface of the carrier film 1, but is omitted in the drawing. The lead portion 5 is provided around the outside of the lead portion 5.
Are arranged.
【００１８】次に、図２および図１に示されるように、
リード部５は一部が第１の絶縁性フィルム２の外周から
突出して形成されている。半導体素子９の外部接続用電
極１０の上に形成された金属突起１１とリード部５は位
置合わせされ、熱圧着などの方法によりリード部５と金
属突起１１が接続される。半導体素子９の外部接続用電
極１０に設された金属突起１１の形成方法については、
細線の金ワイヤーを用いててボールを作り熱圧着する方
法や、メッキ法により形成する方法がある。[0018] Next, as shown in Figure 2 and Figure 1,
The lead part 5 is partially from the outer periphery of the first insulating film 2.
It is formed to protrude. The metal protrusion 11 formed on the external connection electrode 10 of the semiconductor element 9 and the lead portion 5 are aligned, and the lead portion 5 and the metal protrusion 11 are connected by a method such as thermocompression bonding. Regarding the method of forming the metal protrusion 11 provided on the external connection electrode 10 of the semiconductor element 9,
There are a method of forming a ball using a thin gold wire and performing thermocompression bonding, and a method of forming the ball by a plating method.
【００１９】リード部５と半導体素子９の金属突起１１
が電気的に接続された後、半導体素子用フィルム１に設
けられた測定用回路パターン７により、リード部５と半
導体素子９との電気的特性のチェックや信頼性を確認す
るバーインテストなどが行われる。The lead portion 5 and the metal protrusion 11 of the semiconductor element 9
Are electrically connected, a measurement circuit pattern 7 provided on the semiconductor element film 1 performs an electrical characteristic check between the lead portion 5 and the semiconductor element 9 and a burn-in test for confirming reliability. Will be
【００２０】図１および図４に示されるように、親基板
１２への搭載は半導体素子用フィルム１が半導体素子９
とほぼ同じ寸法でリード部５の端部より切離されて実装
される。親基板１２には球状半田８に対応した接続用回
路パターン１３が形成されており、半導体素子９は裏面
が上向きされて搭載され、リフロー装置などによって加
熱されて球状半田８を再溶融させることにより接続され
る。As shown in FIGS. 1 and 4, the semiconductor element film 1 is
, Which are almost the same size as those of FIG. A connection circuit pattern 13 corresponding to the spherical solder 8 is formed on the parent substrate 12, and the semiconductor element 9 is mounted with the back surface facing upward, and is heated by a reflow device or the like to re-melt the spherical solder 8. Connected.
【００２１】発熱量の大きい半導体素子を使用する場合
には、図４に示すような熱伝導性の高い材料でできたラ
ジエータ１４を半導体素子９の裏面に接触させて配置す
ることで放熱を高めることが可能である。When a semiconductor element having a large heat value is used, a radiator 14 made of a material having high thermal conductivity as shown in FIG. It is possible.
【００２２】再び図５を参照して、本発明の半導体素子
実装用フィルムの内部の構成についてもう少し詳細に説
明する。第１の絶縁性フィルム２の上面には、半田８を
含む端子が形成されている。この端子は図４に示される
ように、最終的には親基板１２に実装される際に接続に
用いられるものである。また、上面側には端子に電気的
に接続され、外部との接続を図るためのリード部５を有
する回路パターン４が 形成されている。ここで、リード
部５は図５に示されるように代１の絶縁性フィルム２の
外周から突出している。これにより半導体素子９と金属
突起１１を介して電気的な接続が可能となる。一方、第
１の絶縁性フィルム２の半導体素子９側（図中下側）に
は、回路パターン１５と第２の絶縁性フィルム１６が形
成されている。第１の絶縁性フィルム２には接続用孔１
７が形成されている。回路パターン４と回路パターン１
５との間には第１の絶縁性フィルム２が介在している
が、上記接続用孔１７に埋められた金属を介して電気的
に接続されている。ここで、回路パターン１５を接地電
位とすることで半導体素子９の回路部分と接地電位と接
続されない回路パターン４との電気的結合を疎にするこ
とが可能である。また、球状半田８までの回路パターン
４のパターン幅と回路パターン（接地電位）に挟まれた
絶縁性フィルム２の比誘電率を適宜選択することによ
り、高周波に対応したマイクロストリップラインの回路
パターンを構成することも可能である。さらに、上記構
成で、絶縁性フィルムの回路パターン１５の電極に相当
する位置に穴を設けることにより半導体素子を実装する
フィルムを構成することも可能である。Referring again to FIG. 5, the semiconductor device of the present invention
A more detailed explanation of the internal structure of the mounting film
I will tell. Solder 8 is provided on the upper surface of first insulating film 2.
Terminals are formed. This terminal is shown in FIG.
Finally, when mounted on the motherboard 12,
What is used. Also, on the top side, the terminals are electrically
And a lead 5 for connection to the outside.
The circuit pattern 4 is formed. Where the lead
As shown in FIG. 5, the portion 5 of the insulating film 2
It protrudes from the outer circumference. Thereby, the semiconductor element 9 and the metal
Electrical connection is possible via the protrusions 11. On the other hand,
A circuit pattern 15 and a second insulating film 16 are formed on the semiconductor element 9 side (the lower side in the figure) of the first insulating film 2 . The first insulating film 2 has a connection hole 1
7 are formed. Circuit pattern 4 and circuit pattern 1
5 and the first insulating film 2 is interposed.
Is electrically connected via the metal buried in the connection hole 17.
It is connected to the. Here, by setting the circuit pattern 15 to the ground potential, the electrical coupling between the circuit portion of the semiconductor element 9 and the circuit pattern 4 not connected to the ground potential can be reduced. Also, by appropriately selecting the pattern width of the circuit pattern 4 up to the spherical solder 8 and the relative dielectric constant of the insulating film 2 sandwiched between the circuit patterns (ground potential), the circuit pattern of the microstrip line corresponding to a high frequency can be obtained. It is also possible to configure. Further , with the above configuration, it is also possible to configure a film on which the semiconductor element is mounted by providing holes at positions corresponding to the electrodes of the circuit pattern 15 of the insulating film.
【００２３】[0023]
【発明の効果】以上説明したように、本発明の半導体装
置では従来のＢＧＡ構造に比較して、ワイヤーボンディ
ングを行う領域と裏面へのスルーホール接続の領域が不
要であるため小型化が可能であり、半導体素子を半導体
素子用フィルムに取り付けた後の試験が半導体素子用フ
ィルムに設けた測定用回路パターンにて実施できるた
め、球状半田の変形を起こすこともなく、特殊な冶工具
も不要である。また発熱量の大きい半導体素子に対して
も自由度の高い放熱構造が採用できる効果がある。As described above, the semiconductor device of the present invention does not require a region for performing wire bonding and a region for connecting a through hole to the back surface, as compared with the conventional BGA structure, so that the semiconductor device can be miniaturized. Yes, since the test after attaching the semiconductor element to the semiconductor element film can be performed with the measurement circuit pattern provided on the semiconductor element film, it does not cause deformation of the spherical solder and does not require special jigs and tools is there. Further, there is an effect that a heat radiation structure having a high degree of freedom can be adopted for a semiconductor element having a large heat generation.
【図１】本発明の半導体素子実装構造の理解を容易にす
るための参考図であり（本発明は第１及び第２の絶縁性
フィルムの積層よりなるところ単層フィルムとして記
載。図２乃至４において同じ。）、半導体素子が実装さ
れた半導体素子実装用フィルムが親基板に搭載される際
に所定の寸法に切断された状態を示す正面図と縦断 面図
である。 FIG. 1 facilitates understanding of a semiconductor device mounting structure of the present invention.
FIG. 4 is a reference diagram for the present invention (the present invention relates to first and second insulating properties).
A single-layer film consisting of laminated films
On. The same applies to FIGS. ), Semiconductor element mounted
Semiconductor device mounting film is mounted on the mother board
Front view and longitudinal sectional view showing a state cut to predetermined dimensions
It is.
【図２】本発明の半導体素子実装用フィルムの理解を容
易にするための参考図であり、単層の絶縁性フィルムか
らなる実装用フィルムの縦断面を図であって半導体素子
が実装され切断前の状態を示す縦断面図である。 FIG. 2 illustrates the understanding of the film for mounting a semiconductor element of the present invention.
This is a reference drawing for ease of use.
FIG. 2 is a longitudinal sectional view of a mounting film made of a semiconductor device.
FIG. 3 is a longitudinal sectional view showing a state before mounting and before cutting.
【図３】本発明の半導体素子実装用フィルムの理解を容
易にするための参考図であり、所定の寸法に切断される
前の正面図である。 FIG. 3 is a reference view for facilitating understanding of the semiconductor element mounting film of the present invention, and is a front view before being cut into a predetermined size .
【図４】本発明の半導体素子実装構造の理解を容易にす
るための縦断面図であり、半導体素子実装用フィルムが
親基板に実装された状態を示す縦断面図である。 FIG. 4 facilitates understanding of a semiconductor element mounting structure of the present invention.
FIG. 5 is a longitudinal sectional view for illustrating a state in which a film for mounting a semiconductor element is mounted on a parent substrate .
【図５】本発明の半導体素子実装構造の一実施例の構造
を示す縦断面図である。 [5] The structure of an embodiment of a semiconductor device mounting structure of the present invention
It is a longitudinal sectional view showing a.
【図６】従来のＢＧＡ構造の正面図と縦断面図である。 FIG. 6 is a front view and a longitudinal sectional view of a conventional BGA structure .
【図７】従来のＱＦＰ構造の正面図と縦断面図である。 FIG. 7 is a front view and a longitudinal sectional view of a conventional QFP structure .
１ ・・・ 半導体素子実装用フィルム ２ ・・・ 第１の絶縁性フィルム ３ ・・・ スプロケットホール ４ ・・・ 回路パターン ５ ・・・ リード部 ６ ・・・ 孔 ７ ・・・ 測定用回路パターン ８ ・・・ 球状半田 ９ ・・・ 半導体素子 １０ ・・・ 外部接続用電極 １１ ・・・ 金属突起 １２ ・・・ 親基板 １３ ・・・ 親基板に形成された接続用回路パターン １４ ・・・ ラジエータ １５ ・・・ 回路パターン １６ ・・・ 第２の絶縁性フィルム １７ ・・・ 接続用孔 １８ ・・・ プラスティック基板 １９ ・・・ スルーホール ２０ ・・・ 回路パターン ２１ ・・・ 回路パターン ２２ ・・・ 金線 ２３ ・・・ モールド ２４ ・・・ 入出力端子リード ２５ ・・・ モールドDESCRIPTION OF SYMBOLS 1 ... Semiconductor element mounting film 2 ... 1st insulating film 3 ... Sprocket hole 4 ... Circuit pattern 5 ... Lead part 6 ... Hole 7 ... Measurement circuit pattern Reference Signs List 8 spherical solder 9 semiconductor element 10 external connection electrode 11 metal projection 12 parent substrate 13 connection circuit pattern formed on parent substrate 14 Radiator 15 Circuit pattern 16 Second insulating film 17 Connection hole 18 Plastic substrate 19 Through hole 20 Circuit pattern 21 Circuit pattern 22 .. Gold wire 23 ... Mold 24 ... I / O terminal lead 25 ... Mold
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 311 S H01L 21/60 311 W ──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 311 S H01L 21/60 311 W
Claims (4)
ィルムが積層された半導体素子実装用フィルムであっ
て、 前記第１の絶縁性フィルムは、 第１の面の中央の領域に配列された半田を含む複数の端
子と、 前記端子に接続され、前記第１の絶縁性フィルムの外周
から突出して形成されたリード部を含む第１の回路パタ
ーンと を有し、 前記第１の絶縁性フィルムの第２の面、又は該第２の面
に固着される前記第２の絶縁性フィルムの第１の面に、
第２の回路パターンが形成されており、 前記第１の回路パターンと前記第２の回路パターンとが
電気的に 接続されていることを特徴とする半導体素子実
装用フィルム。(1)The second insulating film is provided on the first insulating film.
Film for semiconductor device mounting
hand, The first insulating film includes: A plurality of ends including solder arranged in a central region of the first surface;
With the child, Connected to the terminal, the outer periphery of the first insulating film
Circuit pattern including a lead portion projecting from the first circuit pattern
And Has, A second surface of the first insulating film, or the second surface
On the first surface of the second insulating film fixed to
A second circuit pattern is formed, The first circuit pattern and the second circuit pattern
Electrically A semiconductor device characterized by being connected
Wearing film.
路パターンとは、前記第１の絶縁性フィルムに形成され
た孔に挿入された導電物質により電気的に接続されてい
ることを特徴とする請求項１記載の半導体素子実装用フ
ィルム。2. The method according to claim 1, wherein the first circuit pattern and the second circuit
The road pattern is formed on the first insulating film.
Electrically connected by a conductive material inserted into the hole.
Semiconductor element mounting film of claim 1, wherein the that.
実装用フィルムに半導体素子を実装する半導体素子実装
構造であって、 前記半導体素子は、前記第２の絶縁性フィルムの第２の
面の側に配置され、 前記リード部は、前記半導体素子の表面に形成された外
部接続用電極に相対する位置に形成されており、 前記リード部と前記外部接続用電極が接触されて前記半
導体素子と前記半導体素子実装用フィルムが接続されて
いる ことを特徴とする半導体素子実装構造。(3)The semiconductor device according to claim 1.
Semiconductor element mounting for mounting semiconductor elements on mounting film
Structure, The semiconductor element may be a second insulating film.
Placed on the side of the surface, The lead portion is formed on an outer surface formed on a surface of the semiconductor element.
It is formed at a position opposite to the part connection electrode, The lead portion and the external connection electrode are brought into contact with each other,
The conductor element and the semiconductor element mounting film are connected
Is A semiconductor element mounting structure characterized by the above-mentioned.
板電極が接続されて前記半導体実装用フィルムが前記親
基板に固定され、 前記半導体素子には、前記外部接続用電極が形成された
面とは反対の面に放熱部材が固着されていることを特徴
とする請求項３記載の半導体素子実装構造。(4)The terminal and the substrate formed on the surface of the motherboard
A plate electrode is connected and the semiconductor mounting film is
Fixed to the board, In the semiconductor element,The external connection electrode is formed
Heat dissipating member on the opposite side to the surfaceIt is characterized by being fixed
4. The semiconductor element mounting structure according to claim 3, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086646A JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086646A JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07297236A JPH07297236A (en) | 1995-11-10 |
| JP3033662B2 true JP3033662B2 (en) | 2000-04-17 |
Family
ID=13892801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6086646A Expired - Lifetime JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033662B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2817704B2 (en) * | 1996-04-25 | 1998-10-30 | 日本電気株式会社 | Tape carrier package and connection method |
| TW480636B (en) | 1996-12-04 | 2002-03-21 | Seiko Epson Corp | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| TW571373B (en) | 1996-12-04 | 2004-01-11 | Seiko Epson Corp | Semiconductor device, circuit substrate, and electronic machine |
| EP1443555A3 (en) | 1997-01-23 | 2005-02-23 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3295457B2 (en) * | 1992-08-27 | 2002-06-24 | 三菱電機株式会社 | Semiconductor device |
-
1994
- 1994-04-25 JP JP6086646A patent/JP3033662B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07297236A (en) | 1995-11-10 |
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