JPH1174421A - Composite semiconductor device - Google Patents
Composite semiconductor deviceInfo
- Publication number
- JPH1174421A JPH1174421A JP9249587A JP24958797A JPH1174421A JP H1174421 A JPH1174421 A JP H1174421A JP 9249587 A JP9249587 A JP 9249587A JP 24958797 A JP24958797 A JP 24958797A JP H1174421 A JPH1174421 A JP H1174421A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductive circuit
- circuit pattern
- connection terminal
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＢＧＡ（ボールグ
リッドアレイ）型の接続端子を備え、２層構造の半導体
素子を有する複合型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device having a BGA (ball grid array) type connection terminal and a semiconductor element having a two-layer structure.
【０００２】[0002]
【従来の技術】従来は多数の半導体装置をプリント基板
上に平面的に並べた電子回路基盤が殆どであったが、近
年は複数の素子からなるコンピュータを小型の装置の中
に組み込む必要があって、プリント基板自体の小型化が
要望されるようになった。そこで、特開平９−３６３０
０号公報に記載のように、リードフレームのアイランド
の両面に、半導体素子を搭載した半導体装置が提案さ
れ、また、特開平８−２７４２５０号公報には、基板の
上部と下部に半導体素子を搭載し、上部の半導体素子の
配線はアウターリードによって行い、下部の半導体素子
の接続は半田ボールによって行うようにした半導体装置
が提案されている。2. Description of the Related Art Conventionally, most electronic circuit boards have a large number of semiconductor devices arranged in a plane on a printed circuit board. In recent years, however, it has been necessary to incorporate a computer comprising a plurality of elements into a small device. Therefore, there has been a demand for miniaturization of the printed circuit board itself. Therefore, Japanese Patent Application Laid-Open No. 9-3630 describes
As described in Japanese Patent Application Laid-Open No. 0-250, a semiconductor device in which semiconductor elements are mounted on both sides of an island of a lead frame is proposed. A semiconductor device has been proposed in which wiring of the upper semiconductor element is performed by outer leads and connection of the lower semiconductor element is performed by solder balls.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、特開平
９−３６３００号公報記載の半導体装置においては、全
体をモールドし、外部との配線をリードフレームによっ
て行っているので、リードフレームの分だけが外方に突
出し、装置全体の小型化を図ることができないという問
題があった。また、特開平８−２７４２５０号公報記載
の半導体装置においては、上部の半導体素子の配線はア
ウターリードによって行っているのて、装置自体の小型
化には支障があるという問題がある他、上下の半導体素
子を連結するための配線は、外部のプリント基板を介し
てしか行えず、このため配線基板の導体回路が複雑化
し、更には回路自体のインピーダンスが大きくなって、
動作周波数を上げると支障があるという問題があった。
本発明はかかる事情に鑑みてなされたもので、半導体装
置の小型化が可能であると共に、その接続端子にはＢＧ
Ａ型の接続端子を備える複合型半導体装置を提供するこ
とを目的とする。However, in the semiconductor device described in Japanese Patent Application Laid-Open No. 9-36300, since the whole is molded and the wiring to the outside is performed by the lead frame, only the lead frame corresponds to the outside. And the size of the entire device cannot be reduced. Further, in the semiconductor device described in Japanese Patent Application Laid-Open No. 8-274250, wiring of the upper semiconductor element is performed by outer leads, so that there is a problem that the miniaturization of the device itself is hindered. Wiring for connecting semiconductor elements can only be performed via an external printed circuit board, which complicates the conductor circuit of the wiring board and further increases the impedance of the circuit itself,
There has been a problem that raising the operating frequency has a problem.
The present invention has been made in view of such circumstances, and it is possible to reduce the size of a semiconductor device and to connect BG to a connection terminal thereof.
It is an object to provide a composite semiconductor device including an A-type connection terminal.
【０００４】[0004]
【課題を解決するための手段】前記目的に沿う請求項１
記載の複合型半導体装置は、絶縁シートの表裏に第１及
び第２の導体回路パターンを備え、しかも、前記絶縁シ
ートに設けられた抜き孔を介して前記第１及び第２の導
体回路パターンの導通部が形成された回路基板と、前記
回路基板の表面側に固着され、前記第１の導体回路パタ
ーンの各リードの第１の内側接続端子とは第１のボンデ
ィングワイヤを介してそれぞれ電気的に連結された第１
の半導体素子と、前記第１の半導体素子、前記第１の導
体回路パターン、及びこれらを連結する前記第１のボン
ディングワイヤを封止する第１の封止樹脂と、前記回路
基板の裏面側に固着され、前記第２の導体回路パターン
の各リードの第２の内側接続端子とは第２のボンディン
グワイヤを介してそれぞれ電気的に連結された第２の半
導体素子と、中央部には前記第２の導体回路パターンの
各リードの第２の内側接続端子が露出する開口部を備
え、一面側が前記第２の導体回路パターンに接合され、
該第２の導体回路パターンの各リードの外側接続端子に
連結される導体部を備え、他面側には前記各導体部に導
通する半田ボールを備える絶縁材料からなる支持基板
と、前記第２の半導体素子、前記第２の導体回路パター
ンの第２の内側接続端子、及びこれらを連結する前記第
２のボンディングワイヤを、前記半田ボールが突出した
状態で封止する第２の封止樹脂とを有している。According to the present invention, there is provided a semiconductor device comprising:
The composite semiconductor device according to the aspect of the invention includes first and second conductive circuit patterns on the front and back of the insulating sheet, and furthermore, the first and second conductive circuit patterns are formed through holes formed in the insulating sheet. The circuit board on which the conductive portion is formed, and the first inner connection terminal of each lead of the first conductive circuit pattern, which is fixed to the front side of the circuit board, are electrically connected via a first bonding wire. The first connected to
A first sealing resin for sealing the first semiconductor element, the first semiconductor element, the first conductive circuit pattern, and the first bonding wire connecting the first semiconductor element, the first conductive circuit pattern, and the first bonding wire; A second semiconductor element that is fixed and electrically connected to a second inner connection terminal of each lead of the second conductive circuit pattern via a second bonding wire; An opening through which a second inner connection terminal of each lead of the second conductor circuit pattern is exposed, and one surface side is joined to the second conductor circuit pattern;
A support substrate made of an insulating material including a conductor portion connected to an outer connection terminal of each lead of the second conductor circuit pattern, and a solder ball connected to the conductor portion on the other surface; A second sealing resin for sealing the semiconductor element, the second inner connection terminal of the second conductive circuit pattern, and the second bonding wire connecting them, with the solder balls protruding. have.
【０００５】請求項２記載の複合型半導体装置は、請求
項１記載の複合型半導体装置において、前記第１の封止
樹脂はトランスファーモールドによって形成されたエポ
キシ樹脂からなり、前記第２の封止樹脂はポッテングモ
ールドによって形成された液状エラストマ樹脂又はエポ
キシ樹脂からなる。請求項３記載の複合型半導体装置
は、請求項１又は２記載の複合型半導体装置において、
前記第１及び第２の導体回路パターンを連結する導通部
は、超音波接合によって形成されている。請求項４記載
の複合型半導体装置は、請求項１〜３のいずれか１項に
記載の複合型半導体装置において、前記第１の半導体素
子はメモリ素子からなって、前記第２の半導体素子はＣ
ＰＵ素子からなる。請求項５記載の複合型半導体装置
は、請求項１〜４のいずれか１項に記載の複合型半導体
装置において、前記第１、第２の導体回路パターンは、
金属薄板条材からプレス加工又はエッチング加工により
形成された前記リードを有している。According to a second aspect of the present invention, in the composite type semiconductor device according to the first aspect, the first sealing resin is made of an epoxy resin formed by transfer molding, and the second sealing resin is made of an epoxy resin. The resin is made of a liquid elastomer resin or an epoxy resin formed by a potting mold. The composite semiconductor device according to claim 3 is the composite semiconductor device according to claim 1 or 2,
The conductive portion connecting the first and second conductive circuit patterns is formed by ultrasonic bonding. The composite semiconductor device according to claim 4 is the composite semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor element is a memory element, and the second semiconductor element is a memory element. C
It consists of PU elements. The composite semiconductor device according to claim 5 is the composite semiconductor device according to claim 1, wherein the first and second conductor circuit patterns are:
It has the lead formed by pressing or etching from a sheet metal strip.
【０００６】[0006]
【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図１は本発明の一実施の形
態に係る複合型半導体装置の断面図、図２は同複合型半
導体装置の底面図、図３は同複合型半導体装置の第１の
導体回路パターンの平面図、図４は同複合型半導体装置
の回路基板の断面図、図５は同複合型半導体装置の第２
の導体回路パターンの平面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention. FIG. 1 is a cross-sectional view of a composite semiconductor device according to an embodiment of the present invention, FIG. 2 is a bottom view of the composite semiconductor device, and FIG. 3 is a first conductor circuit pattern of the composite semiconductor device. FIG. 4 is a sectional view of a circuit board of the composite semiconductor device, and FIG. 5 is a second view of the composite semiconductor device.
3 is a plan view of the conductor circuit pattern of FIG.
【０００７】図１〜図５に示すように、本発明の一実施
の形態に係る複合型半導体装置１０は、表裏に第１及び
第２の導体回路パターン１１、１２がそれぞれ形成され
た回路基板１３と、その裏面側に接合されて中央に開口
部１４を備える支持基板１５を有している。As shown in FIGS. 1 to 5, a composite semiconductor device 10 according to one embodiment of the present invention has a circuit board having first and second conductive circuit patterns 11 and 12 formed on the front and back, respectively. 13 and a support substrate 15 joined to the back surface side and having an opening 14 in the center.
【０００８】前記回路基板１３は、図４に示すように、
中央に絶縁シートの一例であるポリイミド樹脂テープ１
６が使用され、その表側中央には第１の素子搭載部１７
が形成され、図３に示すようにその周囲に第１の導体回
路パターン１１が配置されている。第１の導体回路パタ
ーン１１は、外側に伸びる多数のリード１８を備えて、
内側端部にはそれぞれ第１の内側接続端子１９を有して
いる。一方、ポリイミド樹脂テープ１６の裏面側には、
図５に示すように、中央に第２の素子搭載部２０が、そ
の周囲には第２の導体回路パターン１２が配置されてい
る。第２の導体回路パターン１２は多数のリード２１を
有し、各リード２１の内側は第２の内側接続端子２２を
備えている。なお、第１及び／又は第２の導体回路パタ
ーン１１、１２の各リードを金属薄板条材からプレス加
工又はエッチング加工により形成してもよい。The circuit board 13 is, as shown in FIG.
Polyimide resin tape 1 as an example of an insulating sheet in the center
6 is used, and a first element mounting portion 17 is provided in the center of the front side.
Are formed, and a first conductive circuit pattern 11 is arranged around the first conductive circuit pattern 11 as shown in FIG. The first conductive circuit pattern 11 includes a plurality of leads 18 extending outward.
Each of the inner ends has a first inner connection terminal 19. On the other hand, on the back side of the polyimide resin tape 16,
As shown in FIG. 5, a second element mounting portion 20 is disposed at the center, and a second conductive circuit pattern 12 is disposed around the second element mounting portion 20. The second conductive circuit pattern 12 has a large number of leads 21, and the inside of each lead 21 has a second inside connection terminal 22. In addition, each lead of the first and / or second conductive circuit patterns 11 and 12 may be formed from a thin metal plate material by pressing or etching.
【０００９】前記ポリイミド樹脂テープ１６の周囲に
は、図３に示すように、４個の抜き孔２３が形成され、
この部分で第１及び第２の導体回路パターン１１、１２
の各リード１８、２１の外側部分が重なりあって、超音
波接合によって電気的に接合された導通部２２ａを形成
し、このような構造で回路基板１３は構成されている。
なお、この実施の形態では、絶縁シートとしてポリイミ
ド樹脂テープを使用したが、ポリイミド樹脂フィルムや
その他の熱に強いシート又はテープであれば使用可能で
ある。Around the polyimide resin tape 16, four holes 23 are formed as shown in FIG.
In this portion, the first and second conductive circuit patterns 11 and 12
The outer portions of the respective leads 18 and 21 overlap each other to form a conductive portion 22a electrically connected by ultrasonic bonding, and the circuit board 13 is configured with such a structure.
In this embodiment, a polyimide resin tape is used as an insulating sheet. However, any polyimide resin film or other heat-resistant sheet or tape can be used.
【００１０】前記回路基板１３の表側中央には、第１の
半導体素子の一例であるメモリ素子２４が導電性接着剤
の一例である銀ペースト等を用いて接合され、メモリ素
子２４の各パッド（接続端子）と前記各リード１８の第
１の内側接続端子１９とは第１のボンディングワイヤ２
５を介して連結されている。なお、ここで、メモリ素子
２４の接合にアース等をとる必要がない場合には絶縁性
接着剤を用いることも可能である。このようにして、メ
モリ素子２４から第１の導体回路パターン１１、第２の
導体回路パターン１２への電気回路が形成されている。At the center of the front side of the circuit board 13, a memory element 24, which is an example of a first semiconductor element, is bonded using a silver paste or the like, which is an example of a conductive adhesive. The first bonding wire 2 and the first inner connection terminal 19 of each lead 18
5 are connected. Here, when it is not necessary to take ground or the like for bonding the memory element 24, an insulating adhesive can be used. Thus, an electric circuit from the memory element 24 to the first conductive circuit pattern 11 and the second conductive circuit pattern 12 is formed.
【００１１】一方、回路基板１３の裏面側の第２の素子
搭載部２０には、第２の半導体素子の一例であるＣＰＵ
素子２６が導電性接着剤等を介して搭載され、このＣＰ
Ｕ素子２６の各パッド（接続端子）と第２の導体回路パ
ターン１２の各リード２１の第２の内側接続端子２２と
は第２のボンディングワイヤ２７によって接合されてい
る。On the other hand, the second element mounting portion 20 on the back side of the circuit board 13 has a CPU, which is an example of a second semiconductor element, mounted thereon.
The element 26 is mounted via a conductive adhesive or the like.
Each pad (connection terminal) of the U element 26 and the second inner connection terminal 22 of each lead 21 of the second conductive circuit pattern 12 are joined by a second bonding wire 27.
【００１２】前記回路基板１３の裏面側には、中央に開
口部１４を備える絶縁材料からなる支持基板１５が絶縁
性接着剤２８を介して接合されている。開口部１４の大
きさは、第２の導体回路パターン１２の各第２の内側接
続端子２２が露出する大きさとなって、開口部１４の中
央にＣＰＵ素子２６が配置されている。また、図２に示
すように、支持基板１５には所定個数のスルーホールが
設けられ、内部には半田や銀ペースト等の導体部２９が
形成されて、その一方側の基端部が第２の導体回路パタ
ーン１２の各外側接続端子３０に電気的に接合してい
る。それぞれの導体部２９の他方側には半田ボール３１
が設けられ、これによって、この複合型半導体装置１０
の連結用の接続端子を形成している。A support substrate 15 made of an insulating material and having an opening 14 in the center is joined to the back side of the circuit board 13 via an insulating adhesive 28. The size of the opening 14 is such that each second inner connection terminal 22 of the second conductive circuit pattern 12 is exposed, and the CPU element 26 is arranged at the center of the opening 14. As shown in FIG. 2, a predetermined number of through-holes are provided in the support substrate 15, and a conductor portion 29 such as solder or silver paste is formed therein. Are electrically connected to the respective outer connection terminals 30 of the conductor circuit pattern 12. A solder ball 31 is provided on the other side of each conductor portion 29.
Is provided, whereby the composite semiconductor device 10
Are formed.
【００１３】一方、前記メモリ素子２４、第１のボンデ
ィングワイヤ２５、第１の導体回路パターン１１はトラ
ンスファーモールドによって形成された第１の封止樹脂
の一例であるエポキシ樹脂３２によって樹脂封止されて
いる。また、裏面側のＣＰＵ素子２６、及びこれに連結
される第２のボンディングワイヤ２７及び第２の内側接
続端子２２は、第２の封止樹脂の一例であるポッテング
モールドによって形成されたポリイミド樹脂３３（又は
その他の液状エラストマ樹脂やエポキシ樹脂であっても
よい）によって、半田ボール３１が突出した状態で樹脂
封止されている。そして、裏面側の各半田ボール３１の
隙間はソルダーレジスト膜３４に 覆われて、接合時の
隣り合う半田ボール３１の短絡を防止している。On the other hand, the memory element 24, the first bonding wires 25, and the first conductive circuit pattern 11 are resin-sealed by an epoxy resin 32 which is an example of a first sealing resin formed by transfer molding. I have. The CPU element 26 on the back side, and the second bonding wire 27 and the second inner connection terminal 22 connected to the CPU element 26 are made of polyimide resin formed by a potting mold which is an example of a second sealing resin. The solder ball 31 is resin-sealed with 33 (or another liquid elastomer resin or epoxy resin) in a protruding state. The gap between the solder balls 31 on the back side is covered with the solder resist film 34 to prevent short circuit between the adjacent solder balls 31 at the time of joining.
【００１４】以上の構成となっているので、上部のメモ
リ素子２４と下部のＣＰＵ素子２６の連結は、第１のボ
ンディングワイヤ２５、リード１８、導通部２２ａ、リ
ード２１、第２の内側接続端子２２にその一端が連結さ
れる第２のボンディングワイヤ２７を介して行われる
（図１、図３、図５参照）。また、メモリ素子２４から
外部接続端子となる半田ボール３１への導通は、第１の
ボンディングワイヤ２５、リード１８、導通部２２ａ、
リード２１、外側接続端子３０、導体部２９を介して行
われる。そして、ＣＰＵ素子２６から半田ボール３１へ
の導通は、第２のボンディングワイヤ２７、リード２
１、外側接続端子３０、及び導体部２９を介して行われ
ることになる。これによって、この複合型半導体装置１
０をコンピュータの心臓部として構成することができ
る。なお、図３において３５は外枠を、図５において３
６は外枠を示す。With the above structure, the upper memory element 24 and the lower CPU element 26 are connected by the first bonding wire 25, the lead 18, the conductive portion 22a, the lead 21, and the second inner connection terminal. This is performed via a second bonding wire 27 having one end connected to the second bonding wire 22 (see FIGS. 1, 3 and 5). In addition, conduction from the memory element 24 to the solder ball 31 serving as an external connection terminal is performed by the first bonding wire 25, the lead 18, the conduction portion 22a,
This is performed via the lead 21, the outer connection terminal 30, and the conductor 29. The conduction from the CPU element 26 to the solder ball 31 is determined by the second bonding wire 27 and the lead 2.
1, via the outer connection terminal 30 and the conductor portion 29. Thereby, the composite semiconductor device 1
0 can be configured as the heart of the computer. In FIG. 3, reference numeral 35 denotes an outer frame, and in FIG.
Reference numeral 6 denotes an outer frame.
【００１５】前記実施の形態においては、第１の半導体
素子にメモリ素子２４を、第２の半導体素子にＣＰＵ素
子２６を適用した場合について説明したが、双方ともメ
モリ素子あるいは別の素子に適用することもできる。ま
た、前記実施の形態においては、第１の導体回路パター
ン１１と第２の導体回路パターン１２と各リードの接合
にあっては、超音波接合によって接合したが、スルーホ
ール、半田、導電性ペースト等によって接合する場合も
本発明は適用される。In the above embodiment, the case where the memory element 24 is applied to the first semiconductor element and the CPU element 26 is applied to the second semiconductor element has been described, but both are applied to the memory element or another element. You can also. In the above embodiment, the first conductive circuit pattern 11, the second conductive circuit pattern 12, and the leads are bonded by ultrasonic bonding. However, through-holes, solder, conductive paste The present invention is also applicable to the case of joining by means such as.
【００１６】[0016]
【発明の効果】請求項１〜５記載の複合型半導体装置に
おいては、回路基板の表裏に第１、第２の半導体素子を
搭載すると共に、これらを第１及び第２の導体回路パタ
ーンによって連結し、更に回路基板の裏側に設けられた
支持基板に外部接続端子となる半田ボールに連結してい
るので、第１、第２の半導体素子の接続が内部で行われ
たＢＧＡタイプの複合型半導体装置を提供できる。これ
によって、更に小型の装置の中に複合型半導体装置を組
み込むことが可能となった。特に、請求項２記載の複合
型半導体装置においては、第１の封止樹脂はトランスフ
ァーモールドによって形成され、第２の封止樹脂はポッ
テングモールドからなるので、その製造が容易となっ
て、大量生産が可能となる。また、請求項３記載の複合
型半導体装置においては、第１及び第２の導体回路パタ
ーンを連結する導通部は、超音波接合によって形成され
ているので、効率的に製造を行うことができる。請求項
４記載の複合型半導体装置においては、第１の半導体素
子はメモリ素子からなって、第２の半導体素子はＣＰＵ
素子からなっているので、この複合型半導体装置で一つ
の超小型のコンピュータを形成できる。請求項５記載の
複合型半導体装置においては、導体回路パターンのみを
独自に製造できるので、任意の形のものが容易に製造で
き、これによって、作業性が向上し、製造原価を引き下
げることができる。In the composite semiconductor device according to the first to fifth aspects, the first and second semiconductor elements are mounted on the front and back of the circuit board, and these are connected by the first and second conductive circuit patterns. Further, since the first and second semiconductor elements are connected internally to the supporting substrate provided on the back side of the circuit board and connected to solder balls serving as external connection terminals, a BGA type composite semiconductor Equipment can be provided. This makes it possible to incorporate the composite semiconductor device into a smaller device. In particular, in the composite semiconductor device according to the present invention, the first sealing resin is formed by transfer molding, and the second sealing resin is formed by potting mold. Production becomes possible. Further, in the composite semiconductor device according to the third aspect, since the conductive portion connecting the first and second conductive circuit patterns is formed by ultrasonic bonding, it can be manufactured efficiently. In the composite semiconductor device according to claim 4, the first semiconductor element is a memory element, and the second semiconductor element is a CPU.
Since the semiconductor device is composed of elements, one ultra-compact computer can be formed with this composite semiconductor device. In the composite semiconductor device according to the fifth aspect, since only the conductor circuit pattern can be manufactured independently, any shape can be easily manufactured, thereby improving workability and reducing manufacturing costs. .
【図１】本発明の一実施の形態に係る複合型半導体装置
の断面図である。FIG. 1 is a sectional view of a composite semiconductor device according to one embodiment of the present invention.
【図２】同複合型半導体装置の底面図である。FIG. 2 is a bottom view of the composite semiconductor device.
【図３】同複合型半導体装置の第１の導体回路パターン
の平面図である。FIG. 3 is a plan view of a first conductive circuit pattern of the composite semiconductor device.
【図４】同複合型半導体装置の回路基板の断面図であ
る。FIG. 4 is a sectional view of a circuit board of the composite semiconductor device.
【図５】同複合型半導体装置の第２の導体回路パターン
の平面図である。FIG. 5 is a plan view of a second conductor circuit pattern of the composite semiconductor device.
１０ 複合型半導体装置 １１ 第１の導
体回路パターン １２ 第２の導体回路パターン １３ 回路基板 １４ 開口部 １５ 支持基板 １６ ポリイミド樹脂テープ １７ 第１の素
子搭載部 １８ リード １９ 第１の内
側接続端子 ２０ 第２の素子搭載部 ２１ リード ２２ 第２の内側接続端子 ２２ａ 導通部 ２３ 抜き孔 ２４ メモリ素
子 ２５ 第１のボンディングワイヤ ２６ ＣＰＵ素
子 ２７ 第２のボンディングワイヤ ２８ 絶縁性接
着剤 ２９ 導体部 ３０ 外側接続
端子 ３１ 半田ボール ３２ エポキシ
樹脂 ３３ ポリイミド樹脂 ３４ ソルダー
レジスト膜 ３５ 外枠 ３６ 外枠REFERENCE SIGNS LIST 10 composite semiconductor device 11 first conductive circuit pattern 12 second conductive circuit pattern 13 circuit board 14 opening 15 support substrate 16 polyimide resin tape 17 first element mounting portion 18 lead 19 first inner connection terminal 20 first 2 element mounting part 21 lead 22 second inner connection terminal 22a conduction part 23 hole 24 memory element 25 first bonding wire 26 CPU element 27 second bonding wire 28 insulating adhesive 29 conductor part 30 outer connection terminal 31 solder ball 32 epoxy resin 33 polyimide resin 34 solder resist film 35 outer frame 36 outer frame
フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 1/11 Ｈ０５Ｋ 1/18 Ｈ 1/18 Ｈ０１Ｌ 23/12 Ｌ Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 1/11 H05K 1/18 H 1/18 H01L 23/12 L
Claims (5)
回路パターンを備え、しかも、前記絶縁シートに設けら
れた抜き孔を介して前記第１及び第２の導体回路パター
ンの導通部が形成された回路基板と、 前記回路基板の表面側に固着され、前記第１の導体回路
パターンの各リードの第１の内側接続端子とは第１のボ
ンディングワイヤを介してそれぞれ電気的に連結された
第１の半導体素子と、 前記第１の半導体素子、前記第１の導体回路パターン、
及びこれらを連結する前記第１のボンディングワイヤを
封止する第１の封止樹脂と、 前記回路基板の裏面側に固着され、前記第２の導体回路
パターンの各リードの第２の内側接続端子とは第２のボ
ンディングワイヤを介してそれぞれ電気的に連結された
第２の半導体素子と、 中央部には前記第２の導体回路パターンの各リードの第
２の内側接続端子が露出する開口部を備え、一面側が前
記第２の導体回路パターンに接合され、該第２の導体回
路パターンの各リードの外側接続端子に連結される導体
部を備え、他面側には前記各導体部に導通する半田ボー
ルを備える絶縁材料からなる支持基板と、 前記第２の半導体素子、前記第２の導体回路パターンの
第２の内側接続端子、及びこれらを連結する前記第２の
ボンディングワイヤを、前記半田ボールが突出した状態
で封止する第２の封止樹脂とを有することを特徴とする
複合型半導体装置。1. An insulating sheet having first and second conductive circuit patterns on both sides thereof, and a conductive portion of the first and second conductive circuit patterns is formed through a hole provided in the insulating sheet. The formed circuit board and a first inner connection terminal of each lead of the first conductive circuit pattern, which are fixed to a front surface side of the circuit board, are electrically connected to each other via a first bonding wire. A first semiconductor element, the first semiconductor element, the first conductive circuit pattern,
And a first sealing resin that seals the first bonding wire connecting the first and second bonding wires, and a second inner connection terminal of each lead of the second conductive circuit pattern, which is fixed to a back surface side of the circuit board. Is a second semiconductor element electrically connected to each other via a second bonding wire, and an opening in a central portion where a second inner connection terminal of each lead of the second conductive circuit pattern is exposed. A conductor portion connected to the outer connection terminal of each lead of the second conductor circuit pattern on one surface side, and being electrically connected to the conductor portions on the other surface side. A supporting substrate made of an insulating material having solder balls to be connected, the second semiconductor element, a second inner connection terminal of the second conductive circuit pattern, and the second bonding wire connecting these components, Complex type semiconductor device characterized by a second sealing resin for sealing in a state in which Lumpur is projected.
ールドによって形成されたエポキシ樹脂からなり、前記
第２の封止樹脂はポッテングモールドによって形成され
た液状エラストマ樹脂又はエポキシ樹脂からなる請求項
１記載の複合型半導体装置。2. The method according to claim 1, wherein the first sealing resin is made of an epoxy resin formed by transfer molding, and the second sealing resin is made of a liquid elastomer resin or an epoxy resin formed by potting molding. The composite semiconductor device according to the above.
連結する導通部は、超音波接合によって形成された請求
項１又は２記載の複合型半導体装置。3. The composite semiconductor device according to claim 1, wherein the conductive portion connecting the first and second conductive circuit patterns is formed by ultrasonic bonding.
なって、前記第２の半導体素子はＣＰＵ素子からなる請
求項１〜３のいずれか１項に記載の複合型半導体装置。4. The composite semiconductor device according to claim 1, wherein said first semiconductor element comprises a memory element, and said second semiconductor element comprises a CPU element.
金属薄板条材からプレス加工又はエッチング加工により
形成された前記リードを有する請求項１〜４のいずれか
１項に記載の複合型半導体装置。5. The first and second conductive circuit patterns,
The composite semiconductor device according to claim 1, further comprising the lead formed by pressing or etching a thin metal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9249587A JPH1174421A (en) | 1997-08-30 | 1997-08-30 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9249587A JPH1174421A (en) | 1997-08-30 | 1997-08-30 | Composite semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1174421A true JPH1174421A (en) | 1999-03-16 |
Family
ID=17195241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9249587A Pending JPH1174421A (en) | 1997-08-30 | 1997-08-30 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1174421A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127186A (en) * | 1999-10-25 | 2001-05-11 | Oki Electric Ind Co Ltd | Ball grid array package, method of manufacturing the same, and semiconductor device |
| JP2004158825A (en) * | 2003-07-17 | 2004-06-03 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| KR100447554B1 (en) * | 2000-05-16 | 2004-09-08 | 히다찌 에이아이시 가부시키가이샤 | Printed wiring board having cavity |
| JP2007529882A (en) * | 2004-02-26 | 2007-10-25 | 新科實業有限公司 | Method and apparatus for connecting metal structures on opposite sides of a circuit |
| WO2020100899A1 (en) * | 2018-11-14 | 2020-05-22 | 株式会社村田製作所 | Electronic component and electronic component module provided with same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088285A (en) * | 1994-06-23 | 1996-01-12 | Hitachi Ltd | Semiconductor device |
| JPH08330509A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Electronic circuit device and its manufacturing method |
| JPH0945821A (en) * | 1995-07-31 | 1997-02-14 | Rohm Co Ltd | Resin-packaged semiconductor device and manufacture thereof |
-
1997
- 1997-08-30 JP JP9249587A patent/JPH1174421A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088285A (en) * | 1994-06-23 | 1996-01-12 | Hitachi Ltd | Semiconductor device |
| JPH08330509A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Electronic circuit device and its manufacturing method |
| JPH0945821A (en) * | 1995-07-31 | 1997-02-14 | Rohm Co Ltd | Resin-packaged semiconductor device and manufacture thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127186A (en) * | 1999-10-25 | 2001-05-11 | Oki Electric Ind Co Ltd | Ball grid array package, method of manufacturing the same, and semiconductor device |
| KR100447554B1 (en) * | 2000-05-16 | 2004-09-08 | 히다찌 에이아이시 가부시키가이샤 | Printed wiring board having cavity |
| JP2004158825A (en) * | 2003-07-17 | 2004-06-03 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JP2007529882A (en) * | 2004-02-26 | 2007-10-25 | 新科實業有限公司 | Method and apparatus for connecting metal structures on opposite sides of a circuit |
| WO2020100899A1 (en) * | 2018-11-14 | 2020-05-22 | 株式会社村田製作所 | Electronic component and electronic component module provided with same |
| CN113016065A (en) * | 2018-11-14 | 2021-06-22 | 株式会社村田制作所 | Electronic component and electronic component module provided with same |
| US11948854B2 (en) | 2018-11-14 | 2024-04-02 | Murata Manufacturing Co., Ltd. | Electronic component and electronic component module including the same |
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