JPH07221427A - Package for surface mount and package mount device - Google Patents
Package for surface mount and package mount deviceInfo
- Publication number
- JPH07221427A JPH07221427A JP6029014A JP2901494A JPH07221427A JP H07221427 A JPH07221427 A JP H07221427A JP 6029014 A JP6029014 A JP 6029014A JP 2901494 A JP2901494 A JP 2901494A JP H07221427 A JPH07221427 A JP H07221427A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- bonding wire
- hole
- semiconductor element
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、表面実装用パッケージ
及びパッケージ実装装置に関し、更に詳しくは、薄型で
しかもリールツウリール方式にて製造可能な表面実装用
パッケージ及びこれを用いた薄型のパッケージ実装装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mounting package and a package mounting device, and more particularly to a thin surface mounting package which can be manufactured by a reel-to-reel method and a thin package mounting using the same. Regarding the device.
【０００２】[0002]
【従来の技術】従来の表面実装用パッケージとしては、
半田接合用のピンＰを備えるパッドグリッドアレイ（図
１２）及びこれを半田Ｈによりプリント配線基板に接合
して製作されたパッケージ実装装置（図１３）〔特公平
５−１９９８５号公報〕、基板の側方にはみ出た表面パ
ターンを有する半導体素子搭載用両面フィルムキャリア
（特公平５−１７７０４号公報）及びＩＣモジュール用
キヤリア要素（特公昭６３−５４２１９号公報）が知ら
れている。2. Description of the Related Art As a conventional surface mount package,
A pad grid array having pins P for soldering (FIG. 12) and a package mounting device (FIG. 13) manufactured by bonding this to a printed wiring board with solder H [Japanese Patent Publication No. 5-19935], A double-sided film carrier for mounting a semiconductor element having a surface pattern protruding laterally (Japanese Patent Publication No. 5-17704) and a carrier element for an IC module (Japanese Patent Publication No. 63-54219) are known.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記特公平５
−１９９８５号公報に係るパッドグリッドアレイは、半
田接合用のピンＰを備えるので、厚くなるし、このピン
を挿入するスルーホールの内面をメッキする必要もあ
り、更にリールトウリールにて製造することも困難とな
る。また、所謂ピングリッドアレイにおいても厚くなる
という欠点を同様に有する。上記特公平５−１７７０４
号公報に係る半導体素子搭載用両面フィルムキャリアに
おいては、基板の側方にはみ出た表面パターンが実装用
の接続端子となり、これを介して表面実装することとな
り、そのためボンディングワイヤーと接続される端子部
が実装用の接続端子とならないので、横長となり且つ簡
便な構造とならないし、リールトウリールにて製造する
ことも困難となる。所謂、フラットパッケージも同様な
欠点を有する。また、上記特公昭６３−５４２１９号公
報に係るＩＣモジュール用キヤリア要素においては、外
側端子部が半導体素子の下方に位置しているし、フィル
ム片の上に半導体素子が搭載されているので、厚くな
る。[Problems to be Solved by the Invention]
Since the pad grid array according to Japanese Patent Publication No. 199985 has a pin P for solder joining, it becomes thicker, and it is necessary to plate the inner surface of the through hole into which this pin is inserted, and further, it should be manufactured by a reel to reel. Will also be difficult. In addition, the so-called pin grid array also has a drawback that it becomes thick. Japanese Patent Publication No. 5-17704
In the double-sided film carrier for mounting a semiconductor element according to the publication, the surface pattern protruding to the side of the substrate serves as a connection terminal for mounting, and the surface mounting is performed through this, and therefore a terminal portion connected to the bonding wire. Since it does not serve as a connection terminal for mounting, it does not have a horizontally long and simple structure, and it is difficult to manufacture it with a reel toe reel. So-called flat packages also have similar drawbacks. Further, in the carrier element for an IC module according to Japanese Patent Publication No. 63-54219, the outer terminal portion is located below the semiconductor element, and the semiconductor element is mounted on the film piece, so that the thickness is increased. Become.
【０００４】本発明は、上記問題点を解決するためにな
されたものであり、薄型で、ボンディングワイヤー用貫
通孔の内周面のメッキを不要とする表面実装用パッケー
ジ及びこれを用いた薄型のパッケージ実装装置を提供す
ることを目的とする。更に、リールツウリール方式にて
製造可能な、半導体素子の搭載位置からより離れた位置
においてプリント配線基板と接合可能とした、又は放熱
効果に優れた表面実装用パッケージ及びこれを用いたパ
ッケージ実装装置を提供することを目的とする。The present invention has been made in order to solve the above-mentioned problems, and is a thin type package which does not require plating on the inner peripheral surface of the through hole for a bonding wire and a thin type package using the same. An object is to provide a package mounting device. Further, a surface mounting package which can be manufactured by a reel-to-reel method, can be bonded to a printed wiring board at a position farther from a mounting position of a semiconductor element, or has an excellent heat dissipation effect, and a package mounting device using the same The purpose is to provide.
【０００５】[0005]
【課題を解決するための手段】本第１発明の表面実装用
パッケージは、半導体素子搭載用貫通孔及び該半導体素
子搭載用貫通孔の周辺に配置された複数のボンディング
ワイヤー用貫通孔を有する樹脂製基材と、該半導体素子
搭載用貫通孔を塞ぐように該樹脂製基材の一方の面上に
形成される導電層と、該導電層上に接着剤層を介して接
着され且つ搭載される半導体素子と、上記ボンディング
ワイヤー用貫通孔を塞ぐように上記樹脂製基材の上記一
方の面上に形成される実装用端子部と、該実装用端子部
と上記半導体素子とを上記ボンディングワイヤー用貫通
孔を介して電気的に接合するボンディングワイヤーと、
該ボンディングワイヤー及び上記半導体素子を封止する
樹脂製封止部とからなることを特徴とする。A surface mount package according to the first aspect of the present invention is a resin having a through hole for mounting a semiconductor element and a plurality of through holes for bonding wires arranged around the through hole for mounting the semiconductor element. A base material made of a resin, a conductive layer formed on one surface of the base material made of a resin so as to close the through hole for mounting the semiconductor element, and bonded and mounted on the conductive layer via an adhesive layer. A semiconductor element, a mounting terminal portion formed on the one surface of the resin base material so as to close the through hole for the bonding wire, the mounting terminal portion and the semiconductor element, and the bonding wire. Bonding wire that is electrically joined through the through hole for
It is characterized by comprising the bonding wire and a resin-made sealing portion for sealing the semiconductor element.
【０００６】本第２発明の表面実装用パッケージは、複
数のボンディングワイヤー用貫通孔を有する樹脂製基材
と、上記ボンディングワイヤー用貫通孔を塞ぐように上
記樹脂製基材の上記一方の面上に形成される実装用端子
部と、該樹脂製基材の他方の面上であって上記ボンディ
ングワイヤー用貫通孔に取り囲まれるように搭載される
半導体素子と、上記実装用端子部と上記半導体素子とを
上記ボンディングワイヤー用貫通孔を介して電気的に接
合するボンディングワイヤーと、該ボンディングワイヤ
ー及び上記半導体素子を封止する樹脂製封止部とからな
ることを特徴とする。The surface mounting package according to the second aspect of the present invention comprises a resin base material having a plurality of through holes for bonding wires, and one surface of the resin base material so as to close the through holes for the bonding wires. A mounting terminal portion formed on the semiconductor substrate, a semiconductor element mounted on the other surface of the resin base material so as to be surrounded by the bonding wire through hole, the mounting terminal portion, and the semiconductor element. And a bonding wire that electrically bonds the bonding wire through the through hole for the bonding wire, and a resin-made sealing portion that seals the bonding wire and the semiconductor element.
【０００７】本第３発明の表面実装用パッケージは、上
記第１又は第２発明の表面実装用パッケージにおいて、
上記実装用端子部と上記半導体素子とを上記ボンディン
グワイヤー用貫通孔を介してボンディングワイヤーを用
いて電気的に接合する場合、上記樹脂製基材の上記他方
の面上に他の導電層が形成され、上記半導体素子と該他
の導電層とをボンディングワイヤーを用いて電気的に接
合するとともに、該他の導電層と上記実装用端子部とを
他のボンディングワイヤーを用いて電気的に接合するこ
とを特徴とする。The surface mounting package of the third invention is the same as the surface mounting package of the first or second invention,
When the mounting terminal portion and the semiconductor element are electrically joined using a bonding wire through the bonding wire through hole, another conductive layer is formed on the other surface of the resin base material. And electrically connecting the semiconductor element and the other conductive layer with a bonding wire, and electrically connecting the other conductive layer and the mounting terminal portion with another bonding wire. It is characterized by
【０００８】上記発明において、第４発明に示すよう
に、上記ボンディングワイヤー用貫通孔は、上記半導体
素子を直線状に取り囲むのではなく、千鳥状若しくは波
状に配置されることによって、より多数の配置を確保し
たものとすることができる。In the above invention, as shown in the fourth invention, the through holes for the bonding wires are arranged not in a straight line around the semiconductor element, but in a staggered or wavy pattern, so that a larger number of arrangements can be achieved. Can be secured.
【０００９】上記発明において、第５発明に示すよう
に、ボンディングワイヤーが挿通される上記ボンディン
グワイヤー用貫通孔以外に、電子部品搭載用貫通孔を備
え、該電子部品搭載用貫通孔には電子部品を配置し、且
つ該電子部品に接合されるとともに該電子部品搭載用貫
通孔を塞ぐように上記樹脂製基材の上記一方の面上に形
成される、少なくとも２分割された電子部品用端子部を
備えたものとすることができる。In the above invention, as shown in the fifth invention, in addition to the bonding wire through hole through which the bonding wire is inserted, an electronic component mounting through hole is provided, and the electronic component mounting through hole is provided in the electronic component. And a terminal part for at least two parts, which is formed on the one surface of the resin base material so as to be bonded to the electronic component and close the through hole for mounting the electronic component. Can be provided.
【００１０】上記において、第６発明に示すように、上
記樹脂製基材を長尺状とすることができる。また、上記
において、第７発明に示すように、表面実装用パッケー
ジが、該表面実装用パッケージの上記実装用端子部に対
向する位置に接合用端子部を備えるプリント配線基板の
表面に、該実装用端子部と該接合用端子部とを接合する
ことにより実装されてなるものとすることができる。In the above, as shown in the sixth aspect of the invention, the resin base material can be made into a long shape. Further, in the above, as shown in the seventh invention, the surface mounting package is mounted on the surface of a printed wiring board having a joining terminal portion at a position facing the mounting terminal portion of the surface mounting package. It can be mounted by joining the for-use terminal portion and the joining terminal portion.
【００１１】上記において、第８発明に示すように、表
面実装用パッケージを構成する上記樹脂製基材の上記一
方の面上であって且つ上記半導体素子が搭載される下方
側には、放熱体が形成され、該放熱体がプリント配線基
板に形成された放熱体収納用貫通孔内に収容されるもの
とすることができる。また、上記において、第９発明に
示すように、上記プリント配線基板には、放熱用貫通孔
を備えるものとすることができる。In the above, as shown in the eighth invention, a radiator is provided on the one surface of the resin base material constituting the surface mounting package and on the lower side on which the semiconductor element is mounted. And the heat sink is housed in a heat sink housing through hole formed in the printed wiring board. Further, in the above, as shown in the ninth invention, the printed wiring board may be provided with a through hole for heat dissipation.
【００１２】[0012]
【実施例】以下、実施例及び比較例により本発明を具体
的に説明する。 実施例１ 本実施例の表面実装用パッケージは、図１及び図２に示
すように、樹脂製基材１に設けられた半導体素子搭載用
貫通孔１１内に、半導体素子４を収納したものである。
即ち、本パッケージは、樹脂製基材１と導電層２と半導
体素子４と実装用端子部５とボンディングワイヤー６と
樹脂製封止部７とからなる。EXAMPLES The present invention will be specifically described below with reference to Examples and Comparative Examples. Example 1 As shown in FIGS. 1 and 2, the surface mounting package of this example has a semiconductor element 4 housed in a semiconductor element mounting through hole 11 provided in a resin base material 1. is there.
That is, the present package includes the resin base material 1, the conductive layer 2, the semiconductor element 4, the mounting terminal portion 5, the bonding wire 6, and the resin sealing portion 7.
【００１３】この樹脂性基材１は、図２に示すように、
正方形（縦３５ｍｍ、横３３ｍｍ、厚さ０．１ｍｍ）で
あるが、同図（一部平面図）の一点鎖線に示すように、
長尺状であって、そのリールトウリール方式にて搬送が
可能なように、送り用孔１３を両端側に形成させたもの
でもよい。尚、この正方形の基材は、この長尺状基材を
所定の大きさに切断して得たものである。この基材１
は、ガラスエポキシからなるが、他にポリエステル、ポ
リイミド等からなってもよい。また、この基材１には、
その中央に半導体素子搭載用貫通孔１１が形成され、そ
の周辺に全部で１３個のボンディングワイヤー用貫通孔
１２が形成されており、これが一対を構成している。
尚、長尺状基材の場合には、この対が多数、搬送方向に
並列されている。また、この対が短手方向にも複数列
（例えば２列、３列若しくは４列等）連続されており、
各列毎に切断した場合、図２の長尺状のものとなる。As shown in FIG. 2, this resinous substrate 1 has
Although it is a square (length 35 mm, width 33 mm, thickness 0.1 mm), as shown by the alternate long and short dash line in the figure (partial plan view),
The feed hole 13 may be formed in a long shape, and the feed holes 13 may be formed at both ends of the reel to reel so that the reel 13 can be conveyed. The square base material is obtained by cutting the long base material into a predetermined size. This base material 1
Is made of glass epoxy, but may be made of polyester, polyimide or the like. Further, the base material 1 includes
A through hole 11 for mounting a semiconductor element is formed in the center thereof, and a total of 13 through holes 12 for bonding wires are formed in the periphery of the through hole 11, which form a pair.
In the case of a long base material, a large number of this pair are arranged in parallel in the transport direction. Also, this pair is continuous in a plurality of rows (for example, two rows, three rows or four rows) in the lateral direction,
When each row is cut, it becomes the long shape of FIG.
【００１４】上記導電層（銅箔製）２は、半導体素子搭
載用貫通孔１１を塞ぐとともにこれよりも大きな面積で
もって、この脂製基材１の一方の面（下面）上に形成さ
れている。これは通常実施されるエッチングにより形成
され、またこの表面にはこれを保護するためのメッキ層
（ニッケル、金、半田等）が形成さている。そして、半
導体素子（５ｍｍ×５ｍｍ×０．３ｍｍ（厚さ））４
が、この導電層２の上に接着剤層３を介して接着され且
つ搭載されている。The conductive layer (made of copper foil) 2 is formed on one surface (lower surface) of the fat base material 1 so as to close the semiconductor element mounting through-hole 11 and to have a larger area. There is. This is formed by etching which is usually performed, and a plating layer (nickel, gold, solder, etc.) for protecting this is formed on this surface. Then, the semiconductor element (5 mm × 5 mm × 0.3 mm (thickness)) 4
Are bonded and mounted on the conductive layer 2 via the adhesive layer 3.
【００１５】上記実装用端子部５は、各ボンディングワ
イヤー用貫通孔１２を塞ぐとともにこれよりも大きな面
積（円形、尚円形以外に四角状等としてもよい。）でも
って、樹脂製基材１の下面上に形成されている。これは
上記導電層２と同様の構成であり、同様に形成されると
ともに、これらを一回のエッチング処理により同時に形
成される。また、この端子部５は、図３に示すように、
各ボンディングワイヤー用貫通孔を塞ぐ部分（四角形、
尚、丸形状等でもよい。）等）５１と、これを他領域に
導いてその他端に形成される端部（四角形、尚、丸形状
等でもよい。）５２とその両者を接続する中間帯部５３
とからなるものとすることができる。このようにするこ
とにより、適宜の位置にあるプリント配線基板８の上面
に形成された各接合用端子部８２とを適宜接続でき、接
続の自由度が増大する。この実装用端子部５は、図１に
示すように、プリント配線基板（尚、基材は８１を示
す。）８の上面に形成されている各接合用端子部８２に
電気的に接合される。The mounting terminal portion 5 closes the through holes 12 for the bonding wires and has a larger area (circular shape, square shape other than circular shape, etc.) and a larger area than that of the resin base material 1. It is formed on the lower surface. This has the same structure as the conductive layer 2 and is formed in the same manner, and these are formed simultaneously by one etching process. In addition, as shown in FIG.
Part that closes each through hole for bonding wire (square,
Incidentally, a round shape or the like may be used. ) Etc.) 51, an end portion (rectangular shape, round shape or the like) 52 that guides this to another region and is formed at the other end, and an intermediate band portion 53 that connects the two.
Can consist of and. By doing so, the bonding terminal portions 82 formed on the upper surface of the printed wiring board 8 at appropriate positions can be appropriately connected, and the degree of freedom of connection is increased. As shown in FIG. 1, the mounting terminal portion 5 is electrically joined to each joining terminal portion 82 formed on the upper surface of the printed wiring board (the base material indicates 81) 8. .
【００１６】上記ボンディングワイヤー６は、各実装用
端子部５と半導体素子４とをボンディングワイヤー用貫
通孔１２を介して、超音波ボンディング等により電気的
に接合されている。更に、これらのボンディングワイヤ
ー６及び半導体素子４を封止するための樹脂製封止部７
が、ポッティング法、トランスファーモールド法等によ
り形成されている。尚、一般的に知られるように、上記
樹脂製基材１の下面には、半田等により接合しない部分
や半田によるショートを防ぐ目的でソルダーレジスト
（永久レジスト）１４等を施しても良い。The bonding wire 6 is electrically connected to the mounting terminal portion 5 and the semiconductor element 4 through the bonding wire through hole 12 by ultrasonic bonding or the like. Further, a resin sealing portion 7 for sealing the bonding wire 6 and the semiconductor element 4
Are formed by a potting method, a transfer molding method, or the like. Incidentally, as is generally known, a solder resist (permanent resist) 14 or the like may be provided on the lower surface of the resin base material 1 for the purpose of preventing a portion not joined by solder or the like or a short circuit due to solder.
【００１７】また、上記ボンディングワイヤー用貫通孔
１２は、半導体素子の外形線に沿って直線状一列に周辺
配置されているが、これに限らず、例えば、図４に示す
ように千鳥配置（２列状のジグザグ配列）でもよいし、
図５に示すように３列状のジグザグ配列、図６に示すよ
うに３列状の平行配列、更には４列以上の列のジグザグ
配列等であってもよい。これらの場合は、半導体素子の
短い外形線の領域において多数のボンディングワイヤー
を取り付けることができる。 以上より、本実施例の表
面実装用パッケージは、薄型とすることができ、リール
トウリール方式にて、孔開け、エッチング、メッキ処
理、半導体素子の搭載等を連続的に行うことができる。
また、各実装用端子部５は半導体素子の下方位置よりも
外側に位置し、更にこの実装用端子部５及び接合相手の
各接合用端子部８２ともに薄膜の平面的なもののため、
その接合の信頼性が高い。The bonding wire through-holes 12 are arranged in a straight line along the outline of the semiconductor element, but the arrangement is not limited to this. For example, as shown in FIG. It may be a zigzag array in rows,
As shown in FIG. 5, a zigzag arrangement of three rows, a parallel arrangement of three rows as shown in FIG. 6, and a zigzag arrangement of four or more rows may be used. In these cases, a large number of bonding wires can be attached in the region of the short outline of the semiconductor element. As described above, the surface-mounting package of this embodiment can be made thin, and the reeling reel system can continuously perform punching, etching, plating, mounting of semiconductor elements, and the like.
Further, since each mounting terminal portion 5 is located outside the lower position of the semiconductor element, and both the mounting terminal portion 5 and each joining terminal portion 82 of the joining partner are thin-film planar ones,
The joint is highly reliable.
【００１８】実施例２ 本実施例の表面実装用パッケージは、図７に示すよう
に、樹脂製基材１には実施例１で設けられていた半導体
素子搭載用貫通孔がなく、半導体素子４が樹脂製基材１
の上面上に搭載されているものである。また、樹脂製封
止部７はダム７１によりせき止められている。その他の
構成は、実施例１と同じである。本パッケージは、厚さ
がやや厚くなるものの、リールトウリール方式にて製造
できること、各実装用端子部は半導体素子の下面よりも
外側に位置すること、及び接合の信頼性が高いことは同
様である。Example 2 In the surface mounting package of this example, as shown in FIG. 7, the resin base material 1 does not have the through hole for mounting the semiconductor element provided in the example 1, and the semiconductor element 4 is provided. Is a resin base material 1
Is mounted on the upper surface of. Further, the resin sealing portion 7 is dammed by the dam 71. Other configurations are the same as those in the first embodiment. Although this package is slightly thicker, it can be manufactured by the reel to reel method, that each mounting terminal is located outside the bottom surface of the semiconductor element, and that the reliability of bonding is high. is there.
【００１９】実施例３ 本実施例の表面実装用パッケージは、図８に示すよう
に、実装用端子部５と半導体素子４とをボンディングワ
イヤー用貫通孔を介してボンディングワイヤーを用いて
電気的に接合する場合、樹脂製基材１の上面上に他の導
電層６１が形成され、半導体素子４とこの他の導電層６
１とをボンディングワイヤー６ａを用いて電気的に接合
するとともに、この他の導電層６１と実装用端子部５と
を他のボンディングワイヤー６ｂを用いて、二段階にて
電気的に接合するものである。尚、図８では、二段階接
合は右側の実装用端子部５においてのみ示されている
が、これに限らず、左側に示す実装用端子部において利
用してもよいし、他の端子部において利用してもよい。
即ち、複数の端子部のうち、所望の端子部の１又は２以
上をこのように二段階接合してもよいし、更に３段階以
上の接合方式としてもよい。このような二段階又は三段
階以上の接合方式によれば、長いボンディングワイヤー
を用いることもなく、離れた位置にある接合用導電層に
安定的に接合できる。Embodiment 3 In the surface mounting package of this embodiment, as shown in FIG. 8, the mounting terminal portion 5 and the semiconductor element 4 are electrically connected to each other by using a bonding wire through a bonding wire through hole. When joining, another conductive layer 61 is formed on the upper surface of the resin base material 1, and the semiconductor element 4 and the other conductive layer 6 are formed.
1 is electrically connected using the bonding wire 6a, and the other conductive layer 61 and the mounting terminal portion 5 are electrically connected in two steps using the other bonding wire 6b. is there. In FIG. 8, the two-step joining is shown only in the mounting terminal portion 5 on the right side, but the present invention is not limited to this, and may be used in the mounting terminal portion shown on the left side, or in other terminal portions. You may use it.
That is, one or two or more of the desired terminal portions of the plurality of terminal portions may be joined in two stages as described above, or a joining method of three or more stages may be adopted. According to such a two-step or three-step or more joining method, it is possible to stably join to the joining conductive layer at a distant position without using a long bonding wire.
【００２０】実施例４ 本実施例の表面実装用パッケージは、図９に示すよう
に、ボンディングワイヤー６が挿通されるボンディング
ワイヤー用貫通孔１２以外に、電子部品搭載用貫通孔１
２ａを備え、この電子部品搭載用貫通孔１２ａには電子
部品９が配置される。そして、この電子部品（例えばキ
ャパシタ等）９の左側部及び右側部は、２分割された電
子部品用端子部９ａ及び９ｂの一方にて接合される。
尚、２分割以外にも３分割若しくは４以上の分割方法と
することもできる。以上より、半導体素子のみならず、
この電子部品９をも搭載できる。しかも、これが収納さ
れる電子部品搭載用貫通孔１２ａは、他のボンディング
ワイヤー用貫通孔１２と同時に孔開け形成されるので、
製造工程の複雑さはない。Embodiment 4 In the surface mounting package of this embodiment, as shown in FIG. 9, in addition to the bonding wire through hole 12 through which the bonding wire 6 is inserted, an electronic component mounting through hole 1 is formed.
2a, and the electronic component 9 is arranged in the through hole 12a for mounting the electronic component. Then, the left side portion and the right side portion of the electronic component (for example, a capacitor) 9 are joined at one of the divided electronic component terminal portions 9a and 9b.
In addition to the two divisions, the division method may be divided into three or four or more. From the above, not only semiconductor elements,
This electronic component 9 can also be mounted. Moreover, since the through hole 12a for mounting the electronic component in which this is housed is formed simultaneously with the other through holes 12 for bonding wires,
There is no complexity in the manufacturing process.
【００２１】実施例５ 本実施例は、図１０に例示されるようにパッケージ実装
装置を示すものである。即ち、実施例１にて示す表面実
装用パッケージ（図１及び図２に図示）が、この表面実
装用パッケージの実装用端子部５に対向する位置に接合
用端子部８２を備えるプリント配線基板８の表面に、半
田８３により、これらの両端子部（５及び８２）を接合
することにより実装されてなるものである。これは簡便
な構造であるとともに、薄型であり、また端子部同志が
平面接合のため接合の信頼性も高い。尚、一般的に知ら
れるように、半田等により接合しない部分や半田による
ショートを防ぐ目的でソルダーレジスト（永久レジス
ト）１４等を施しても良い。Embodiment 5 This embodiment shows a package mounting apparatus as illustrated in FIG. That is, the surface mounting package (illustrated in FIGS. 1 and 2) according to the first embodiment includes the printed wiring board 8 having the joining terminal portion 82 at a position facing the mounting terminal portion 5 of the surface mounting package. These terminal portions (5 and 82) are mounted on the surface of the above with solder 83 so as to be mounted. This is a simple structure, is thin, and has a high reliability of bonding because the terminals are planar bonded. As is generally known, a solder resist (permanent resist) 14 or the like may be applied for the purpose of preventing a portion not joined by solder or the like or a short circuit due to solder.
【００２２】また、実施例２にて示す表面実装用パッケ
ージ（図７に図示）が、同図に示すプリント配線基板８
の表面に接合されたものとすることもできる。これはや
や厚くなるものの、簡便な構造であるとともに、同様に
接合の信頼性が高い。The surface mounting package (shown in FIG. 7) of the second embodiment is the same as the printed wiring board 8 shown in FIG.
It can also be bonded to the surface of. Although this is slightly thicker, it has a simple structure and similarly has high reliability of bonding.
【００２３】実施例６ 本実施例は、図１１に例示されるように放熱性に優れた
パッケージ実装装置を示すものである。即ち、表面実装
用パッケージを構成する樹脂製基材の下面上であって且
つ半導体素子４が搭載される下方側には、放熱体１０が
接着剤等により形成され、この放熱体１０がプリント配
線基板８に形成された放熱体収納用貫通孔８４内に収納
されている。この放熱体１０は同図に示すように、半導
体素子用貫通孔及び基材の下側には接着剤層１７を介し
て銅箔層１８が形成され、この下に接着剤層１９を介し
て接着されている。尚、この銅箔層１８及び接着剤層１
９を用いずに、直接に基材に接着剤層を介して接着した
構成としてもよい。この放熱体１０は、銅や銅タングス
テン等により構成されている。更に、この貫通孔（例え
ば四角状等）８４の周辺には、複数（例えば６〜１２
個、特に好ましくは８個）の放熱用貫通孔８５が形成さ
れている。以上より、放熱性に優れるので、半導体素子
等の寿命、信頼性を向上させることができる。尚、同図
においてプリント配線基板８を接着する前の表面実装用
パッケージ、即ち同図に示すような基材に放熱体１０を
接着した構成のものも、本発明の表面実装用パッケージ
の一例とすることができる。また、上記実施例では放熱
体１０及び放熱用貫通孔８５の両方が備わっているが、
この一方のみを備えた構成としてもよい。Embodiment 6 This embodiment shows a package mounting apparatus having excellent heat dissipation as illustrated in FIG. That is, on the lower surface of the resin base material that constitutes the surface mounting package and on the lower side on which the semiconductor element 4 is mounted, the heat radiator 10 is formed with an adhesive or the like, and the heat radiator 10 is printed wiring. It is accommodated in a through hole 84 for accommodating a radiator formed in the substrate 8. As shown in the figure, in this heat radiator 10, a copper foil layer 18 is formed below a through hole for a semiconductor element and a base material via an adhesive layer 17, and an adhesive layer 19 is interposed below the copper foil layer 18. It is glued. The copper foil layer 18 and the adhesive layer 1
Instead of using 9, the adhesive may be directly bonded to the base material via the adhesive layer. The radiator 10 is made of copper, copper tungsten, or the like. Further, a plurality (for example, 6 to 12) is formed around the through hole (for example, square shape) 84.
(Especially preferably 8) through holes 85 for heat dissipation are formed. As described above, since the heat dissipation is excellent, the life and reliability of the semiconductor element and the like can be improved. Incidentally, the surface mounting package before the printed wiring board 8 is adhered in the figure, that is, the structure in which the radiator 10 is adhered to the base material as shown in the figure is also an example of the surface mounting package of the present invention. can do. Further, in the above embodiment, both the heat radiator 10 and the heat radiation through hole 85 are provided,
A configuration including only one of these may be adopted.
【００２４】尚、本発明においては、前記具体的実施例
に示すものに限られず、目的、用途に応じて本発明の範
囲内で種々変更した実施例とすることができる。即ち、
樹脂製基材の大きさ（縦、横）、厚さ、これが長尺状の
場合はその長さ、また半導体素子搭載用貫通孔、ボンデ
ィングワイヤー用貫通孔及び電子部品搭載用貫通孔の大
きさ、配置数、取り囲む用に配置する場合のその配置方
法等は、上記実施例に示すものに限定されない。上記実
装用端子部及び接合用端子部の平面形状（丸型、四角
型、楕円型、所定場所に引き出された所定パターン形状
等）、その大きさ等も限定されず、種々選択される。ま
た、上記実施例１〜４にて示す各表面実装用パッケージ
を、所定のプリント配線基板に接合して各種のパッケー
ジ実装装置とすることもできる。The present invention is not limited to the specific examples described above, but various modifications may be made within the scope of the present invention depending on the purpose and application. That is,
The size (length, width) and thickness of the resin base material, if it is long, its length, and the size of the semiconductor element mounting through hole, bonding wire through hole, and electronic component mounting through hole. The number of arrangements, the arrangement method in the case of arranging for surrounding, etc. are not limited to those shown in the above embodiment. The planar shape (round shape, square shape, elliptical shape, predetermined pattern shape drawn out at a predetermined place, etc.) of the mounting terminal portion and the joining terminal portion, the size thereof, etc. are not limited, and various selections can be made. Further, the surface mounting packages shown in Examples 1 to 4 may be joined to a predetermined printed wiring board to form various package mounting devices.
【００２５】更に、参考例として、図７に示す樹脂製基
材の上に半導体素子を配置した場合、この基材を介して
その下面であって且つこの半導体素子の下方に位置する
場所に放熱体を取り付け、これを上記実施例６にて示す
プリント配線基板の所定孔内に収納配置したものとする
こともできる。この場合は、パッケージ実装装置の厚さ
がやや厚くなるものの、簡便な構造であるとともに、同
様に接合の信頼性が高い。Further, as a reference example, when the semiconductor element is arranged on the resin base material shown in FIG. 7, heat is radiated to the place below the semiconductor element through the base material. It is also possible to attach the body and store it in a predetermined hole of the printed wiring board shown in the sixth embodiment. In this case, although the thickness of the package mounting device is slightly thick, the package mounting device has a simple structure and the bonding reliability is high.
【００２６】[0026]
【発明の効果】本第１発明の表面実装用パッケージは、
薄型とすることができ、リールトウリール方式にて、孔
開け、エッチング及びメッキ処理等を連続的に行うこと
ができ、また、実装用端子部と接合相手の各接合用端子
部との接合が平面接合のため、その接合の信頼性が高
い。本第２発明の表面実装用パッケージは、厚さがやや
厚くなるものの、リールトウリール方式にて製造でき、
また接合の信頼性も高い。本第３発明の表面実装用パッ
ケージは、実装用端子部と半導体素子とを複数段階にて
電気的に接合するので、長いボンディングワイヤーを用
いることもなく、離れた位置にある接合用導電層と安定
的に接合できる。The surface mounting package of the first invention is
It can be made thin, and can be continuously drilled, etched and plated by the reel to reel system, and the mounting terminal can be joined to each joining terminal of the mating partner. Since it is a plane bond, the reliability of the bond is high. Although the surface mounting package of the second invention is slightly thicker, it can be manufactured by the reel to reel system.
Also, the reliability of joining is high. In the surface mounting package of the third aspect of the present invention, since the mounting terminal portion and the semiconductor element are electrically bonded in a plurality of steps, a bonding conductive layer at a distant position can be used without using a long bonding wire. Can be joined stably.
【００２７】本第４発明の表面実装用パッケージにおい
ては、ボンディングワイヤー用貫通孔の配列がジグザグ
の千鳥配置又は他の波状形状のため、半導体素子の短い
外形線の領域において多数のボンディングワイヤーを互
いに接触しないように容易に取り付けることができる。
本第５発明の表面実装用パッケージは、所定のスルーホ
ールに電子部品が配置されので、１枚の樹脂製基材に半
導体素子のみならずキャパシタ等の電子部品をも、複雑
な工程を必要とせずに搭載できる。本第６発明の表面実
装用パッケージは、長尺状の樹脂製基材を用いるので、
リールトウリール方式にて製造でき、大変、製造効率に
優れる。In the surface mounting package of the fourth aspect of the present invention, since the bonding wire through holes are arranged in a zigzag staggered arrangement or another wavy shape, a large number of bonding wires are connected to each other in the region of the short outline of the semiconductor element. It can be easily attached without touching.
In the surface mounting package of the fifth aspect of the invention, the electronic parts are arranged in the predetermined through holes, so that not only the semiconductor elements but also the electronic parts such as the capacitors need not be complicatedly processed on one resin base material. Can be installed without. Since the surface mount package of the sixth invention uses the elongated resin base material,
It can be manufactured by the reel to reel system, and it has excellent manufacturing efficiency.
【００２８】本第７発明のパッケージ実装装置は、簡便
な構造であるとともに、薄型であり、また平面接合のた
め接合の信頼性も高い。本第８発明のパッケージ実装装
置においては、半導体素子が搭載される下方側に放熱体
が形成されているので、また本第９発明のパッケージ実
装装置においては、放熱用貫通孔が形成されているの
で、いずれも放熱性に優れ、そのため半導体素子等の寿
命を向上させることができる。The package mounting apparatus according to the seventh aspect of the present invention has a simple structure, is thin, and is highly reliable because of the planar bonding. In the package mounting apparatus of the eighth aspect of the present invention, the heat radiator is formed on the lower side on which the semiconductor element is mounted, and in the package mounting apparatus of the ninth aspect of the invention, the heat dissipation through hole is formed. Therefore, all of them have excellent heat dissipation properties, and therefore, the life of the semiconductor element or the like can be improved.
【図１】主として実施例１に係る表面実装用パッケージ
を説明する縦断面図である。FIG. 1 is a vertical cross-sectional view mainly illustrating a surface mounting package according to a first embodiment.
【図２】実施例１に係る表面実装用パッケージの平面図
である。FIG. 2 is a plan view of the surface mounting package according to the first embodiment.
【図３】表面実装用パッケージにおいて実装用端子部の
平面形状を変えた場合を示す説明図である。FIG. 3 is an explanatory diagram showing a case where the planar shape of the mounting terminal portion is changed in the surface mounting package.
【図４】ボンディングワイヤー用貫通孔の配列が千鳥配
置（２列状のジグザグ配列）の状態を示す説明図であ
る。FIG. 4 is an explanatory diagram showing a state in which the bonding wire through holes are arranged in a staggered arrangement (two-row zigzag arrangement).
【図５】ボンディングワイヤー用貫通孔の配列が３列状
のジグザグ配列の状態を示す説明図である。FIG. 5 is an explanatory diagram showing a zigzag arrangement of three through holes for bonding wires.
【図６】ボンディングワイヤー用貫通孔の配列が３列状
の波型平行配列の状態を示す説明図である。FIG. 6 is an explanatory diagram showing a state in which the through holes for bonding wires are arranged in a three-row corrugated parallel arrangement.
【図７】主として実施例２に係る表面実装用パッケージ
の縦断面図である。FIG. 7 is a vertical cross-sectional view of a surface mounting package mainly according to a second embodiment.
【図８】実施例３に係る表面実装用パッケージの縦断面
図である。FIG. 8 is a vertical sectional view of a surface mounting package according to a third embodiment.
【図９】主として実施例４に係る表面実装用パッケージ
の縦断面図である。FIG. 9 is a vertical cross-sectional view of a surface-mounting package mainly according to a fourth embodiment.
【図１０】実施例５に係るパッケージ実装装置の縦断面
図である。FIG. 10 is a vertical sectional view of a package mounting apparatus according to a fifth embodiment.
【図１１】実施例６に係る放熱性に優れるパッケージ実
装装置の縦断面図である。FIG. 11 is a vertical cross-sectional view of a package mounting device having excellent heat dissipation according to the sixth embodiment.
【図１２】従来の表面実装用パッケージの一例を示す縦
断面図である。FIG. 12 is a vertical cross-sectional view showing an example of a conventional surface mount package.
【図１３】図１２に示す表面実装用パッケージを用いた
製作したパッケージ実装装置の縦断面図である。13 is a vertical cross-sectional view of a package mounting device manufactured using the surface mounting package shown in FIG.
１；樹脂製基材、１１；半導体素子搭載用貫通孔、１
２；ボンディングワイヤー用貫通孔、１２ａ；電子部品
搭載用貫通孔、２；導電層、３；接着層、４；半導体素
子、５；実装用端子部、６；ボンディングワイヤー、６
１；他の導電層、７；樹脂製封止部、７１；ダム、８；
プリント配線基板、８２；接合用端子部、８４；放熱体
収納用貫通孔、８５；放熱用貫通孔、９；電子部品、９
ａ、９ｂ；電子部品用端子部、１０；放熱体。1; Resin base material, 11; Through hole for mounting semiconductor element, 1
2; Through hole for bonding wire, 12a; Through hole for mounting electronic component, 2; Conductive layer, 3; Adhesive layer, 4; Semiconductor element, 5; Mounting terminal portion, 6; Bonding wire, 6
1; other conductive layer, 7; resin sealing part, 71; dam, 8;
Printed wiring board, 82; joining terminal part, 84; through hole for housing radiator, 85; through hole for heat dissipation, 9; electronic component, 9
a, 9b: terminal parts for electronic parts, 10: heat radiator.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/36 Ｚ 8824−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H05K 3/36 Z 8824-4E
Claims (9)
子搭載用貫通孔の周辺に配置された複数のボンディング
ワイヤー用貫通孔を有する樹脂製基材と、該半導体素子
搭載用貫通孔を塞ぐように該樹脂製基材の一方の面上に
形成される導電層と、該導電層上に接着剤層を介して接
着され且つ搭載される半導体素子と、上記ボンディング
ワイヤー用貫通孔を塞ぐように上記樹脂製基材の上記一
方の面上に形成される実装用端子部と、該実装用端子部
と上記半導体素子とを上記ボンディングワイヤー用貫通
孔を介して電気的に接合するボンディングワイヤーと、
該ボンディングワイヤー及び上記半導体素子を封止する
樹脂製封止部とからなることを特徴とする表面実装用パ
ッケージ。1. A resin base material having a through hole for mounting a semiconductor element and a plurality of through holes for bonding wires arranged around the through hole for mounting a semiconductor element, and a through hole for mounting the semiconductor element. A conductive layer formed on one surface of the resin base material, a semiconductor element bonded and mounted on the conductive layer via an adhesive layer, and a through hole for the bonding wire. A mounting terminal portion formed on the one surface of the resin base material, and a bonding wire that electrically joins the mounting terminal portion and the semiconductor element through the bonding wire through hole,
A surface mounting package comprising the bonding wire and a resin sealing portion for sealing the semiconductor element.
有する樹脂製基材と、上記ボンディングワイヤー用貫通
孔を塞ぐように上記樹脂製基材の上記一方の面上に形成
される実装用端子部と、該樹脂製基材の他方の面上であ
って上記ボンディングワイヤー用貫通孔に取り囲まれる
ように搭載される半導体素子と、上記実装用端子部と上
記半導体素子とを上記ボンディングワイヤー用貫通孔を
介して電気的に接合するボンディングワイヤーと、該ボ
ンディングワイヤー及び上記半導体素子を封止する樹脂
製封止部とからなることを特徴とする表面実装用パッケ
ージ。2. A resin base material having a plurality of bonding wire through holes, and a mounting terminal portion formed on the one surface of the resin base material so as to close the bonding wire through holes. A semiconductor element mounted on the other surface of the resin base material so as to be surrounded by the through hole for the bonding wire, the mounting terminal portion and the semiconductor element through the through hole for the bonding wire. A surface mounting package comprising a bonding wire electrically connected via a bonding wire, and a resin sealing part for sealing the bonding wire and the semiconductor element.
ージにおいて、上記実装用端子部と上記半導体素子とを
上記ボンディングワイヤー用貫通孔を介してボンディン
グワイヤーを用いて電気的に接合する場合、上記樹脂製
基材の上記他方の面上に他の導電層が形成され、上記半
導体素子と該他の導電層とをボンディングワイヤーを用
いて電気的に接合するとともに、該他の導電層と上記実
装用端子部とを他のボンディングワイヤーを用いて電気
的に接合することを特徴とする表面実装用パッケージ。3. The surface mounting package according to claim 1, wherein when the mounting terminal portion and the semiconductor element are electrically connected to each other by using a bonding wire through the bonding wire through hole, Another conductive layer is formed on the other surface of the resin base material, the semiconductor element and the other conductive layer are electrically joined using a bonding wire, and the other conductive layer and the above A surface mounting package, which is electrically connected to a mounting terminal portion using another bonding wire.
上記半導体素子を直線状に取り囲むのではなく、千鳥状
若しくは波状に配置されることによって、より多数の配
置を確保した請求項１〜３記載の表面実装用パッケー
ジ。4. The through hole for a bonding wire,
The surface mounting package according to claim 1, wherein a larger number of arrangements are ensured by arranging the semiconductor elements in a zigzag shape or a wave shape, not surrounding the semiconductor elements in a straight line.
ジにおいて、ボンディングワイヤーが挿通される上記ボ
ンディングワイヤー用貫通孔及び半導体素子搭載用貫通
孔以外に、電子部品搭載用貫通孔を備え、該電子部品搭
載用貫通孔には電子部品を配置し、且つ該電子部品に接
合されるとともに該電子部品搭載用貫通孔を塞ぐように
上記樹脂製基材の上記一方の面上に形成される、少なく
とも２分割された電子部品用端子部を備える請求項１〜
４記載の表面実装用パッケージ。5. The surface mounting package according to claim 1, further comprising an electronic component mounting through-hole, in addition to the bonding wire through-hole into which the bonding wire is inserted and the semiconductor element mounting-through hole. An electronic component is arranged in the electronic component mounting through hole, and is formed on the one surface of the resin base material so as to be bonded to the electronic component and close the electronic component mounting through hole. An electronic component terminal portion divided into at least two is provided.
The surface mounting package described in 4.
〜５記載の表面実装用パッケージ。6. The resin base material is elongated.
The package for surface mounting according to 5 above.
ジが、該表面実装用パッケージの上記実装用端子部に対
向する位置に接合用端子部を備えるプリント配線基板の
表面に、該実装用端子部と該接合用端子部とを接合する
ことにより実装されてなることを特徴とするパッケージ
実装装置。7. The surface mounting package according to claim 1, wherein the surface mounting package has a bonding terminal portion at a position facing the mounting terminal portion of the surface mounting package. A package mounting apparatus, which is mounted by joining a terminal portion and the joining terminal portion.
構成する上記樹脂製基材の上記一方の面上であって且つ
上記半導体素子が搭載される下方側には、放熱体が形成
され、該放熱体がプリント配線基板に形成された放熱体
収納用貫通孔内に収納される請求項７記載のパッケージ
実装装置。8. A heat radiator is formed on the one surface of the resin base material forming the surface mounting package according to claim 7 and below the semiconductor element is mounted. 8. The package mounting device according to claim 7, wherein the radiator is housed in a radiator housing through hole formed in the printed wiring board.
孔を備える請求項８記載のパッケージ実装装置。9. The package mounting apparatus according to claim 8, wherein the printed wiring board has a through hole for heat dissipation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02901494A JP3630713B2 (en) | 1994-01-31 | 1994-01-31 | Surface mounting package and package mounting apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02901494A JP3630713B2 (en) | 1994-01-31 | 1994-01-31 | Surface mounting package and package mounting apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07221427A true JPH07221427A (en) | 1995-08-18 |
| JP3630713B2 JP3630713B2 (en) | 2005-03-23 |
Family
ID=12264561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02901494A Expired - Fee Related JP3630713B2 (en) | 1994-01-31 | 1994-01-31 | Surface mounting package and package mounting apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3630713B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1075074A (en) * | 1996-08-30 | 1998-03-17 | Tdk Corp | Electronic part using mid package |
| JP2013229490A (en) * | 2012-04-26 | 2013-11-07 | Kyocera Corp | Wiring board and electronic apparatus |
| WO2017011049A3 (en) * | 2015-04-28 | 2017-02-16 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
| WO2021251170A1 (en) * | 2020-06-12 | 2021-12-16 | 株式会社オートネットワーク技術研究所 | Substrate connection structure and wiring module for vehicle |
-
1994
- 1994-01-31 JP JP02901494A patent/JP3630713B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1075074A (en) * | 1996-08-30 | 1998-03-17 | Tdk Corp | Electronic part using mid package |
| JP2013229490A (en) * | 2012-04-26 | 2013-11-07 | Kyocera Corp | Wiring board and electronic apparatus |
| WO2017011049A3 (en) * | 2015-04-28 | 2017-02-16 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
| CN107709226A (en) * | 2015-04-28 | 2018-02-16 | 伊文萨思公司 | Side surface contact element is coupled to circuit platform |
| WO2021251170A1 (en) * | 2020-06-12 | 2021-12-16 | 株式会社オートネットワーク技術研究所 | Substrate connection structure and wiring module for vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3630713B2 (en) | 2005-03-23 |
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