JP3398556B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3398556B2
JP3398556B2 JP01471797A JP1471797A JP3398556B2 JP 3398556 B2 JP3398556 B2 JP 3398556B2 JP 01471797 A JP01471797 A JP 01471797A JP 1471797 A JP1471797 A JP 1471797A JP 3398556 B2 JP3398556 B2 JP 3398556B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
semiconductor
manufacturing
element mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01471797A
Other languages
Japanese (ja)
Other versions
JPH10199899A (en
Inventor
俊也 松原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tech Inc
Original Assignee
Mitsui High Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tech Inc filed Critical Mitsui High Tech Inc
Priority to JP01471797A priority Critical patent/JP3398556B2/en
Publication of JPH10199899A publication Critical patent/JPH10199899A/en
Application granted granted Critical
Publication of JP3398556B2 publication Critical patent/JP3398556B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、生産性及び実装の
信頼性を向上できるBGA型(Ball Grid A
rray)の半導体装置、特に、樹脂基板の一面側にリ
ードパターンを有し、他面側に半導体素子の搭載領域を
有する金属基板シートを接合して構成された半導体素子
搭載基板を用いたBGA型の半導体装置の製造方法に関
する。
TECHNICAL FIELD The present invention relates to a BGA type (Ball Grid A) capable of improving productivity and mounting reliability.
rray) semiconductor device, in particular, a BGA type using a semiconductor element mounting substrate configured by bonding a metal substrate sheet having a lead pattern on one surface side of a resin substrate and a semiconductor element mounting region on the other surface side. And a method for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】従来、IC、LSI等の半導体装置の実
装は、半導体装置の外周縁に沿って、J型、ガルウイン
グ型等の所要の形状に形成された複数のアウターリード
を突出し、このアウターリードをプリント配線基板(P
WB)等の実装基板上に形成された配線パターンのマウ
ンティング・パッドに半田を用いて接続することによっ
て行なわれている。ところが、この実装方法において
は、比較的広い面積の実装領域を必要とし、装置の小型
化に対応できないという問題がある。そこで、近年、半
導体素子の微細化及び半導体装置のダウン・サイジング
化、低コスト化に対応して、半導体装置の複数の外部接
続端子に半田ボールを用い、これを実装基板上に実装す
る装置(BGAと称される)が、例えば特開平3−99
456号公報、特開平4−277636号公報等におい
て提案されている。これらの装置によれば、前記複数の
半田ボールのそれぞれに対応して設けた実装基板上の複
数のマウンティング・パッド上に半導体装置の位置決め
を行って載置した後、加熱により、易溶融性の半田ボー
ルをリフローし、実装基板上に同時に接続できるので、
半導体装置の実装が容易となる利点がある。
2. Description of the Related Art Conventionally, when mounting a semiconductor device such as an IC or an LSI, a plurality of outer leads formed in a required shape such as a J type and a gull wing type are protruded along the outer peripheral edge of the semiconductor device, and the outer leads are formed. Printed wiring board (P
This is performed by using solder to connect to a mounting pad of a wiring pattern formed on a mounting board such as WB). However, this mounting method has a problem in that it requires a mounting area having a relatively large area and cannot be made smaller in size. Therefore, in recent years, in response to miniaturization of semiconductor elements, downsizing of semiconductor devices, and cost reduction, an apparatus for mounting solder balls on a mounting board using solder balls for a plurality of external connection terminals of the semiconductor device ( (Referred to as BGA), for example, JP-A-3-99.
No. 456, Japanese Patent Laid-Open No. 4-277636, and the like. According to these devices, the semiconductor device is positioned and placed on the plurality of mounting pads on the mounting substrate provided corresponding to each of the plurality of solder balls, and then the semiconductor device is easily melted by heating. Since the solder balls can be reflowed and connected to the mounting board at the same time,
There is an advantage that the semiconductor device can be easily mounted.

【0003】前記BGA型の半導体装置は、例えば、次
のような方法によって製造されている。即ち、熱伝導性
を有する金属基材シートに素子搭載部を含む複数のユニ
ット領域を縦横方向に密接して整列した金属基板シート
シートとこれに接合される回路基板シートシートと重層
状態で接合する。この回路基板シートシートは、片面に
銅箔層を設けた所定の電気的絶縁性樹脂基材シートに、
中央部に半導体素子に対応した開口部と、この開口部に
沿ってかつ同開口部を取り囲むように放射状に配列され
た複数の導体リードから成るリードパターンと、導体リ
ードをエリアアレイ状に露出させる複数の空間部を設け
たソルダーレジスト膜とからなる複数のユニット領域を
縦横方向に密接して配列して構成されている。このよう
にして形成された半導体素子搭載基板シートを、各ユニ
ット領域を区分する縦横の境界線に沿って切断分離を行
い、図4に示すような個別の半導体素子搭載基板60を
多数形成し、この半導体素子搭載基板60を搬送キャリ
アに搭載して、又は個々に半導体装置の組立ラインに供
給、位置決めし、導電性接着剤を介在させて、半導体素
子61の搭載を行なう。次に、それぞれボンディングワ
イヤ62の一端部をワイヤボンディングパッドの一つに
接続し、他端部を半導体素子61に設けられる電極端子
の一つに接続して電気的導通回路を形成するワイヤボン
ディングを行なう。その後、図5に示すように、半導体
素子61、ボンディングワイヤ62、ワイヤボンディン
グパッドをポッティング樹脂63により樹脂封止するポ
ッティングモールドを行なう。そして、予め形成したソ
ルダーレジスト膜64上にグリッドアレイ状に露出した
複数の前記外部接続端子65上に、突出状態で半田ボー
ル66をそれぞれ接続して個別の半導体装置67を製造
していた。
The BGA type semiconductor device is manufactured, for example, by the following method. That is, a metal substrate sheet having a plurality of unit regions including element mounting portions closely aligned in the vertical and horizontal directions on a metal base sheet having thermal conductivity and a circuit board sheet sheet to be joined to the metal substrate sheet sheet are joined in a multi-layered state. . This circuit board sheet sheet is a predetermined electrically insulating resin base sheet having a copper foil layer on one side,
An opening corresponding to the semiconductor element is formed in the central portion, a lead pattern including a plurality of conductor leads radially arranged along the opening and surrounding the opening, and the conductor leads are exposed in an area array form. A plurality of unit regions composed of a solder resist film having a plurality of spaces are closely arranged in the vertical and horizontal directions. The semiconductor element mounting substrate sheet thus formed is cut and separated along the vertical and horizontal boundaries that divide each unit area, and a large number of individual semiconductor element mounting substrates 60 as shown in FIG. 4 are formed. The semiconductor element mounting board 60 is mounted on a carrier or individually supplied to an assembly line of a semiconductor device for positioning, and the semiconductor element 61 is mounted by interposing a conductive adhesive. Next, one end of each of the bonding wires 62 is connected to one of the wire bonding pads, and the other end thereof is connected to one of the electrode terminals provided on the semiconductor element 61 to form an electrical conduction circuit. To do. Thereafter, as shown in FIG. 5, potting mold is performed in which the semiconductor element 61, the bonding wires 62, and the wire bonding pads are resin-sealed with the potting resin 63. Then, the solder balls 66 are respectively connected in a protruding state on the plurality of external connection terminals 65 exposed in a grid array on the solder resist film 64 formed in advance to manufacture individual semiconductor devices 67.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、前記し
た従来例に係る半導体装置の製造方法にあっては、複数
の個別のユニット区画領域を有する金属基板シートシー
トと回路基板シートシートとが集積的に熱圧着された半
導体素子搭載基板シートから切断分離を行って、個々の
半導体素子搭載基板60が形成されているので、個別の
半導体素子搭載基板60の搬送や位置決め等の取り扱い
が煩雑となり、位置ずれや取扱い中の損傷による品質の
低下や半導体素子実装の作業効率が低下し、生産性を著
しく阻害するという問題が生じていた。さらに、個別の
半導体素子搭載基板60を搬送キャリアに位置決めする
ために高価な実装設備を必要とし、半導体装置の製造コ
ストを上昇させるという経済性の問題が生じていた。ま
た、半導体素子61は半導体素子搭載基板60の上に搭
載し、更にはその上からワイヤボンディングを行うの
で、半導体素子61が少し厚い場合には実装が困難であ
るという問題があった。本発明はかかる事情に鑑みてな
されたもので、半導体素子等の実装の際に、搬送及び位
置決め等の作業性を向上することができて半導体素子等
の実装を容易に行うことができ、更には半導体素子自体
が多少厚い場合であっても容易に実装が可能で、しか
も、半導体装置の生産性を向上させることのできるBG
A型の半導体装置における半導体装置の製造方法を提供
することを目的とする。
However, in the method of manufacturing a semiconductor device according to the conventional example described above, the metal substrate sheet sheet and the circuit substrate sheet sheet having a plurality of individual unit partition regions are integrated. Since the individual semiconductor element mounting substrates 60 are formed by cutting and separating from the semiconductor element mounting substrate sheet that has been thermocompression bonded, handling such as transportation and positioning of the individual semiconductor element mounting substrates 60 becomes complicated and misalignment occurs. There is a problem that the quality is deteriorated due to the damage during the handling and the working efficiency of the semiconductor element mounting is lowered, and the productivity is significantly hindered. Furthermore, an expensive mounting facility is required to position the individual semiconductor element mounting substrate 60 on the carrier, which causes an economical problem of increasing the manufacturing cost of the semiconductor device. In addition, since the semiconductor element 61 is mounted on the semiconductor element mounting substrate 60 and wire bonding is performed from thereover, there is a problem that mounting is difficult when the semiconductor element 61 is a little thick. The present invention has been made in view of such circumstances, when mounting a semiconductor element or the like, it is possible to improve workability such as conveyance and positioning, and to easily mount the semiconductor element or the like. Is a BG that can be easily mounted even when the semiconductor element itself is slightly thick and can improve the productivity of the semiconductor device.
An object of the present invention is to provide a method of manufacturing a semiconductor device in an A type semiconductor device.

【0005】[0005]

【課題を解決するための手段】前記目的に沿う請求項1
記載の半導体装置の製造方法は、中央に半導体素子が搭
載され、その周囲には該半導体素子の複数の電極パッド
にボンディングワイヤを介して連結された複数のリード
からなるリードパターンを有し、しかもそれぞれの前記
リードにはグリッドアレイ状に配置されて接続端子とな
る複数の半田ボール又はバンプが設けられた半導体装置
の製造方法であって、所要数の前記半導体装置が縦横に
並置可能な広さを有すると共に熱伝導性の良好な金属基
板シートを用意し、それぞれの半導体装置の素子搭載部
の窪み加工を行って、その周囲より下部位置に形成する
と共に、その表面に所定の下地めっきを行う第1工程
と、前記金属基板シート上に形成される複数の半導体装
置の素子搭載部に符合する開口部が形成され、しかも該
開口部の周囲には、該開口部に配置される半導体素子に
連結されるリードパターンがエッチング加工によって形
成された回路基板シートを用意する第2工程と、前記第
1工程で製造された金属基板シートに、前記第2工程で
用意された回路基板シートをそれぞれの前記素子搭載部
に開口部を一致させて接合して半導体素子搭載基板シー
トを造る第3工程と、前記半導体素子搭載基板シートを
搬送プレート上に位置決め載置し、前記半導体素子搭載
基板シートをX方向及びY方向に所定距離だけ移送し
て、それぞれの素子搭載部に半導体素子を搭載し、所定
のワイヤボンディングを行ってそれぞれの半導体素子の
端子パッドと前記リードパターンとを連結する第4工程
と、それぞれの前記半導体素子及びワイヤボンディング
された部分を、ポッティングモールド又はインジェンク
ションモールドにより樹脂封止する第5工程と、前記リ
ードパターンの各外部接続端子ランドに前記半田ボール
又はバンプを形成する第6工程と、以上の工程によっ
て、半導体装置が縦横に並置された連結半導体装置から
単一の半導体装置を切断分離する第7工程とを有してい
る。また、請求項2記載の半導体装置の製造方法は、請
求項1記載の半導体装置の製造方法において、第1工程
における前記窪み加工は、プレス処理によって行ってい
る。請求項3記載の半導体装置の製造方法は、請求項1
記載の半導体装置の製造方法は、第1工程における前記
窪み加工は、エッチング処理によって行っている。請求
項4記載の半導体装置の製造方法は、請求項1〜3のい
ずれか1項に記載の半導体装置の製造方法における第2
工程において、前記回路基板シートの前記外部接続端子
ランドを除く部分には、ソルダーレジスト膜が形成され
ている。なお、以上の発明において、熱伝導性の良好な
金属基板シートには、純銅の基板の他、銅合金の基板を
含む。
A method according to the above-mentioned object.
According to the method for manufacturing a semiconductor device described above, a semiconductor element is mounted in the center, and a periphery thereof has a lead pattern including a plurality of leads connected to a plurality of electrode pads of the semiconductor element via bonding wires, and A method for manufacturing a semiconductor device in which a plurality of solder balls or bumps, which are arranged in a grid array and serve as connection terminals, are provided on each of the leads, and a required number of the semiconductor devices are arranged side by side vertically and horizontally. A metal substrate sheet having good thermal conductivity is prepared, and a recess is formed in the element mounting portion of each semiconductor device to form a lower portion than its periphery, and a predetermined undercoating is performed on its surface. In the first step, openings corresponding to the element mounting portions of the plurality of semiconductor devices formed on the metal substrate sheet are formed, and around the openings, A second step of preparing a circuit board sheet in which a lead pattern connected to a semiconductor element arranged in the opening is formed by an etching process, and a metal board sheet manufactured in the first step. A third step of manufacturing the prepared circuit board sheet by joining the prepared circuit board sheets to the respective element mounting portions so that the openings are aligned with each other, and positioning the semiconductor element mounting substrate sheet on the transport plate. The semiconductor element mounting substrate sheet is moved by a predetermined distance in the X direction and the Y direction, the semiconductor element is mounted on each element mounting portion, and predetermined wire bonding is performed to perform terminal bonding of each semiconductor element and the lead. The fourth step of connecting the pattern and the semiconductor element and the wire-bonded portion are connected to each other by potting mold or A fifth step of resin-sealing with an injection mold, a sixth step of forming the solder balls or bumps on the external connection terminal lands of the lead pattern, and a connection in which semiconductor devices are arranged side by side vertically and horizontally by the above steps. A seventh step of cutting and separating a single semiconductor device from the semiconductor device. A semiconductor device manufacturing method according to a second aspect of the present invention is the method of manufacturing a semiconductor device according to the first aspect, wherein the recessing process in the first step is performed by a press process. A method for manufacturing a semiconductor device according to claim 3 is the method according to claim 1.
In the method of manufacturing a semiconductor device described above, the recess processing in the first step is performed by etching. A method of manufacturing a semiconductor device according to claim 4 is the second method in the method of manufacturing a semiconductor device according to any one of claims 1 to 3.
In the step, a solder resist film is formed on the portion of the circuit board sheet excluding the external connection terminal lands. In the above invention, the metal substrate sheet having good thermal conductivity includes a pure copper substrate and a copper alloy substrate.

【0006】請求項1〜4記載の半導体装置の製造方法
は、複数の半導体装置が縦横に並ぶ広さの金属基板シー
トを用意し、これに所定のリードパターンが形成された
回路基板シートを貼着して半導体素子搭載基板を造り、
この上に半導体素子を搭載して、所定のワイヤボンディ
ングを行い、樹脂封止しているので、多数の半導体装置
を一つの基板上に製造できる。そして、半導体素子が搭
載される素子搭載部は、窪み加工が行われて、その周囲
より下部位置に形成されているので、薄い半導体素子は
当然載置できるとして、多少厚みのある半導体素子であ
っても搭載できる。特に、請求項2記載の半導体装置の
製造方法においては、窪み加工がプレス処理によって形
成されているので、短時間に所定の形状の窪み加工が行
え、更にその窪み深さも任意に設定できる。そして、請
求項3記載の半導体装置の製造方法においては、窪み加
工がエッチング処理によって行われているので、その処
理が簡単であり、特別な金型等を必要としないが、金属
基板シートの厚みによってその深さが制限される。請求
項4記載の半導体装置の製造方法においては、回路基板
シートの外部接続端子ランドを除く部分には、ソルダー
レジスト膜が形成されているので、半田ボールの固着が
容易であり、更には、リードパターンの腐食を防止する
と共に、この半導体装置を実装した場合の他回路との不
要な接触を防止できる。
In the method for manufacturing a semiconductor device according to any one of claims 1 to 4, a metal substrate sheet having a plurality of semiconductor devices arranged in a matrix is prepared, and a circuit substrate sheet having a predetermined lead pattern is attached to the metal substrate sheet. To make a semiconductor element mounting board,
Since a semiconductor element is mounted on this, predetermined wire bonding is performed, and resin sealing is performed, a large number of semiconductor devices can be manufactured on one substrate. Since the element mounting portion on which the semiconductor element is mounted is recessed and is formed at a position lower than its periphery, it is natural that a thin semiconductor element can be mounted. Can be installed. In particular, in the method for manufacturing a semiconductor device according to the second aspect, since the depression is formed by pressing, the depression having a predetermined shape can be performed in a short time, and the depth of the depression can be set arbitrarily. Further, in the method for manufacturing a semiconductor device according to claim 3, since the recess processing is performed by an etching process, the process is easy and a special mold or the like is not required, but the thickness of the metal substrate sheet. Limits its depth. In the method for manufacturing a semiconductor device according to claim 4, a solder resist film is formed on a portion of the circuit board sheet excluding the external connection terminal lands, so that the solder balls can be easily fixed, and further, the leads can be used. It is possible to prevent corrosion of the pattern and prevent unnecessary contact with other circuits when the semiconductor device is mounted.

【0007】[0007]

【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図1は本発明の第1の実施
の形態に係る半導体装置の製造方法によって製造された
半導体装置の部分断面図、図2は同平面図、図3は本発
明の第2の実施の形態に係る半導体装置の製造方法によ
って製造された半導体装置の部分断面図である。
BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to the attached drawings, an embodiment in which the present invention is embodied will be described to provide an understanding of the present invention. 1 is a partial sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a plan view of the same, and FIG. 3 is a second embodiment of the present invention. FIG. 6 is a partial cross-sectional view of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the above embodiment.

【0008】まず、第1の実施の形態に係る半導体装置
の製造方法によって製造された半導体装置10の単体に
ついて説明する。図1に示すように、半導体装置10
は、熱伝導性の良好な金属基板の一例である銅基板11
と、この上に接合された絶縁性樹脂基材の一例であるガ
ラスクロスエポキシ樹脂板12aを絶縁材として用いた
回路基板12と、銅基板11の中央に窪み加工を行って
形成された素子搭載部13に搭載される半導体素子14
と、半導体素子14の端子部(電極パッド)と回路基板
12上のリードパターン15の各リード16の内側端部
とをそれぞれ連結するボンディングワイヤ17と、各リ
ード16の外側端部の外部接続端子ランド18にそれぞ
れ固着された半田ボール19と、半導体素子14及びボ
ンディングワイヤ17を被覆するポッティング樹脂20
と、各リードパターン15の表面を覆うソルダーレジス
ト膜21とを有している。
First, a single unit of the semiconductor device 10 manufactured by the method of manufacturing a semiconductor device according to the first embodiment will be described. As shown in FIG. 1, the semiconductor device 10
Is a copper substrate 11 which is an example of a metal substrate having good thermal conductivity.
And a circuit board 12 using as an insulating material a glass cloth epoxy resin plate 12a, which is an example of an insulating resin base material bonded thereon, and an element mounting formed by forming a recess in the center of the copper substrate 11. Semiconductor element 14 mounted on the part 13
A bonding wire 17 for connecting a terminal portion (electrode pad) of the semiconductor element 14 and an inner end portion of each lead 16 of the lead pattern 15 on the circuit board 12, and an external connection terminal at an outer end portion of each lead 16. Solder balls 19 fixed to lands 18 respectively, and potting resin 20 for covering semiconductor element 14 and bonding wires 17
And a solder resist film 21 that covers the surface of each lead pattern 15.

【0009】前記素子搭載部13は、プレス処理によっ
て板厚程度の窪み加工がなされ、搭載する半導体素子1
4の高さが銅基板11の表面から余分に突出しないよう
になっている。前記回路基板12には素子搭載部13に
符合する開口部22が形成されて、半導体素子14が露
出するようになっている。また、前記外部接続端子ラン
ド18は、素子搭載部13の外側に縦横でしかも一定ピ
ッチで形成され、外部接続端子ランド18に接合される
半田ボール19がグリッドアレイ状に配列されるように
なっている。前記ソレダーレジスト膜21は、各外部接
続端子ランドを除く回路基板12の表面を覆うようにな
って、半田ボール19が所定の位置に固着するのを助け
ると共に、表面のリードパターン15の保護を図ってい
る。以下、このような構造となった半導体装置10の製
造方法について説明する。
The element mounting portion 13 is subjected to a pressing process to form a recess having a thickness of about a plate thickness, and the semiconductor element 1 to be mounted is mounted.
The height of 4 does not project excessively from the surface of the copper substrate 11. The circuit board 12 is formed with an opening 22 corresponding to the element mounting portion 13 so that the semiconductor element 14 is exposed. The external connection terminal lands 18 are formed on the outside of the element mounting portion 13 vertically and horizontally and at a constant pitch, and the solder balls 19 joined to the external connection terminal lands 18 are arranged in a grid array. There is. The solder resist film 21 covers the surface of the circuit board 12 excluding the external connection terminal lands to help the solder balls 19 adhere to predetermined positions and protect the lead pattern 15 on the surface. I am trying. Hereinafter, a method of manufacturing the semiconductor device 10 having such a structure will be described.

【0010】図2には、前記半導体装置10が縦横に複
数個(この例では20個)連結された連結半導体装置2
3を示すが、図に示すような、連結半導体装置23と同
一の広さを有する金属基板シートの一例である厚みが
0.25〜0.55mmの銅基板シートを用意し、この
上に、各半導体装置10の半導体素子14が搭載される
部分に窪み加工の一例であるプレス処理を行って、表面
より少し下部位置に複数の素子搭載部13を所定ピッチ
で形成する。この後、前記銅基板シートに所定のめっき
(例えば、Niめっき)を行って、下地めっき層24を
形成する。なお、更に、耐食性を向上するため、あるい
は鑞付け性を向上するために、下地めっき層24の上
に、更に金、銀、パラジウム等のめっきをすることは自
由である(以上、第1工程)。
In FIG. 2, a plurality of semiconductor devices 10 are connected vertically and horizontally (20 in this example) to form a connected semiconductor device 2.
3, a copper substrate sheet having a thickness of 0.25 to 0.55 mm, which is an example of a metal substrate sheet having the same width as the connected semiconductor device 23, is prepared as shown in FIG. A portion of each semiconductor device 10 on which the semiconductor element 14 is mounted is subjected to a pressing process, which is an example of dent processing, to form a plurality of element mounting portions 13 at a predetermined pitch slightly below the surface. Then, the copper substrate sheet is subjected to predetermined plating (for example, Ni plating) to form the base plating layer 24. Further, in order to further improve the corrosion resistance or the brazing property, it is free to further plate gold, silver, palladium or the like on the base plating layer 24 (the above is the first step). ).

【0011】前記銅基板シートと同一広さの電気的絶縁
性部材の一例であるガラスクロスエポキシ樹脂基材シー
ト(板厚0.3〜0.5mm、FR−4又はFR−5)
を用意し、その片面に厚みが32μm程度の銅箔層を設
けると共に、他面に、熱硬化性接着剤の一例であって、
厚みが50〜100μm程度のプリプレグ層25を設け
ておく。このような構成となった基板シートを、まずプ
レス処理によって前記銅基板シートに形成された各素子
搭載部13に符合する複数の開口部22を形成する。そ
して、表面の銅箔層を周知の方法によってエッチング加
工して、各開口部22の周囲にリードパターン15を形
成して、回路基板シートを製造する(以上、第2工
程)。
A glass cloth epoxy resin base sheet (plate thickness 0.3 to 0.5 mm, FR-4 or FR-5) which is an example of an electrically insulating member having the same size as the copper substrate sheet.
And a copper foil layer having a thickness of about 32 μm is provided on one side thereof, and the other side is an example of a thermosetting adhesive,
A prepreg layer 25 having a thickness of about 50 to 100 μm is provided in advance. The substrate sheet having such a structure is first subjected to a press process to form a plurality of openings 22 corresponding to the respective element mounting portions 13 formed on the copper substrate sheet. Then, the copper foil layer on the surface is etched by a known method to form the lead pattern 15 around each opening 22 to manufacture a circuit board sheet (above, the second step).

【0012】この回路基板シートを前記銅基板シートに
プリプレグ層を介して熱圧着するが、この場合、銅基板
シートの各素子搭載部13と、回路基板シートの各開口
部22との位置を符合させた状態で接合する。この後、
慣用のスクリーン印刷法によって外部接続端子ランド1
8を露出させた状態で、ソルダーレジスト膜21を形成
する。これによって、半導体素子搭載基板シートが完成
する(以上、第3工程)。次に、この半導体素子搭載基
板シートを図示しない搬送プレート上に位置決め載置し
て、該搬送プレートをX方向及びY方向に所定距離だけ
移動して、載置した半導体素子搭載基板シートを所定の
位置に移動させた状態で、各素子搭載部13に所定の半
導体素子14を順次搭載し、所定のワイヤボンディング
を行う。ここで、素子搭載部13は窪み加工が成されて
いるので、各半導体素子14の端子パッド26の位置が
下がり、各端子パッド26と、リード16の内側端部と
を連結するボンディングワイヤが回路基板シートの表面
から突出しないことになる(以上、第4工程)。
This circuit board sheet is thermocompression-bonded to the copper board sheet via a prepreg layer. In this case, the positions of the element mounting portions 13 of the copper board sheet and the openings 22 of the circuit board sheet are aligned with each other. Join in the state of being made. After this,
External connection terminal land 1 by conventional screen printing method
The solder resist film 21 is formed with 8 exposed. As a result, the semiconductor element mounting substrate sheet is completed (the above is the third step). Next, this semiconductor element mounting substrate sheet is positioned and mounted on a carrier plate (not shown), and the carrier plate is moved in the X direction and the Y direction by a predetermined distance, and the mounted semiconductor element mounting substrate sheet is moved to a predetermined position. In the state where it is moved to the position, a predetermined semiconductor element 14 is sequentially mounted on each element mounting portion 13 and predetermined wire bonding is performed. Here, since the element mounting portion 13 is dented, the position of the terminal pad 26 of each semiconductor element 14 is lowered, and a bonding wire connecting each terminal pad 26 and the inner end portion of the lead 16 is formed into a circuit. It will not protrude from the surface of the substrate sheet (the above is the fourth step).

【0013】以上の工程を経た後、各素子搭載部13に
所定量のポッティング樹脂20を流し込んで、半導体素
子14とボンデイングワイヤ17及びこれらの接合部分
の樹脂シールを行う(以上、第5工程)。次に、各リー
ドの外側端部である外部接続端子ランド18に半田ボー
ル19を固着して、連結半導体装置23が完成する(以
上、第6工程)。使用にあっては、図2に示す縦横の切
り取り線27の部分でジグ・フライスやその他のカッタ
ー等によって切断分離して、単独の半導体装置10が製
造される(以上、第7工程)。なお、銅基板11は半導
体素子14の放熱の促進を図ると共に、半導体素子14
を電気的にシールし、外部からの雑音を遮断する働きが
ある。
After passing through the above steps, a predetermined amount of potting resin 20 is poured into each element mounting portion 13 to seal the semiconductor element 14, the bonding wire 17 and their joints with resin (the above fifth step). . Next, the solder balls 19 are fixed to the external connection terminal lands 18, which are the outer ends of the leads, to complete the coupled semiconductor device 23 (the sixth step). In use, a single semiconductor device 10 is manufactured by cutting and separating the vertical and horizontal cutoff lines 27 shown in FIG. 2 with a jig / milling machine or other cutters (the seventh step). The copper substrate 11 promotes heat dissipation of the semiconductor element 14, and at the same time, the semiconductor element 14
It has a function of electrically sealing and blocking external noise.

【0014】続いて、図3に示す本発明の第2の実施の
形態に係る半導体装置の製造方法によって製造された半
導体装置30について説明するが、前記第1の実施の形
態に係る半導体装置の製造方法によって製造された半導
体装置10と同一の構成要素については、同一の番号を
付してその詳しい説明を省略する。半導体装置30に使
用する金属基板の一例である銅基板31はやや厚めの銅
基板31が使用され、その中央に形成される素子搭載部
32は、周知のエッチング処理によって板厚の1/3〜
2/3程度の窪み加工が行われている。これによって、
搭載する半導体素子14の位置を下げることができ、全
体としてより薄い半導体装置30を提供できる。
Next, the semiconductor device 30 manufactured by the method for manufacturing a semiconductor device according to the second embodiment of the present invention shown in FIG. 3 will be described. The semiconductor device according to the first embodiment will be explained. The same components as those of the semiconductor device 10 manufactured by the manufacturing method are designated by the same reference numerals, and detailed description thereof will be omitted. A slightly thick copper substrate 31 is used as a copper substrate 31 which is an example of a metal substrate used for the semiconductor device 30, and an element mounting portion 32 formed in the center thereof has a thickness of 1/3 to 1/3 of a plate thickness by a well-known etching process.
About 2/3 of the recess is processed. by this,
The position of the mounted semiconductor element 14 can be lowered, and a thinner semiconductor device 30 can be provided as a whole.

【0015】その製造方法においては、第1の実施の形
態に係る半導体装置の製造方法におけるプレス処理によ
って窪み加工を行う代わりにエッチング処理によって、
素子搭載部32を形成しており、その他の点については
同一である。この半導体装置30においては、比較的厚
い銅基板を使用するので、更に放熱性が向上すること、
半導体装置30の片側が平面状となるので、厚み方向に
嵩張らず、より薄い装置(例えば、ICカード)を提供
できる利点がある。
In the manufacturing method, an etching process is used instead of the depression process by the press process in the semiconductor device manufacturing method according to the first embodiment.
The element mounting portion 32 is formed, and the other points are the same. In this semiconductor device 30, since a relatively thick copper substrate is used, heat dissipation is further improved.
Since one side of the semiconductor device 30 is flat, there is an advantage that a thinner device (for example, an IC card) can be provided without being bulky in the thickness direction.

【0016】前記実施の形態においては、金属基板の材
質及び厚みを特定して説明したが、これより薄い場合で
あっても、厚い場合であっても本発明は適用される。ま
た、連結半導体装置は、半導体装置の個数を特定して説
明したが、本発明はその数には限定されない。更には、
前記実施の形態においては、それぞれ外部接続端子ラン
ドに半田ボールを固着していたが、この部分にバンプを
形成することも可能である。そして、前記実施の形態に
おいては、各半導体装置をポッティング樹脂モールドを
行って製造しているが、インジェクション樹脂モールド
を行って各半導体装置を製造してもよい。
In the above-mentioned embodiment, the material and thickness of the metal substrate are specified and explained, but the present invention is applicable regardless of whether it is thinner or thicker. Moreover, although the number of semiconductor devices is specified and described for the coupled semiconductor device, the present invention is not limited to that number. Furthermore,
Although the solder balls are fixed to the external connection terminal lands in each of the above-described embodiments, bumps can be formed on these portions. In addition, in the above-described embodiment, each semiconductor device is manufactured by potting resin molding, but each semiconductor device may be manufactured by injection resin molding.

【0017】[0017]

【発明の効果】請求項1〜4記載の半導体装置の製造方
法は、複数の半導体装置を連結状態で同時に製造するの
で、効率が良く安価な大量生産が可能である。そして、
金属基板に窪み部を設けて半導体素子を搭載しているの
で、より薄いBGA型の半導体装置を提供できる。特
に、請求項2記載の半導体装置の製造方法においては、
窪み加工がプレス処理によって形成されているので、短
時間で正確な一括加工が行える。そして、請求項3記載
の半導体装置の製造方法においては、窪み加工がエッチ
ング処理によって行われているので、その処理が簡単で
あり、特別な金型等を必要としない。そして、金属基板
の側面を平面状に保持できるので、より薄い半導体装置
を提供できる。更には、金属基板シート内に滞有する内
部残留応力が少なくなり、金属基板シートの変形の発生
を防ぐことができ、平坦度が著しく向上する。その結果
として、半田ボール又はバンプのコプラナリティの向上
が可能となる。請求項4記載の半導体装置の製造方法に
おいては、回路基板シートの外部接続端子ランドを除く
部分には、ソルダーレジスト膜が形成されているので、
半田ボールの固着が容易となると共に、リードパターン
の保護が図れる。
In the method for manufacturing a semiconductor device according to the first to fourth aspects of the present invention, since a plurality of semiconductor devices are manufactured simultaneously in a connected state, efficient mass production at low cost is possible. And
Since the semiconductor element is mounted by providing the recessed portion on the metal substrate, a thinner BGA type semiconductor device can be provided. Particularly, in the method of manufacturing a semiconductor device according to claim 2,
Since the recess processing is formed by the press processing, accurate batch processing can be performed in a short time. Further, in the method for manufacturing a semiconductor device according to the third aspect, since the recessing process is performed by the etching process, the process is simple and no special mold or the like is required. Since the side surface of the metal substrate can be held flat, a thinner semiconductor device can be provided. Furthermore, the internal residual stress retained in the metal substrate sheet is reduced, the deformation of the metal substrate sheet can be prevented, and the flatness is remarkably improved. As a result, the coplanarity of the solder balls or bumps can be improved. In the method for manufacturing a semiconductor device according to claim 4, since the solder resist film is formed on a portion of the circuit board sheet excluding the external connection terminal lands,
The solder balls can be easily fixed and the lead pattern can be protected.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態に係る半導体装置の
製造方法によって製造された半導体装置の部分断面図で
ある。
FIG. 1 is a partial cross-sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】同半導体装置を縦横に接続した連結半導体装置
の平面図である。
FIG. 2 is a plan view of a coupled semiconductor device in which the same semiconductor device is vertically and horizontally connected.

【図3】本発明の第2の実施の形態に係る半導体装置の
製造方法によって製造された半導体装置の部分断面図で
ある。
FIG. 3 is a partial cross-sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

【図4】従来例に係る半導体装置の製造方法を示す説明
図である。
FIG. 4 is an explanatory diagram showing a method of manufacturing a semiconductor device according to a conventional example.

【図5】従来例に係る半導体装置の製造方法を示す説明
図である。
FIG. 5 is an explanatory diagram showing a method of manufacturing a semiconductor device according to a conventional example.

【符号の説明】[Explanation of symbols]

10 半導体装置 11 銅基板
(金属基板) 12 回路基板 12a ガラスクロスエポキシ樹脂板 13 素子搭載
部 14 半導体素子 15 リードパ
ターン 16 リード 17 ボンディ
ングワイヤ 18 外部接続端子ランド 19 半田ボー
ル 20 ポッティング樹脂 21 ソルダー
レジスト膜 22 開口部 23 連結半導
体装置 24 下地めっき層 25 プリプレ
グ層 26 端子パッド 27 切り取り
線 30 半導体装置 31 銅基板
(金属基板) 32 素子搭載部
10 semiconductor device 11 copper substrate (metal substrate) 12 circuit board 12a glass cloth epoxy resin plate 13 element mounting portion 14 semiconductor element 15 lead pattern 16 lead 17 bonding wire 18 external connection terminal land 19 solder ball 20 potting resin 21 solder resist film 22 Opening 23 Connected semiconductor device 24 Base plating layer 25 Prepreg layer 26 Terminal pad 27 Cutting line 30 Semiconductor device 31 Copper substrate (metal substrate) 32 Element mounting part

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 H01L 23/36 H01L 23/04 H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 23/36 H01L 23/04 H01L 21/60

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 中央に半導体素子が搭載され、その周囲
には該半導体素子の複数の電極パッドにボンディングワ
イヤを介して連結された複数のリードからなるリードパ
ターンを有し、しかもそれぞれの前記リードにはグリッ
ドアレイ状に配置されて接続端子となる複数の半田ボー
ル又はバンプが設けられた半導体装置の製造方法であっ
て、 所要数の前記半導体装置が縦横に並置可能な広さを有す
ると共に熱伝導性の良好な金属基板シートを用意し、そ
れぞれの半導体装置の素子搭載部の窪み加工を行って、
その周囲より下部位置に形成すると共に、その表面に所
定の下地めっきを行う第1工程と、 前記金属基板シート上に形成される複数の半導体装置の
素子搭載部に符合する開口部が形成され、しかも該開口
部の周囲には、該開口部に配置される半導体素子に連結
されるリードパターンがエッチング加工によって形成さ
れた回路基板シートを用意する第2工程と、 前記第1工程で製造された金属基板シートに、前記第2
工程で用意された回路基板シートをそれぞれの前記素子
搭載部に開口部を一致させて接合して半導体素子搭載基
板シートを造る第3工程と、 前記半導体素子搭載基板シートを搬送プレート上に位置
決め載置し、前記半導体素子搭載基板シートをX方向及
びY方向に所定距離だけ移送して、それぞれの素子搭載
部に半導体素子を搭載し、所定のワイヤボンディングを
行ってそれぞれの半導体素子の端子パッドと前記リード
パターンとを連結する第4工程と、 それぞれの前記半導体素子及びワイヤボンディングされ
た部分を、ポッティングモールド又はインジェンクショ
ンモールドにより樹脂封止する第5工程と、 前記リードパターンの各外部接続端子ランドに前記半田
ボール又はバンプを形成する第6工程と、 以上の工程によって、半導体装置が縦横に並置された連
結半導体装置から単一の半導体装置を切断分離する第7
工程とを有することを特徴とする半導体装置の製造方
法。
1. A semiconductor element is mounted in the center, and a lead pattern composed of a plurality of leads connected to a plurality of electrode pads of the semiconductor element via bonding wires is provided around the semiconductor element, and each of the leads is provided. Is a method for manufacturing a semiconductor device in which a plurality of solder balls or bumps, which are arranged in a grid array and serve as connection terminals, are provided. Prepare a metal substrate sheet with good conductivity, process the recess of the element mounting part of each semiconductor device,
A first step of forming a predetermined undercoat on the surface of the metal substrate sheet, and forming an opening corresponding to the element mounting portion of the plurality of semiconductor devices formed on the metal substrate sheet, Moreover, the second step of preparing a circuit board sheet around the opening is provided with the lead pattern connected to the semiconductor element arranged in the opening by the etching process, and the first step. On the metal substrate sheet, the second
A third step of manufacturing the circuit board sheet prepared in the step by bonding the circuit board sheets to the element mounting portions with their openings aligned with each other, and positioning the semiconductor element mounting substrate sheet on the transport plate. Then, the semiconductor element mounting substrate sheet is moved by a predetermined distance in the X and Y directions, the semiconductor element is mounted on each element mounting portion, and predetermined wire bonding is performed to form a terminal pad of each semiconductor element. A fourth step of connecting the lead pattern, a fifth step of resin-sealing the semiconductor element and the wire-bonded portion with a potting mold or an injection mold, and external connection terminal lands of the lead pattern. The sixth step of forming the solder balls or bumps on the A single semiconductor device is cut and separated from a connected semiconductor device in which devices are arranged side by side in a longitudinal direction.
A method of manufacturing a semiconductor device, comprising:
【請求項2】 第1工程における前記窪み加工は、プレ
ス処理によって行う請求項1記載の半導体装置の製造方
法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the recessing process in the first step is performed by a press process.
【請求項3】 第1工程における前記窪み加工は、エッ
チング処理によって行う請求項1記載の半導体装置の製
造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the recessing process in the first step is performed by an etching process.
【請求項4】 第2工程において、前記回路基板シート
の前記外部接続端子ランドを除く部分には、ソルダーレ
ジスト膜が形成されている請求項1〜3のいずれか1項
に記載の半導体装置の製造方法。
4. The semiconductor device according to claim 1, wherein, in the second step, a solder resist film is formed on a portion of the circuit board sheet excluding the external connection terminal lands. Production method.
JP01471797A 1997-01-10 1997-01-10 Method for manufacturing semiconductor device Expired - Fee Related JP3398556B2 (en)

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Application Number Priority Date Filing Date Title
JP01471797A JP3398556B2 (en) 1997-01-10 1997-01-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH10199899A JPH10199899A (en) 1998-07-31
JP3398556B2 true JP3398556B2 (en) 2003-04-21

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ID=11868903

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JP (1) JP3398556B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319624B1 (en) * 1999-05-20 2002-01-09 김영환 Semiconductor chip package and method for fabricating thereof
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