JP4100685B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4100685B2
JP4100685B2 JP2003296727A JP2003296727A JP4100685B2 JP 4100685 B2 JP4100685 B2 JP 4100685B2 JP 2003296727 A JP2003296727 A JP 2003296727A JP 2003296727 A JP2003296727 A JP 2003296727A JP 4100685 B2 JP4100685 B2 JP 4100685B2
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lead frame
circuit pattern
copper circuit
solder
protrusion
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JP2005072098A (en
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克彦 吉原
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、パワー半導体モジュールなどを対象とした半導体装置に関し、詳しくは半導体回路基板である絶縁基板の銅回路パターン, あるいは絶縁基板にマウントした半導体チップにリードフレームを半田接合する接続構造に係わる。   The present invention relates to a semiconductor device intended for a power semiconductor module or the like, and more particularly to a copper circuit pattern of an insulating substrate which is a semiconductor circuit substrate or a connection structure in which a lead frame is soldered to a semiconductor chip mounted on the insulating substrate.

昨今では、パワー半導体モジュールの電流容量が増大化する一方で小形, 高密度化が進み、これに対応してパッケージ内部の配線についても、通電容量，放熱性の向上および配線インダクタンスの低減化を図るために、従来のボンディングワイヤ（アルミワイヤ）に代えてリードフレーム（銅板）が多く採用されるようになっている。
ところで、ボンディングワイヤをリードフレームに代えて絶縁基板（セラミック板の表裏両面に銅回路パターンを直接接合したDirect Bonding Copper 基板）の銅回路パターン，あるいは該絶縁基板にマウントした半導体チップに半田接合する場合に、その半田層の厚みにバラツキがあると次記のような不具合が生じる。すなわち、半田層が所定の厚みより厚いと半田付けの際に溶融半田が接合面域から周囲に流れ出して他の回路パターンと電気的に短絡することがある。また、逆に半田層の厚みが薄いと、使用環境でのヒートサイクルにより、絶縁基板とリードフレームとの熱膨張差に起因して半田接合部に発生した熱応力で早期に疲労破壊に至るといった問題がある。 In recent years, the current capacity of power semiconductor modules has increased, while miniaturization and high density have progressed. Correspondingly, with regard to the wiring inside the package, the current carrying capacity and heat dissipation are improved and the wiring inductance is reduced. For this reason, a lead frame (copper plate) is often used instead of the conventional bonding wire (aluminum wire).
By the way, when bonding wires are soldered to a copper circuit pattern of an insulating substrate (Direct Bonding Copper substrate in which copper circuit patterns are directly bonded to both front and back surfaces of a ceramic plate) or a semiconductor chip mounted on the insulating substrate instead of a lead frame In addition, if the thickness of the solder layer varies, the following problems occur. That is, when the solder layer is thicker than a predetermined thickness, the molten solder may flow out from the joint surface area to the periphery during soldering, and may be electrically short-circuited with other circuit patterns. Conversely, if the thickness of the solder layer is thin, it will cause fatigue failure early due to thermal stress generated in the solder joint due to the thermal expansion difference between the insulating substrate and the lead frame due to the heat cycle in the usage environment. There's a problem.

そこで、リードフレームを用いて前記のように半導体装置の電流経路に半田接合する際に、その半田層に所定の厚みを確保するために、リードフレーム，もしくは絶縁基板の銅回路パターンの半田接合面に所定の半田層厚に相応する高さに設定した突起を例えば切削，切り起こし加工などにより形成しておき、半田付けの際に前記突起を相手側部材の半田接合面に突き合わせて半田層を所定厚みに制御するようにした接続構造が知られている（例えば、特許文献１，特許文献２参照）。
特開２００３−７８０９３号公報 特開昭５４−１９６５８号公報 Therefore, when soldering to the current path of the semiconductor device using the lead frame as described above, in order to ensure a predetermined thickness in the solder layer, the solder joint surface of the copper circuit pattern of the lead frame or the insulating substrate Protrusions set to a height corresponding to a predetermined solder layer thickness are formed by, for example, cutting, cutting and raising processes, and the solder layer is abutted against the solder joint surface of the mating member during soldering. A connection structure that is controlled to have a predetermined thickness is known (see, for example, Patent Document 1 and Patent Document 2).
JP 2003-78093 A Japanese Patent Laid-Open No. 54-19658

前記のようにリードフレーム，基板の半田接合面にあらかじめ突起を形成しておき、この突起を相手側部材の半田接合面に突き合わせて半田接合するようにした半導体装置では、高い生産性の確保と製造コストの上昇を低く抑える上から、前記突起をできるだけ簡易な方法で形成することが望まれる。
ところで、前記した半導体装置における接合半田層の厚さが例えば１００μｍ以上であれば、その半田接合面に形成する突起の高さも１００μｍ以上となるので、機械的な切削加工，切り起こし加工により突起を形成することも可能であるが、半田層の厚さがそれ以下にある半導体装置に適用する場合には突起の高さが短小で、かつ要求される加工精度も高くなることから、機械加工法での突起の形成が困難となる。
本発明は上記の点に鑑みなされたものであり、先記のようにリードフレームまたは絶縁基板の銅回路パターンの半田接合面に突起を形成して半田層の厚みのバラツキを防ぐようにした接続構造において、前記突起を簡易な製法で形成できるように改良した半導体装置の接続構造を提供することを目的とする。 As described above, in the semiconductor device in which the protrusion is formed in advance on the solder joint surface of the lead frame and the substrate and this protrusion is abutted against the solder joint surface of the counterpart member and soldered, high productivity is ensured. In order to suppress an increase in manufacturing cost to a low level, it is desirable to form the protrusions by the simplest possible method.
By the way, if the thickness of the bonding solder layer in the semiconductor device described above is, for example, 100 μm or more, the height of the protrusion formed on the solder bonding surface is also 100 μm or more. Therefore, the protrusion is formed by mechanical cutting or cutting and raising. However, when applied to a semiconductor device in which the thickness of the solder layer is less than that, since the height of the protrusion is short and the required processing accuracy is high, the machining method It becomes difficult to form protrusions on the surface.
The present invention has been made in view of the above points, and as described above, a connection formed such that protrusions are formed on the solder joint surface of the copper circuit pattern of the lead frame or the insulating substrate to prevent variations in the thickness of the solder layer. An object of the present invention is to provide a connection structure for a semiconductor device which is improved so that the protrusion can be formed by a simple manufacturing method.

上記目的を達成するために、本発明によれば、絶縁基板の銅回路パターンもしくは銅回路パターン上にマウントした半導体チップにリードフレームを半田接合した接続構造を有する半導体装置において、
前記リードフレーム, 銅回路パターンのいずれか一方の半田接合面に半田層の厚さに相応した凸状の突起を形成するものとし、この突起を次に記す手法により形成する。
(1) 半田接合面に導電性接着剤を塗布して突起を形成する（請求項１）。 To achieve the above object, according to the present invention, in a semiconductor device having a connection structure in which a lead frame is soldered to a copper circuit pattern of an insulating substrate or a semiconductor chip mounted on the copper circuit pattern,
A convex protrusion corresponding to the thickness of the solder layer is formed on the solder joint surface of either the lead frame or the copper circuit pattern, and this protrusion is formed by the following method.
(1) A conductive adhesive is applied to the solder joint surface to form protrusions (claim 1).

上記した手法は切削，切り起こし加工などの機械加工法と比べ、簡単，かつ短時間作業でリードフレームあるいは絶縁基板の銅回路パターンの半田接合面に所定厚さの半田層に対応した突起を形成することができる。
Compared with machining methods such as cutting and raising, the above-mentioned method forms projections corresponding to a solder layer of a predetermined thickness on the solder joint surface of a copper circuit pattern on a lead frame or insulating substrate in a simple and short operation. it can be.

本発明によれば、半導体装置の内部配線の接続構造として、リードフレームあるいは絶縁基板の銅回路パターンの半田接合面に前記した手法により突起を形成したことにより、接合半田層の厚みのバラツキを抑えて配線構造の信頼性を高めるとともに、機械加工による従来の突起形成法と比べて製造コストの低減化，および生産性向上が図れる。   According to the present invention, as the internal wiring connection structure of the semiconductor device, the protrusions are formed on the solder joint surface of the copper circuit pattern of the lead frame or the insulating substrate by the above-described method, thereby suppressing variations in the thickness of the joint solder layer. As a result, the reliability of the wiring structure can be improved, and the manufacturing cost can be reduced and the productivity can be improved as compared with the conventional protrusion forming method by machining.

以下、本発明の実施の形態を以下述べる各実施例に基づいて説明する。なお、実施例の図中で、１は絶縁基板（Direct Bonding Copper 基板）２は、絶縁基板１のセラミック板に形成した銅回路パターン、３は左右に並ぶ銅回路パターン２の間を接続するリードフレーム、４は一方の銅回路パターン２に半田マウントした半導体チップ、５はリードフレーム３と銅回路パターン２の間，リードフレーム３と半導体チップ４との間を接合した半田層、６は半導体チップ４を絶縁基板１の銅回路パターン２に接合した半田層、７はリードフレーム３の半田接合面に形成した突起、８はリードフレーム３に対峙して銅回路パターン２の半田接合面に形成した突起である。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on each example described below. In the drawings of the embodiments, 1 is an insulating substrate (Direct Bonding Copper substrate) 2 is a copper circuit pattern formed on a ceramic plate of the insulating substrate 1, and 3 is a lead connecting between the copper circuit patterns 2 arranged side by side. Frame 4 is a semiconductor chip solder-mounted on one copper circuit pattern 2, 5 is a solder layer joining the lead frame 3 and the copper circuit pattern 2, a lead frame 3 and the semiconductor chip 4, and 6 is a semiconductor chip 4 is a solder layer bonded to the copper circuit pattern 2 of the insulating substrate 1, 7 is a protrusion formed on the solder bonding surface of the lead frame 3, and 8 is formed on the solder bonding surface of the copper circuit pattern 2 facing the lead frame 3. It is a protrusion.

図１(a) 〜(e) は絶縁基板１の上面に形成した左右の銅回路パターン２の間に跨がってリードフレーム３を半田接合したものであり、ここでリードフレーム３の両端の半田接合面（平坦な電極面）には(b) 〜(e) 図のように半田層５の厚さに対応した突起高さに定めた１ないし複数個の凸状突起７を分散形成しておき、この突起７を銅回路パターン２の半田接合面に当ててリードフレーム３を配置した状態で、リードフレーム３と銅回路パターン２の間を半田接合する。なお、図示例の突起７の形状は角柱であるが、角柱以外にも円柱，三角柱，三角錐，球形などの形状にしてもよい。また、突起７の個数は銅回路パターン２の上にリードフレーム３を載せた状態での姿勢を安定化させるために、３個以上分散して形成するのが好ましい。
ここで、前記の凸状突起７は、できるだけコストをかけずに簡易な方法で形成するために、次記のような手法で形成するものとする。 FIGS. 1A to 1E show the lead frame 3 soldered between the left and right copper circuit patterns 2 formed on the upper surface of the insulating substrate 1. On the solder joint surface (flat electrode surface), as shown in (b) to (e), one or a plurality of convex projections 7 having a projection height corresponding to the thickness of the solder layer 5 are dispersedly formed as shown in the figure. In addition, the lead frame 3 and the copper circuit pattern 2 are soldered together in a state where the lead frame 3 is disposed with the protrusions 7 being in contact with the solder joint surface of the copper circuit pattern 2. In addition, although the shape of the protrusion 7 in the illustrated example is a prism, it may be a cylinder, a triangular prism, a triangular pyramid, a sphere, or the like other than the prism. Further, it is preferable that three or more protrusions 7 are formed in a dispersed manner in order to stabilize the posture when the lead frame 3 is placed on the copper circuit pattern 2.
Here, the convex protrusion 7 is formed by the following method in order to form it by a simple method without incurring costs as much as possible.

(1) 半導体装置のワイヤボンディング法として知られている超音波接合法によりアルミ材あるいは銅材をリードフレーム３の電極面に接合して突起７を形成する。
(2) リードフレーム３の電極面にレジストを塗布し、エッチング液に浸して所望高さの突起７を形成する。
(3) 突起の材料に導電性接着剤を用い、ディスペンサを使ってリードフレーム３の電極面上に所定箇所に所望の高さとなるように導電性接着剤を点状に塗布した上で、これを硬化させて突起７を形成する。
(4) 前記導電性接着剤の代わりに、ウレタン系，アクリル系，エポキシ系，ポリイミド系などの耐熱性樹脂を用い、これをリードフレーム３の電極面に点状に塗布した上で、硬化処理して所望高さの突起７を形成する。なお、この場合に樹脂材に光硬化形樹脂を用いることにより、加熱処理を行わずに紫外線照射で硬化させることができる。 (1) The protrusion 7 is formed by bonding an aluminum material or a copper material to the electrode surface of the lead frame 3 by an ultrasonic bonding method known as a wire bonding method of a semiconductor device.
(2) A resist is applied to the electrode surface of the lead frame 3 and dipped in an etching solution to form a projection 7 having a desired height.
(3) A conductive adhesive is used as the material of the protrusion, and a conductive adhesive is applied in a dot shape on the electrode surface of the lead frame 3 at a predetermined position using a dispenser. Is cured to form the protrusion 7.
(4) Instead of the conductive adhesive, use a heat-resistant resin such as urethane, acrylic, epoxy, polyimide, etc., and apply it to the electrode surface of the lead frame 3 in a dot shape, followed by a curing treatment. Thus, the projection 7 having a desired height is formed. In this case, by using a photocurable resin as the resin material, the resin material can be cured by irradiation with ultraviolet rays without performing heat treatment.

(5) 突起の材料に所定厚さの耐熱性粘着テープを用い、この粘着テープにあらかじめ突起となる部分を切り込み形成した上でリードフレーム３の電極面に貼り付けた後、突起部分を電極面上に残してテープを剥がして突起７を形成する。なお、使用する粘着テープは、半田接合の際の半田溶融温度（Sb-Pb 系:183℃,Sn-Ag系:221℃) に耐える耐熱性のポリテトラフロロエチレンテープ，含浸ガラスクロステープ，シリコーンテープなど（耐熱温度：約 250℃) を用いるのがよい。また、高融点半田 (Pb-Sn 系,Pb-Sn-Ag 系：融点約 300℃) を使用する場合には、アルミ箔テープ，銅箔テープ (耐熱温度：約 320℃) を用いるのがよい。   (5) Use a heat-resistant adhesive tape with a predetermined thickness as the material for the protrusions. Cut the protrusions into the adhesive tape in advance and attach them to the electrode surface of the lead frame 3; The protrusion 7 is formed by peeling the tape while leaving it on. The adhesive tape used is heat-resistant polytetrafluoroethylene tape, impregnated glass cloth tape, silicone that can withstand the solder melting temperature during soldering (Sb-Pb system: 183 ° C, Sn-Ag system: 221 ° C) Use tape or the like (heat-resistant temperature: about 250 ° C). Also, when using high melting point solder (Pb-Sn, Pb-Sn-Ag, melting point: about 300 ° C), it is recommended to use aluminum foil tape or copper foil tape (heat resistance temperature: about 320 ° C). .

図２は絶縁基板１に形成した片方の銅回路パターン２に半田マウントした半導体チップ４の上面電極と他方の銅回路パターン２の間に跨がってリードフレーム３を半田接合した実施例であり、リードフレーム３の両端電極面には先記実施例１と同様な手法で突起７を形成しておき、半導体装置の組立工程では前記突起７を図示のように銅回路パターン２，半導体チップ４の上面の半田接合面に当ててリードフレーム３を載置し、この状態で半田接合を行って所定の厚さの半田層９を得るようにしている。   FIG. 2 shows an embodiment in which the lead frame 3 is soldered between the upper electrode of the semiconductor chip 4 solder-mounted on one copper circuit pattern 2 formed on the insulating substrate 1 and the other copper circuit pattern 2. Protrusions 7 are formed on both end electrode surfaces of the lead frame 3 by the same method as in the first embodiment. In the assembling process of the semiconductor device, the protrusions 7 are formed as shown in FIG. The lead frame 3 is placed against the solder joint surface on the upper surface of the substrate, and solder joining is performed in this state to obtain a solder layer 9 having a predetermined thickness.

図３は図１の接続構造に対応する応用実施例を示すものである。すなわち、先記実施例１では、リードフレーム３の電極面に突起７を形成して絶縁基板１の銅回路パターン２に半田接合するようにしているが、この実施例３では、銅回路パターン２の表面におけるリードフレーム３との半田接合面域に実施例１で述べたと同様な手法で突起８を形成しておき、組立工程では前記突起８の上にリードフレーム３の電極面を当てがい、この状態で銅回路パターン２とリードフレーム３との間を半田接合して所定厚さの半田層５を形成するようにしている。   FIG. 3 shows an application embodiment corresponding to the connection structure of FIG. That is, in the first embodiment, the protrusion 7 is formed on the electrode surface of the lead frame 3 and soldered to the copper circuit pattern 2 of the insulating substrate 1. In this embodiment 3, the copper circuit pattern 2 is formed. Protrusions 8 are formed in the solder joint surface area with the lead frame 3 on the surface in the same manner as described in Example 1, and the electrode surface of the lead frame 3 is applied on the protrusions 8 in the assembly process. In this state, the copper circuit pattern 2 and the lead frame 3 are soldered to form a solder layer 5 having a predetermined thickness.

さらに、図４は図２の接続構造に対応する応用実施例を示すものであり、この実施例においては、図示のようにリードフレーム３と半田接合する左側の銅回路パターン２には実施例３（図３参照）で述べたと同様な突起８を形成し、半導体チップ４の上面電極に半田接合するリードフレーム３の右側電極面には実施例１（図１参照）で述べたと同様な突起７を形成しておく。そして、半導体装置の組立工程では、リードフレーム３の左側端の電極面を絶縁基板１の銅回路パターン２に形成した突起８の上に載せ、半導体チップ４の上面電極にはリードフレーム３の右側端の電極面に形成した突起７を当て、この状態で半田接合を行って所定厚さの半田層５を得るようにしている。   4 shows an application embodiment corresponding to the connection structure of FIG. 2. In this embodiment, the left copper circuit pattern 2 soldered to the lead frame 3 as shown in FIG. A protrusion 8 similar to that described in FIG. 3 is formed, and a protrusion 7 similar to that described in the first embodiment (refer to FIG. 1) is formed on the right electrode surface of the lead frame 3 that is soldered to the upper surface electrode of the semiconductor chip 4. Is formed. In the assembly process of the semiconductor device, the electrode surface at the left end of the lead frame 3 is placed on the protrusion 8 formed on the copper circuit pattern 2 of the insulating substrate 1, and the upper surface electrode of the semiconductor chip 4 is placed on the right side of the lead frame 3. A protrusion 7 formed on the electrode surface at the end is applied, and solder bonding is performed in this state to obtain a solder layer 5 having a predetermined thickness.

本発明の実施例１に係る半導体装置の構成図で、(a) は組立構造の側面図，(b) 〜(e) はリードフレームの電極面に形成した突起の配置を表す図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device based on Example 1 of this invention, (a) is a side view of an assembly structure, (b)-(e) represents arrangement | positioning of the processus | protrusion formed in the electrode surface of a lead frame. 本発明の実施例２に係る半導体装置の組立構成図Assembly diagram of semiconductor device according to embodiment 2 of the present invention 本発明の実施例３に係る半導体装置の組立構成図Assembly diagram of semiconductor device according to embodiment 3 of the present invention 本発明の実施例４に係る半導体装置の組立構成図Assembly diagram of semiconductor device according to embodiment 4 of the present invention

符号の説明Explanation of symbols

１ 絶縁基板
２ 銅回路パターン
３ リードフレーム
４ 半導体チップ
５ 半田層
７，８ 突起 1 Insulating substrate 2 Copper circuit pattern 3 Lead frame 4 Semiconductor chip 5 Solder layer 7, 8 Protrusion

Claims (1)

絶縁基板の銅回路パターンもしくは銅回路パターン上にマウントした半導体チップにリードフレームを半田接合した接続構造を有する半導体装置において、
前記リードフレーム, 銅回路パターンのいずれか一方の半田接合面に半田層の厚さに相応した凸状の突起を形成するものとし、かつ該突起を半田接合面に塗布形成した導電性接着剤で形成したことを特徴とする半導体装置。 In a semiconductor device having a connection structure in which a lead frame is solder-bonded to a copper circuit pattern of an insulating substrate or a semiconductor chip mounted on the copper circuit pattern,
A convex protrusion corresponding to the thickness of the solder layer is formed on the solder joint surface of either the lead frame or the copper circuit pattern, and a conductive adhesive is formed by coating the protrusion on the solder joint surface. A semiconductor device formed.
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WO2012157583A1 (en) 2011-05-13 2012-11-22 富士電機株式会社 Semiconductor device and manufacturing method thereof
WO2012157584A1 (en) 2011-05-13 2012-11-22 富士電機株式会社 Semiconductor device and manufacturing method thereof

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JP2007251076A (en) * 2006-03-20 2007-09-27 Hitachi Ltd Power semiconductor module
WO2012127696A1 (en) * 2011-03-24 2012-09-27 三菱電機株式会社 Power semiconductor module and power unit device
JP6289583B1 (en) * 2016-10-24 2018-03-07 三菱電機株式会社 Power semiconductor device

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