JP2005340393A - Small-sized mount module and manufacturing method thereof - Google Patents

Small-sized mount module and manufacturing method thereof Download PDF

Info

Publication number
JP2005340393A
JP2005340393A JP2004155245A JP2004155245A JP2005340393A JP 2005340393 A JP2005340393 A JP 2005340393A JP 2004155245 A JP2004155245 A JP 2004155245A JP 2004155245 A JP2004155245 A JP 2004155245A JP 2005340393 A JP2005340393 A JP 2005340393A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor chip
bump
bonding
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004155245A
Other languages
Japanese (ja)
Inventor
Takashi Nakayama
高志 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp filed Critical Olympus Corp
Priority to JP2004155245A priority Critical patent/JP2005340393A/en
Publication of JP2005340393A publication Critical patent/JP2005340393A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized mount module wherein a semiconductor chip is mounted on a bent and swollen circuit board with flip-chip connection with electric and mechanical reliability. <P>SOLUTION: A joining planar part 2c for configuring a flat surface 2b formed to each of stud bump 4a provided to the circuit board 2 arranged to a reference plane 10 is deposited to the semiconductor chip 3 provided with terminal electrodes 3a opposed to each other, to set each of electrode planes 3b and each of the joining planar parts 2c to a parallel positional relation. Then each of the terminal electrodes 3a of the semiconductor chip 3 is located on each of the joining planar parts 2c formed to each of the stud bumps 4a. In this case, each electrode plane 3b of each of the terminal electrodes 3a provided to the semiconductor chip 3 and each joining planar part 2c of each stud bump 4a provided to the circuit board 2 are brought into a uniform contact state. The semiconductor chip 3 and the circuit board 2 are joined and fixed to each other through the thermocompression bonding at a prescribed temperature under a prescribed pressure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板上に半導体チップを実装して構成される小型実装モジュール及びその製造方法に関する。   The present invention relates to a small mounting module configured by mounting a semiconductor chip on a circuit board and a manufacturing method thereof.

近年、ＬＳＩチップ等の半導体チップを回路基板上に実装するに当たって、小型高機能化が強く求められている。このため、半導体チップを回路基板上に実装する方法として、回路基板面に対して半導体チップを直接実装する、いわゆるフリップチップ接続が採用されている。このフリップチップ接続では、半導体チップと回路基板の電極との電気的接続を、半田、金（Ａｕ）等の材料から構成される金属バンプを介して一括接続で行うことができる。   In recent years, in order to mount a semiconductor chip such as an LSI chip on a circuit board, there has been a strong demand for miniaturization and high functionality. For this reason, as a method for mounting the semiconductor chip on the circuit board, a so-called flip chip connection in which the semiconductor chip is directly mounted on the circuit board surface is employed. In this flip chip connection, electrical connection between the semiconductor chip and the electrodes of the circuit board can be performed in a lump connection via metal bumps made of a material such as solder or gold (Au).

前記回路基板がガラスエポキシ基板、セラミック基板等の有機基板及びセラミック基板等の無機基板においては、導電パターンが形成された基板表面（実装面とも記載する）に反りやうねりが発生して平坦化が損なわれ、このことによって、基板表面に形成されている接続パターンの高さ方向の寸法にバラツキが生じる。   In the case where the circuit board is an organic substrate such as a glass epoxy substrate or a ceramic substrate and an inorganic substrate such as a ceramic substrate, the substrate surface (also referred to as a mounting surface) on which a conductive pattern is formed is warped or swelled and flattened. This causes a variation in the height dimension of the connection pattern formed on the substrate surface.

すると、例えば半導体チップの端子電極に形成されたＡｕバンプと回路基板の接続パターンとをフリップチップ接続する際、接続パターンの高さ方向の寸法にバラツキが生じていることにより、接触圧が不均一になる。そして、接触圧が不均一な状態で、Ａｕバンプと接続パターンとをフリップチップ接続することによって、Ａｕバンプと接続パターンとの接合部の接合状態が不均一になることが考えられる。つまり、接合部によって、導通不良や機械的接続強度の低下等の不具合が発生するおそれがある。   Then, for example, when the Au bump formed on the terminal electrode of the semiconductor chip and the connection pattern of the circuit board are flip-chip connected, the contact pressure is non-uniform due to the variation in the height dimension of the connection pattern. become. Then, it is conceivable that the bonding state of the bonding portion between the Au bump and the connection pattern becomes non-uniform by performing flip chip connection between the Au bump and the connection pattern in a state where the contact pressure is non-uniform. That is, there is a possibility that problems such as poor conduction and a decrease in mechanical connection strength may occur due to the joint.

また、図１３に示すように内層パターン１３ａを有する多層積層基板である例えば有機ビルトアップ基板１３において、実装面の平坦化が損なわれていると、半導体チップ１２をビルトアップ基板１３に対してフリップチップ接続する際、接触圧が不均一になって、応力の偏りによる基板の沈降で、内層パターン１３ａ、１３ａ同士が接触するという不具合が発生するおそれがあった。なお、符号１２ａは端子電極、符号１３ｂは接続パターンである。   Further, for example, in the organic built-up substrate 13 which is a multilayer laminated substrate having the inner layer pattern 13 a as shown in FIG. 13, if the mounting surface is flattened, the semiconductor chip 12 is flipped with respect to the built-up substrate 13. When the chips are connected, the contact pressure becomes non-uniform, and there is a possibility that the inner layer patterns 13a and 13a come into contact with each other due to the sedimentation of the substrate due to the stress bias. Reference numeral 12a is a terminal electrode, and reference numeral 13b is a connection pattern.

前述した電気的な接続の不具合や機械的接続強度の低下を解消するため、例えば、特開２００１−７１５５号公報にはフリップチップ接続構造体が示されている。このフリップチップ接続構造体においては、反り、うねりの大きい回路基板上に半導体チップをフェースダウンボンディングする場合、回路基板の反りが大きい端子電極に対して、他の端子電極に形成されたＡｕバンプよりも接続面積が大きくなるように、寸法の大きなＡｕバンプを形成して接続を行う。このことによって、反り、うねりの大きい回路基板に対して半導体チップをフリップチップ接続する場合において、電気的接続及び機械的接続の信頼性が向上する。
特開２００１−７１５５号公報 In order to eliminate the above-described problems of electrical connection and a decrease in mechanical connection strength, for example, Japanese Unexamined Patent Application Publication No. 2001-7155 discloses a flip chip connection structure. In this flip-chip connection structure, when a semiconductor chip is face-down bonded on a circuit board having a large warp and undulation, a terminal electrode having a large warp of the circuit board is compared with an Au bump formed on another terminal electrode. In addition, an Au bump having a large dimension is formed so as to increase the connection area. This improves the reliability of electrical connection and mechanical connection when a semiconductor chip is flip-chip connected to a circuit board with large warping and undulation.
JP 2001-7155 A

しかしながら、前記特開２００１−７１５５号公報のフリップチップ接続構造体においては、信頼性の高いフリップチップ接続を行うために、それぞれ基板の変形具合に対して選択的に寸法の異なる２種類以上のバンプを形成しなければならない。このため、量産性が損なわれる。また、反り、うねりの大きい場所に接続面積が大きくなるように寸法の大きなバンプを形成するため、高密度実装に弊害が生じる。   However, in the flip chip connection structure disclosed in Japanese Patent Application Laid-Open No. 2001-7155, two or more types of bumps having different dimensions selectively with respect to the deformation state of the substrate in order to perform highly reliable flip chip connection. Must be formed. For this reason, mass productivity is impaired. In addition, since bumps having large dimensions are formed so that the connection area becomes large in a place where warpage and undulation are large, there is a problem in high-density mounting.

本発明は上記事情に鑑みてなされたものであり、反り、うねりを有する回路基板に対して半導体チップを、電気的、機械的な信頼性が高く、かつ高密度に量産性を損なうことなく、フリップチップ接続によって実装した小型実装モジュール及びその製造方法を提供することを目的にしている。   The present invention has been made in view of the above circumstances, a semiconductor chip for a circuit board having warpage and undulation, electrical and mechanical reliability is high, and without impairing mass productivity at high density, It is an object of the present invention to provide a small mounting module mounted by flip chip connection and a manufacturing method thereof.

本発明の小型実装モジュールは、回路基板上の接続パターンと半導体チップの端子電極とをフリップチップ接続によって実装して構成される小型実装モジュールにおいて、
前記半導体チップが実装される前記回路基板に設けられた接続パターンに、整形可能な金属バンプを設けている。 The small mounting module of the present invention is a small mounting module configured by mounting the connection pattern on the circuit board and the terminal electrode of the semiconductor chip by flip chip connection.
Metal bumps that can be shaped are provided on connection patterns provided on the circuit board on which the semiconductor chip is mounted.

そして、前記回路基板の接続パターンに設けられた金属バンプの接合面側に、前記端子電極の電極平面に平行で平坦面を構成する接合用平面部を設けている。   Further, a bonding plane portion that forms a flat surface parallel to the electrode plane of the terminal electrode is provided on the bonding surface side of the metal bump provided in the connection pattern of the circuit board.

この構成によれば、実装面に反りやうねりを有する回路基板上の接続パターンに設けた金属バンプの接合面側に、例えば常温において接合用平面部を形成することによって、フリップチップ接続する際に接触する、回路基板に設けられた金属バンプの接合用平面部と、端子電極の電極平面とが平行平面になる。   According to this configuration, when a flip chip connection is made by forming a flat portion for bonding at a room temperature, for example, on the bonding surface side of the metal bump provided on the connection pattern on the circuit board having warpage and undulation on the mounting surface. The contacting flat part of the metal bumps provided on the circuit board and the electrode plane of the terminal electrode are parallel planes.

また、本発明の小型モジュールの製造方法は、回路基板上の実装面に設けられている接続パターンに、整形可能な金属バンプを設けるバンプ形成工程と、常温において、前記バンプ形成工程によって前記接続パターン上に設けられた金属バンプの接合面側に平坦面形成部材の基準面を押圧して、前記金属バンプの接合面側に平坦面を構成する接合用平面部を整形するバンプ接合面平坦化工程と、前記バンプ接合面平坦化工程において整形された前記金属バンプの接合用平面部と半導体チップの端子電極とをフリップチップ接続する実装工程とを具備している。   In addition, the method for manufacturing a small module according to the present invention includes a bump forming step of providing a shapeable metal bump on a connection pattern provided on a mounting surface on a circuit board, and the connection pattern by the bump forming step at room temperature. A bump bonding surface flattening step of shaping a flat surface for bonding constituting a flat surface on the bonding surface side of the metal bump by pressing the reference surface of the flat surface forming member on the bonding surface side of the metal bump provided on the surface And a mounting step of flip-chip connecting the flat portion for bonding of the metal bumps shaped in the bump bonding surface flattening step and the terminal electrode of the semiconductor chip.

この製造方法によれば、バンプ形成工程及びバンプ接合面平坦化工程を経た回路基板に対して金導体チップをフリップチップ接続する際、回路基板に設けられた金属バンプの接合用平面部と半導体チップの端子電極の電極平面とが均一な接触圧で当接した状態で、電気的・物理的に接合される。   According to this manufacturing method, when a gold conductor chip is flip-chip connected to a circuit board that has undergone a bump forming process and a bump bonding surface flattening process, a planar part for bonding metal bumps provided on the circuit board and a semiconductor chip The electrode planes of the terminal electrodes are electrically and physically joined in a state where they contact with a uniform contact pressure.

本発明による小型実装モジュールは、回路基板上の接続パターンと半導体チップの端子電極とをフリップチップ接続によって実装して構成されるものにおいて、反り、うねりを有する回路基板に対して半導体チップを、電気的及び機械的な信頼性が高く、かつ高密度に実装できる効果を有する。   The small mounting module according to the present invention is configured by mounting the connection pattern on the circuit board and the terminal electrode of the semiconductor chip by flip chip connection. The semiconductor chip is electrically connected to the circuit board having warpage and undulation. The mechanical and mechanical reliability is high, and there is an effect that can be mounted at a high density.

以下、図面を参照して本発明の実施の形態を説明する。
図１ないし図５は本発明の一実施形態に係り、図１は小型実装モジュールを説明する図、図２はバンプ形成工程におけるスタッドバンプを設けた回路基板を示す図、図３はスタッドバンプの接合面側に平坦面を整形するバンプ接合面平坦化工程を説明する図、図４はバンプ接合面平坦化工程で整形された平坦面を有する回路基板を説明する図、図５は実装工程における回路基板と半導体チップとを説明する図である。 Embodiments of the present invention will be described below with reference to the drawings.
1 to 5 relate to an embodiment of the present invention, FIG. 1 is a diagram for explaining a small mounting module, FIG. 2 is a diagram showing a circuit board provided with stud bumps in a bump forming process, and FIG. FIG. 4 is a diagram for explaining a bump bonding surface flattening step for shaping a flat surface on the bonding surface side, FIG. 4 is a diagram for explaining a circuit board having a flat surface shaped in the bump bonding surface flattening step, and FIG. It is a figure explaining a circuit board and a semiconductor chip.

図１に示すように本実施形態の小型実装モジュール１は回路基板２上に半導体チップ３を実装して構成される。本実施形態においては、回路基板２の接続パターン２ａの所定部に金バンプ（以下、バンプと略記する）４が設けられている。そして、回路基板２の接続パターン２ａに設けられた各バンプ４と、半導体チップ３に設けられている各端子電極３ａとが、フリップチップ接続によって、電気的及び機械的に接合されている。   As shown in FIG. 1, the small mounting module 1 of the present embodiment is configured by mounting a semiconductor chip 3 on a circuit board 2. In the present embodiment, gold bumps (hereinafter abbreviated as bumps) 4 are provided on predetermined portions of the connection pattern 2 a of the circuit board 2. And each bump 4 provided in the connection pattern 2a of the circuit board 2 and each terminal electrode 3a provided in the semiconductor chip 3 are electrically and mechanically joined by flip chip connection.

ここで、図２乃至図５を参照して小型実装モジュール１の製造工程を順に説明する。
まず、小型実装モジュール１を製造するに当たって、回路基板２と、半導体チップ３とを用意する。回路基板２は例えばセラミック基板であり、実装面には接続パターン２ａが設けられている。回路基板２の接続パターン２ａが設けられた実装面には、反り、うねり等が発生している。 Here, the manufacturing process of the small mounting module 1 will be described in order with reference to FIGS.
First, in manufacturing the small mounting module 1, a circuit board 2 and a semiconductor chip 3 are prepared. The circuit board 2 is, for example, a ceramic board, and a connection pattern 2a is provided on the mounting surface. The mounting surface provided with the connection pattern 2a of the circuit board 2 is warped, swelled, and the like.

次に、図２を参照してバンプ形成工程を説明する。
図に示すように実装面に例えば反りが発生している回路基板２を、基準平面１０上に配置する。そして、回路基板２の実装面上に設けられているそれぞれの接続パターン２ａ上に、例えばスタッドバンプ４ａ、…、４ａを設ける。このとき、スタッドバンプ４ａの高さ寸法は、回路基板２の反り大きさを考慮して所定寸法に設定される。 Next, the bump forming process will be described with reference to FIG.
As shown in the figure, the circuit board 2 in which the mounting surface is warped, for example, is arranged on the reference plane 10. Then, on each connection pattern 2a provided on the mounting surface of the circuit board 2, for example, stud bumps 4a,..., 4a are provided. At this time, the height dimension of the stud bump 4 a is set to a predetermined dimension in consideration of the warp size of the circuit board 2.

ここで、スタッドバンプは常温或いは高温でも、さらには低圧力若しくは高圧力でも整形可能である。   Here, the stud bump can be shaped even at room temperature or high temperature, or even at low pressure or high pressure.

次いで、図３及び図４を参照してバンプ接合面平坦化工程を説明する。
図に示すように回路基板２の実装面に、二点鎖線に示す前記半導体チップ３と略同形状で形成されている平坦面形成部材５の平坦面形成面５ａを対向配置させる。この平坦面形成面５ａは、基準平面１０に対して平行である。 Next, the bump bonding surface flattening step will be described with reference to FIGS.
As shown in the figure, the flat surface forming surface 5a of the flat surface forming member 5 formed in substantially the same shape as that of the semiconductor chip 3 indicated by the two-dot chain line is disposed opposite to the mounting surface of the circuit board 2. The flat surface forming surface 5 a is parallel to the reference plane 10.

そして、平坦面形成部材５の平坦面形成面５ａを矢印に示すように回路基板２の実装面側に移動し、スタッドバンプ４ａ、…、４ａの接合面側を所定の力量で所定時間押圧する。その後、再び、平坦面形成部材５を元の位置に移動する。   Then, the flat surface forming surface 5a of the flat surface forming member 5 is moved to the mounting surface side of the circuit board 2 as indicated by the arrow, and the joint surface side of the stud bumps 4a,. . Thereafter, the flat surface forming member 5 is moved again to the original position.

回路基板２の接続パターン２ａ上に設けられた各スタッドバンプ４ａの接合面側の突起部分が平坦面形成面５ａによって押圧されたことによって、図４に示すように各スタッドバンプ４ａの接合面側の突起部分は押しつぶされて、実装面の有する反りやうねりに関わらず、基準平面１０に対して平行な一点鎖線に示す平坦面２ｂを構成する接合用平面部２ｃが各スタッドバンプ４ａに一括して形成される。
このことによって、回路基板２に設けられている各スタッドバンプ４ａ、…、４ａの接合用平面部２ｃの基準平面１０に対する高さ寸法のバラツキが解消される。 As shown in FIG. 4, the joint surface side of each stud bump 4a is pressed by the flat surface forming surface 5a by pressing the projection on the joint surface side of each stud bump 4a provided on the connection pattern 2a of the circuit board 2. The protruding flat portions 2c are crushed, and the joining flat portions 2c constituting the flat surface 2b shown by the alternate long and short dash line parallel to the reference plane 10 are collectively put on each stud bump 4a regardless of the warping or waviness of the mounting surface. Formed.
As a result, the variation in the height dimension of each of the stud bumps 4a,..., 4a provided on the circuit board 2 with respect to the reference plane 10 of the bonding plane portion 2c is eliminated.

最後に、図５を参照してフリップチップ接続による実装工程を説明する。
基準平面１０に対して配置された回路基板２に設けられているスタッドバンプ４ａに平坦面２ｂが形成されたなら、この回路基板２に対して前記平坦面形成部材５の代わりに、端子電極３ａが設けられている半導体チップ３を対向配置させる。この半導体チップ３の表面は、基準平面１０に対して平行である。したがって、半導体チップ３の電極平面３ｂは、回路基板２の接合用平面部２ｃに対して平行な位置関係になる。 Finally, a mounting process by flip chip connection will be described with reference to FIG.
If the flat surface 2 b is formed on the stud bump 4 a provided on the circuit board 2 arranged with respect to the reference plane 10, the terminal electrode 3 a is used instead of the flat surface forming member 5 on the circuit board 2. The semiconductor chip 3 provided with is arranged to face each other. The surface of the semiconductor chip 3 is parallel to the reference plane 10. Therefore, the electrode plane 3 b of the semiconductor chip 3 is in a positional relationship parallel to the bonding plane portion 2 c of the circuit board 2.

その後、図に示すように半導体チップ３の端子電極３ａをスタッドバンプ４ａに形成されている平坦面２ｂを構成する接合用平面部２ｃ上に配置させる。このとき、半導体チップ３に設けられている各端子電極３ａの電極平面３ｂと、回路基板２に設けられている各スタッドバンプ４ａの接合用平面部２ｃとが均一な接触状態になる。そして、所定の温度及び圧力による熱圧着を行って半導体チップ３を回路基板２上に接合固定する。このことによって、前記図１に示した小型実装モジュール１が熱圧着によって形成される。   Thereafter, as shown in the figure, the terminal electrode 3a of the semiconductor chip 3 is disposed on the bonding flat portion 2c constituting the flat surface 2b formed on the stud bump 4a. At this time, the electrode flat surface 3b of each terminal electrode 3a provided on the semiconductor chip 3 and the bonding flat portion 2c of each stud bump 4a provided on the circuit board 2 are in a uniform contact state. Then, the semiconductor chip 3 is bonded and fixed on the circuit board 2 by thermocompression bonding at a predetermined temperature and pressure. Thereby, the small mounting module 1 shown in FIG. 1 is formed by thermocompression bonding.

このように、接続パターンが設けられて、反りやうねりが発生している回路基板に対して半導体チップをフリップチップ接続する際、回路基板の接続パターン上にスタッドバンプを設け、そのスタッドバンプの接合面側に所定の平坦面を構成する接合用平面部を形成し、この接合用平面部に半導体チップの各端子電極の電極平面を接合して小型実装モジュールを形成することによって、所望の高密度実装を行うことができる。   Thus, when a semiconductor chip is flip-chip connected to a circuit board on which a connection pattern is provided and warps or undulates, a stud bump is provided on the circuit board connection pattern, and the stud bump is joined. A flat surface for bonding that constitutes a predetermined flat surface is formed on the surface side, and an electrode flat surface of each terminal electrode of the semiconductor chip is bonded to the flat surface for bonding to form a small mounting module, thereby obtaining a desired high density Can be implemented.

また、接続パターンが設けられた回路基板に対して半導体チップをフリップチップ接続する際、回路基板に発生している反りやうねりを考慮して接続パターンの上に所定の高さ寸法のスタッドバンプを設け、各スタッドバンプの接合面側に所定の平坦面を構成する接合用平面部を形成している。このことによって、回路基板と半導体チップとをフリップチップ接続するために、スタッドバンプと端子電極とを当接させた際、各端子電極の電極平面と、各スタッドバンプの平坦面を構成する接合用平面部との接触圧を均一にすることができる。   In addition, when flip chip connecting a semiconductor chip to a circuit board provided with a connection pattern, a stud bump having a predetermined height is formed on the connection pattern in consideration of warpage and undulation generated on the circuit board. Provided is a bonding flat portion that forms a predetermined flat surface on the bonding surface side of each stud bump. As a result, when the stud bump and the terminal electrode are brought into contact with each other in order to make a flip-chip connection between the circuit board and the semiconductor chip, the electrode plane of each terminal electrode and the flat surface of each stud bump are formed. The contact pressure with the flat portion can be made uniform.

これらのことによって、接続パターンが設けられて実装面に反りやうねり等が発生している回路基板に対して半導体チップをフリップチップ接続によって実装して形成された小型実装モジュールの電気的接続の信頼性及び機械的接続の信頼性が大幅に向上する。また、内層パターンを有する例えば有機ビルトアップ基板においても、スタッドバンプの接合面側に接合用平面部を形成し、その接合用平面部に半導体チップに設けられている端子電極の電極平面を当接させることによって、接触圧のバラツキによって基板が沈降して発生する内層パターン同士の接触を防止した小型実装モジュールを形成することができる。   As a result, reliability of electrical connection of a small mounting module formed by mounting a semiconductor chip by flip chip connection on a circuit board on which a connection pattern is provided and the mounting surface is warped or undulated. And the reliability of mechanical connection are greatly improved. Also, for example, in an organic built-up substrate having an inner layer pattern, a bonding flat portion is formed on the bonding surface side of the stud bump, and the electrode flat surface of the terminal electrode provided on the semiconductor chip is brought into contact with the bonding flat portion. By doing so, it is possible to form a small mounting module in which contact between the inner layer patterns generated by the substrate settling due to variations in contact pressure is prevented.

さらに、実装工程の前段に、バンプ形成工程及びバンプ接合面平坦化工程を設けることによって、特別な設備の追加等を行うことなく、小型実装モジュールの生産を連続的に行うことができる。   Furthermore, by providing a bump formation step and a bump bonding surface flattening step before the mounting step, it is possible to continuously produce small mounting modules without adding special equipment.

図６ないし図８は小型実装モジュールの他の構成例にかかり、図６は金メッキバンプを設けた回路基板を説明する図、図７はバンプ接合面平坦化工程で整形された平坦面を有する回路基板を説明する図、図８は実装工程における回路基板と半導体チップとを説明する図である。   FIGS. 6 to 8 relate to another configuration example of the small mounting module, FIG. 6 is a diagram illustrating a circuit board provided with gold-plated bumps, and FIG. 7 is a circuit having a flat surface shaped in the bump bonding surface flattening step. FIG. 8 is a diagram illustrating a circuit board and a semiconductor chip in a mounting process.

前記実施形態においては、回路基板２の接続パターン２ａに設けるバンプ４をスタッドバンプ４ａとしていたが、図６に示すように本実施形態においてはバンプ４を金メッキバンプ４ｂとしている。回路基板２Ａに設けられる金メッキバンプ４ｂは、接続パターン２ａからの高さ寸法が同一に形成することが可能であるが、前述の回路基板２と同様に実装面に反りやうねり等が生じることによって、たとえ予め高さ寸法を同一に形成した場合であっても、例えば反りによって基準平面１０に対する金メッキバンプ４ｂの高さ方向の寸法に対してバラツキが生じる。   In the embodiment, the bumps 4 provided on the connection pattern 2a of the circuit board 2 are the stud bumps 4a. However, in the present embodiment, the bumps 4 are the gold plating bumps 4b as shown in FIG. The gold-plated bumps 4b provided on the circuit board 2A can be formed to have the same height from the connection pattern 2a. However, as with the circuit board 2, the mounting surface is warped or swelled. Even if the height dimension is formed in advance, for example, the height dimension of the gold-plated bump 4b with respect to the reference plane 10 varies due to warpage.

このため、金メッキバンプ４ｂを設けた回路基板２Ａにおいても、バンプ接合面平坦化工程で、図中の二点鎖線で示すように平坦面形成部材５を配置させて、金メッキバンプ４ｂの接合面側を所定の力量で所定時間押圧する。このことによって、図７に示すように各金メッキバンプ４ｂ、…、４ｂの接合面側が押しつぶされて、実装面の有する反りやうねりに関わらず、基準平面１０に対して平行な一点鎖線に示す平坦面２ｂを構成する接合用平面部２ｃが各金メッキバンプ４ｂに一括して形成される。そして、本実施形態においても、回路基板２に対して半導体チップ３を対向配置させたとき、半導体チップ３の電極平面３ｂと、回路基板２の接合用平面部２ｃとが平行な位置関係になる。
その他の構成は前記実施形態と同様であり、同部材には同符号を付して説明を省略する。 For this reason, even in the circuit board 2A provided with the gold plating bumps 4b, the flat surface forming member 5 is disposed in the bump bonding surface flattening step as shown by a two-dot chain line in the figure, and the bonding surface side of the gold plating bumps 4b is arranged. Is pressed for a predetermined time with a predetermined amount of force. As a result, as shown in FIG. 7, the bonding surface side of each gold plating bump 4b,..., 4b is crushed, and the flat surface shown by the alternate long and short dash line parallel to the reference plane 10 regardless of the warp or undulation of the mounting surface. A joining flat surface portion 2c constituting the surface 2b is collectively formed on each gold plating bump 4b. Also in this embodiment, when the semiconductor chip 3 is disposed opposite to the circuit board 2, the electrode plane 3 b of the semiconductor chip 3 and the bonding plane portion 2 c of the circuit board 2 have a parallel positional relationship. .
Other configurations are the same as those of the above-described embodiment, and the same members are denoted by the same reference numerals and description thereof is omitted.

したがって、前述した実施形態と同様に、実装工程において、図８に示すように半導体チップ３に設けられている端子電極３ａの電極平面３ｂを、金メッキバンプ４ｂに形成されている平坦面２ｂを構成する接合用平面部２ｃ上に配置させたとき、半導体チップ３の電極平面３ｂと、回路基板２に設けられている各金メッキバンプ４ｂの接合用平面部２ｃとの間に均一な接触圧がかかった状態にして、熱圧着による半導体チップ３と回路基板２との接合を行える。このことによって、前述した実施形態と同様の作用及び効果を得ることができる。   Therefore, as in the embodiment described above, in the mounting process, as shown in FIG. 8, the electrode plane 3b of the terminal electrode 3a provided on the semiconductor chip 3 is formed with the flat surface 2b formed on the gold plating bump 4b. When arranged on the bonding plane portion 2c to be applied, a uniform contact pressure is applied between the electrode plane 3b of the semiconductor chip 3 and the bonding plane portion 2c of each gold plating bump 4b provided on the circuit board 2. In this state, the semiconductor chip 3 and the circuit board 2 can be joined by thermocompression bonding. As a result, the same operations and effects as those of the above-described embodiment can be obtained.

なお、金メッキバンプの形成に当たっては、通常のメッキ温度であれば良く、圧力は無関係となる。   In forming the gold-plated bumps, a normal plating temperature may be used, and the pressure is irrelevant.

図９ないし図１２は小型実装モジュールの別の構成例にかかり、図９はスタッドバンプを設けた回路基板と金メッキバンプを設けた半導体チップとを説明する図、図１０は実装工程における回路基板と半導体チップとを説明する図、図１１は小型実装モジュールの応用例にかかるＮＣＰ法によるフリップチップ接続を説明する図、図１２は小型実装モジュールの他の応用例にかかる超音波法によるフリップチップ接続を説明する図である。   9 to 12 relate to another configuration example of the small mounting module. FIG. 9 illustrates a circuit board provided with stud bumps and a semiconductor chip provided with gold plating bumps. FIG. 10 illustrates circuit boards in a mounting process. FIG. 11 is a diagram for explaining flip chip connection by NCP method according to an application example of a small mounting module, and FIG. 12 is a flip chip connection by ultrasonic method according to another application example of the small mounting module. FIG.

上述した実施形態においては、回路基板２の接続パターン２ａにスタッドバンプ４ａ又は金メッキバンプ４ｂを設けていたのに対し、本実施形態においては図９に示すように回路基板２に加えて、半導体チップ３に設けられている端子電極３ａの電極平面３ｂにも例えばスタッドバンプ４ｃを設けている。そして、各スタッドバンプ４ｃの接合面側に、半導体チップ３の表面に対して平行なチップ側接合用平面部４ｄを形成する。そして、回路基板２に対して半導体チップ３を対向配置させたとき、半導体チップ３のチップ側接合用平面部４ｄと、回路基板２の接合用平面部２ｃとが平行な配置関係になる。
その他の構成は前記実施形態と同様であり、同部材には同符号を付して説明を省略する。 In the embodiment described above, the connection pattern 2a of the circuit board 2 is provided with the stud bump 4a or the gold plating bump 4b, whereas in this embodiment, in addition to the circuit board 2, as shown in FIG. For example, stud bumps 4 c are also provided on the electrode plane 3 b of the terminal electrode 3 a provided on 3. Then, on the bonding surface side of each stud bump 4c, a chip-side bonding flat portion 4d parallel to the surface of the semiconductor chip 3 is formed. When the semiconductor chip 3 is disposed opposite to the circuit board 2, the chip-side bonding plane part 4 d of the semiconductor chip 3 and the bonding plane part 2 c of the circuit board 2 have a parallel arrangement relationship.
Other configurations are the same as those of the above-described embodiment, and the same members are denoted by the same reference numerals and description thereof is omitted.

図１０に示すように半導体チップ３の電極平面３ｂに設けられたスタッドバンプ４ｃに形成されたチップ側接合用平面部４ｄを、回路基板２のスタッドバンプ４ａに形成されている接合用平面部２ｃ上に配置した際、前述と同様に半導体チップ３のチップ側接合用平面部４ｄと、回路基板２の接合用平面部２ｃとの間に均一な接触圧がかかるとともに、回路基板２と半導体チップ３との間に、スタッドバンプ４ｃの高さ寸法分だけ間隔の広がった間隙を得られる。   As shown in FIG. 10, the chip-side bonding plane portion 4 d formed on the stud bump 4 c provided on the electrode plane 3 b of the semiconductor chip 3 is replaced with the bonding plane portion 2 c formed on the stud bump 4 a of the circuit board 2. When arranged above, a uniform contact pressure is applied between the chip-side bonding flat part 4d of the semiconductor chip 3 and the bonding flat part 2c of the circuit board 2 as described above, and the circuit board 2 and the semiconductor chip 3, a gap having a gap widened by the height dimension of the stud bump 4 c can be obtained.

このことによって、反りやうねりの発生した回路基板２のエッジ部と半導体チップ３のエッジ部とが接触することをより確実に防止することができる。その他の作用及び効果は前述した実施形態と同様である。   As a result, it is possible to more reliably prevent the edge portion of the circuit board 2 and the edge portion of the semiconductor chip 3 that are warped or undulated from coming into contact with each other. Other operations and effects are the same as those of the above-described embodiment.

なお、回路基板２と半導体チップ３とをフリップチップ接続する際、上述したいわゆる熱圧着ではなく図１１に示すように回路基板２の実装面側に熱硬化樹脂６を塗布し、その後、半導体チップ３を配置させた状態で、熱硬化樹脂６を硬化させて、半導体チップ３と回路基板２とを電気的及び機械的に接合固定する。このことによって、熱硬化樹脂を用いたＮＣＰ法による小型実装モジュール１が形成される。   When the circuit board 2 and the semiconductor chip 3 are flip-chip connected, the thermosetting resin 6 is applied to the mounting surface side of the circuit board 2 as shown in FIG. The thermosetting resin 6 is cured in a state where the 3 is disposed, and the semiconductor chip 3 and the circuit board 2 are bonded and fixed electrically and mechanically. Thus, the small mounting module 1 by the NCP method using the thermosetting resin is formed.

この実施形態においては、半導体チップ３の電極平面３ｂに設けられたスタッドバンプ４ｃに形成されたチップ側接合用平面部４ｄを、回路基板２のスタッドバンプ４ａに形成されている接合用平面部２ｃ上に配置させた際、前述と同様に半導体チップ３のチップ側接合用平面部４ｄと、回路基板２の接合用平面部２ｃとの間に均一な接触圧がかかる。したがって、回路基板２に塗布された熱硬化樹脂６がチップ側接合用平面部４ｄと接合用平面部２ｃとの間から均一に排除される。したがって、ＮＣＰ法における電気的接続の信頼性の大幅な向上を図れる。   In this embodiment, the chip-side bonding plane portion 4d formed on the stud bump 4c provided on the electrode plane 3b of the semiconductor chip 3 is replaced with the bonding plane portion 2c formed on the stud bump 4a of the circuit board 2. When arranged above, a uniform contact pressure is applied between the chip-side bonding flat part 4 d of the semiconductor chip 3 and the bonding flat part 2 c of the circuit board 2 in the same manner as described above. Therefore, the thermosetting resin 6 applied to the circuit board 2 is uniformly excluded from between the chip-side bonding flat portion 4d and the bonding flat portion 2c. Therefore, the reliability of electrical connection in the NCP method can be greatly improved.

なお、ＮＣＰ法によるフリップチップ接続は、熱圧着によるフリップチップ接続に比較して低い温度で、半導体チップと回路基板との接合を行える。このため、ＮＣＰ法において回路基板は、前記セラミック基板に加えて、ガラスエポキシ基板等であっても熱的な影響が緩和されて良好な接合が可能である。   Note that the flip chip connection by the NCP method can bond the semiconductor chip and the circuit board at a lower temperature than the flip chip connection by thermocompression bonding. For this reason, in the NCP method, even if the circuit board is a glass epoxy board or the like in addition to the ceramic board, the thermal influence is alleviated and good bonding is possible.

また、半導体チップ３のチップ側接合用平面部４ｄを、回路基板２の接合用平面部２ｃ上に配置させた際、半導体チップ３のチップ側接合用平面部４ｄと、回路基板２の接合用平面部２ｃとの間に均一な接触圧がかかることを利用して、図１２に示すように回路基板２の接合用平面部２ｃと半導体チップ３のチップ側接合用平面部４ｄとを当接させた状態において、半導体チップ３の裏面３ｃに超音波振動装置に備えられた振動部７を当接させる。そして、所定の荷重下で振動部７から発生される超音波振動によって、接合用平面部２ｃとチップ側接合用平面部４ｄとの接触面を振動させて、半導体チップ３と回路基板２とを電気的及び機械的に接合固定する。このことによって、超音波法による小型実装モジュール１が形成される。   In addition, when the chip-side bonding plane portion 4 d of the semiconductor chip 3 is disposed on the bonding plane portion 2 c of the circuit board 2, the chip-side bonding plane portion 4 d of the semiconductor chip 3 and the circuit board 2 are bonded. By utilizing the fact that a uniform contact pressure is applied to the flat surface portion 2c, the bonding flat surface portion 2c of the circuit board 2 and the chip-side bonding flat surface portion 4d of the semiconductor chip 3 are brought into contact with each other as shown in FIG. In this state, the vibration part 7 provided in the ultrasonic vibration device is brought into contact with the back surface 3 c of the semiconductor chip 3. Then, the ultrasonic vibration generated from the vibration part 7 under a predetermined load vibrates the contact surface between the bonding flat part 2c and the chip-side bonding flat part 4d, so that the semiconductor chip 3 and the circuit board 2 are brought together. Bonded and fixed electrically and mechanically. Thereby, the small mounting module 1 by the ultrasonic method is formed.

なお、本発明は、以上述べた実施形態のみに限定されるものではなく、発明の要旨を逸脱しない範囲で種々変形実施可能である。また、本実施形態では、金属バンプとしてスタッドバンプ及び金メッキバンプについて説明したが、これらには限定されず、ＴＡＢ実装に用いる転写バンプを応用して金属バンプを形成しても良い。   It should be noted that the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. In this embodiment, the stud bump and the gold plating bump are described as the metal bump. However, the present invention is not limited to these, and the metal bump may be formed by applying a transfer bump used for TAB mounting.

図１ないし図５は本発明の一実施形態に係り、図１は小型実装モジュールを説明する図1 to 5 relate to one embodiment of the present invention, and FIG. 1 is a diagram for explaining a small mounting module. バンプ形成工程におけるスタッドバンプを設けた回路基板を示す図The figure which shows the circuit board which provided the stud bump in the bump formation process スタッドバンプの接合面側に平坦面を整形するバンプ接合面平坦化工程を説明する図The figure explaining the bump joint surface flattening process which shapes a flat surface on the joint surface side of a stud bump バンプ接合面平坦化工程で整形された平坦面を有する回路基板を説明する図The figure explaining the circuit board which has the flat surface shape | molded by the bump bonding surface flattening process 実装工程における回路基板と半導体チップとを説明する図The figure explaining the circuit board and semiconductor chip in a mounting process 図６ないし図８は小型実装モジュールの他の構成例にかかり、図６は金メッキバンプを設けた回路基板を説明する図6 to 8 relate to another configuration example of the small mounting module, and FIG. 6 is a diagram illustrating a circuit board provided with gold-plated bumps. バンプ接合面平坦化工程で整形された平坦面を有する回路基板を説明する図The figure explaining the circuit board which has the flat surface shape | molded by the bump bonding surface flattening process 実装工程における回路基板と半導体チップとを説明する図The figure explaining the circuit board and semiconductor chip in a mounting process 図９ないし図１２は小型実装モジュールの別の構成例にかかり、図９はスタッドバンプを設けた回路基板と金メッキバンプを設けた半導体チップとを説明する図FIG. 9 to FIG. 12 relate to another configuration example of the small mounting module, and FIG. 9 is a diagram for explaining a circuit board provided with stud bumps and a semiconductor chip provided with gold plating bumps. 実装工程における回路基板と半導体チップとを説明する図The figure explaining the circuit board and semiconductor chip in a mounting process 小型実装モジュールの応用例にかかるＮＣＰ法によるフリップチップ接続を説明する図The figure explaining the flip chip connection by the NCP method concerning the application example of a small mounting module 小型実装モジュールの他の応用例にかかる超音波法によるフリップチップ接続を説明する図The figure explaining the flip chip connection by the ultrasonic method concerning the other application example of a small mounting module 有機ビルトアップ基板において、内層パターン同士が接触している状態を示す図The figure which shows the state where inner layer patterns are in contact with organic built-up substrate

符号の説明Explanation of symbols

１…小型実装モジュール
２…回路基板
２ａ…接続パターン
２ｂ…平坦面
２ｃ…接合用平面部
３…半導体チップ
３ａ…端子電極
３ｂ…電極平面
４ａ…スタッドバンプ
１０…基準平面
代理人 弁理士 伊藤 進 1 ... Small mounting module
2 ... Circuit board
2a ... Connection pattern 2b ... Flat surface 2c ... Joining plane 3 ... Semiconductor chip 3a ... Terminal electrode 3b ... Electrode plane
4a ... Stud bump
10 ... Reference plane
Attorney Susumu Ito

Claims (6)

回路基板上の接続パターンと半導体チップの端子電極とをフリップチップ接続によって実装して構成される小型実装モジュールにおいて、
前記半導体チップが実装される前記回路基板に設けられた接続パターンに、整形可能な金属バンプを設けたことを特徴とする小型実装モジュール。 In a small mounting module configured by mounting the connection pattern on the circuit board and the terminal electrode of the semiconductor chip by flip chip connection,
A compact mounting module, wherein a shaping metal bump is provided on a connection pattern provided on the circuit board on which the semiconductor chip is mounted. 前記回路基板の接続パターンに設けられた金属バンプの接合面側に、前記端子電極の電極平面に平行で平坦面を構成する接合用平面部を設けたことを特徴とする請求項１に記載の小型実装モジュール。   2. The bonding plane portion that forms a flat surface parallel to the electrode plane of the terminal electrode is provided on the bonding surface side of the metal bump provided in the connection pattern of the circuit board. Small mounting module. 前記金属バンプの接合面に対して平坦面形成部材の基準面を押圧して、前記金属バンプの接合面側に接合用平面部を整形したことを特徴とする請求項２に記載の小型実装モジュール。   3. The small mounting module according to claim 2, wherein the flat surface forming member is shaped on the bonding surface side of the metal bump by pressing the reference surface of the flat surface forming member against the bonding surface of the metal bump. . 回路基板上の接続パターンと半導体チップの端子電極とをフリップチップ接続によって実装して構成される小型実装モジュールにおいて、
前記回路基板に設けられた接続パターンと、前記半導体チップの端子電極との間に一段以上のバンプを形成したことを特徴とする小型実装モジュール。 In a small mounting module configured by mounting the connection pattern on the circuit board and the terminal electrode of the semiconductor chip by flip chip connection,
A small mounting module, wherein one or more bumps are formed between a connection pattern provided on the circuit board and a terminal electrode of the semiconductor chip. 前記回路基板の接続パターン上に、整形可能な金属バンプを設ける一方、前記半導体チップの端子電極上に前記金属バンプを設けたことを特徴とする請求項４に記載の小型実装モジュール。   5. The small mounting module according to claim 4, wherein a metal bump that can be shaped is provided on a connection pattern of the circuit board, and the metal bump is provided on a terminal electrode of the semiconductor chip. 回路基板上の実装面に設けられている接続パターンに、整形可能な金属バンプを設けるバンプ形成工程と、
常温において、前記バンプ形成工程によって前記接続パターン上に設けられた金属バンプの接合面側に平坦面形成部材の基準面を押圧して、前記金属バンプの接合面側に平坦面を構成する接合用平面部を整形するバンプ接合面平坦化工程と、
前記バンプ接合面平坦化工程において整形された前記金属バンプの接合用平面部と半導体チップの端子電極とをフリップチップ接続する実装工程と、
を具備することを特徴とする小型実装モジュールの製造方法。 A bump forming step of providing a metal bump that can be shaped on the connection pattern provided on the mounting surface on the circuit board;
At normal temperature, the reference surface of the flat surface forming member is pressed against the bonding surface side of the metal bump provided on the connection pattern by the bump forming step, and the flat surface is formed on the bonding surface side of the metal bump. A bump bonding surface flattening step for shaping the flat portion;
A mounting step of flip-chip connecting the flat portion for bonding of the metal bump shaped in the bump bonding surface flattening step and the terminal electrode of the semiconductor chip;
The manufacturing method of the small mounting module characterized by comprising.
JP2004155245A 2004-05-25 2004-05-25 Small-sized mount module and manufacturing method thereof Pending JP2005340393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004155245A JP2005340393A (en) 2004-05-25 2004-05-25 Small-sized mount module and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004155245A JP2005340393A (en) 2004-05-25 2004-05-25 Small-sized mount module and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2005340393A true JP2005340393A (en) 2005-12-08

Family

ID=35493628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004155245A Pending JP2005340393A (en) 2004-05-25 2004-05-25 Small-sized mount module and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2005340393A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021902A (en) * 2006-07-14 2008-01-31 Denso Corp Semiconductor device, and its manufacturing method
JP2012231093A (en) * 2011-04-27 2012-11-22 Fujitsu Ltd Semiconductor device, method of manufacturing the same, and electronic device
JP2014154601A (en) * 2013-02-05 2014-08-25 Ricoh Co Ltd Mounting method of electronic component, electronic component mounting body and manufacturing method therefor
CN104377181A (en) * 2013-08-15 2015-02-25 日月光半导体制造股份有限公司 Semiconductor packaging part and manufacturing method thereof
CN108666275A (en) * 2018-04-24 2018-10-16 西南电子技术研究所（中国电子科技集团公司第十研究所） The process of the conformal assembling SIP devices of arc-shaped curved surface PCB substrate
US10141273B2 (en) 2014-04-14 2018-11-27 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
CN112768363A (en) * 2021-04-08 2021-05-07 浙江集迈科微电子有限公司 Curved surface chip mounting structure and preparation method thereof
CN113161243A (en) * 2021-04-15 2021-07-23 浙江集迈科微电子有限公司 Surface chip mounting process

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021902A (en) * 2006-07-14 2008-01-31 Denso Corp Semiconductor device, and its manufacturing method
JP2012231093A (en) * 2011-04-27 2012-11-22 Fujitsu Ltd Semiconductor device, method of manufacturing the same, and electronic device
JP2014154601A (en) * 2013-02-05 2014-08-25 Ricoh Co Ltd Mounting method of electronic component, electronic component mounting body and manufacturing method therefor
CN104377181A (en) * 2013-08-15 2015-02-25 日月光半导体制造股份有限公司 Semiconductor packaging part and manufacturing method thereof
US10141273B2 (en) 2014-04-14 2018-11-27 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US10312199B2 (en) 2014-04-14 2019-06-04 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
CN108666275A (en) * 2018-04-24 2018-10-16 西南电子技术研究所（中国电子科技集团公司第十研究所） The process of the conformal assembling SIP devices of arc-shaped curved surface PCB substrate
CN112768363A (en) * 2021-04-08 2021-05-07 浙江集迈科微电子有限公司 Curved surface chip mounting structure and preparation method thereof
CN113161243A (en) * 2021-04-15 2021-07-23 浙江集迈科微电子有限公司 Surface chip mounting process

Similar Documents

Publication Publication Date Title
US6084310A (en) Semiconductor device, lead frame, and lead bonding
US6586830B2 (en) Semiconductor device with an interposer
JP4729963B2 (en) PROJECT ELECTRODE FOR CONNECTING ELECTRONIC COMPONENT, ELECTRONIC COMPONENT MOUNTING BODY USING SAME, AND METHOD FOR PRODUCING THEM
KR20120091691A (en) Semiconductor device having warpage prevention adhesive pattern and fabricating method the same
US6846699B2 (en) Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
JP4864810B2 (en) Manufacturing method of chip embedded substrate
WO1999034436A1 (en) Semiconductor device
JP2002270717A (en) Semiconductor device
JP2000277649A (en) Semiconductor and manufacture of the same
JP2005340393A (en) Small-sized mount module and manufacturing method thereof
JP3833669B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2005268706A (en) Semiconductor device and multilayer board for same
JP4635836B2 (en) Sheet electronic circuit module
JP2005353854A (en) Wiring board and semiconductor device using the same
JP4699089B2 (en) Chip-on-film semiconductor device
JP2001007155A (en) Flip chip connection structure body
JP3770321B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2000150577A (en) Wiring substrate and manufacture thereof, semiconductor device, and electronic part using the same and manufacture thereof
JP2002170848A (en) Circuit board
US8703533B2 (en) Semiconductor package and method for manufacturing the same
JP3337922B2 (en) Semiconductor device and manufacturing method thereof
JP3446608B2 (en) Semiconductor unit
JP2002252326A (en) Method for manufacturing semiconductor device
KR101178840B1 (en) Substrate for semiconductor package and semiconductor package using the substrate and method of manufacturing semiconductor package using the same
JP3586867B2 (en) Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070423

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090511

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090519

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090929