JP2005353854A - Wiring board and semiconductor device using the same - Google Patents

Wiring board and semiconductor device using the same Download PDF

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JP2005353854A
JP2005353854A JP2004173276A JP2004173276A JP2005353854A JP 2005353854 A JP2005353854 A JP 2005353854A JP 2004173276 A JP2004173276 A JP 2004173276A JP 2004173276 A JP2004173276 A JP 2004173276A JP 2005353854 A JP2005353854 A JP 2005353854A
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semiconductor element
wiring board
connection
connection terminal
bumps
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Yoshiaki Takeoka
嘉昭 竹岡
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of relaxing the positioning accuracy between a flip-chip mounted semiconductor element and a wiring board, and improving the connection positional accuracy and the connection reliability between bumps of the semiconductor element and connection terminals of the wiring board. <P>SOLUTION: The semiconductor element 2 is flip-chip mounted to wiring board 1. In the wiring board 1, the wiring board has a plurality of the connection terminals 7 to which the bumps 6 on a plurality of electrode terminals 5 of the semiconductor element 2 are respectively connected, and is formed with recesses 9 each with a slope 9a that is located at each position of the connection terminals 7 opposed to the bumps and is tilted obliquely downwardly and inwardly from its opening end. The tip of each of the bumps 6 of the semiconductor element 2 can be positioned by being guided along the slope 9a into the recess 9 of each connection terminal 7 of the wiring board 1 at mount of the semiconductor element 2. Thus, while relaxing the positioning accuracy between the semiconductor element 2 and the wring board 1 more than prior arts, the bumps 6 can be positioned to the connection terminals 7 with excellent positioning accuracy. Since the contact area of each bump 6 to each connection terminal 7 is greater than the case with conventional flat connection terminals, the connection reliability is enhanced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子をフリップチップ実装する配線基板およびそれを用いた半導体装置に関するものである。   The present invention relates to a wiring board on which a semiconductor element is flip-chip mounted and a semiconductor device using the wiring board.

携帯情報機器等の小型、軽量化が進むにしたがって半導体装置の高密度化、小型化、薄型化が要求されてきており、これらの要求に応えるために、半導体素子が微細化されるとともに、半導体素子をフリップチップ方式で搭載するパッケージ半導体装置が開発されている。（たとえば特許文献１）
図９はチップサイズパッケージ（ＣＳＰ）と呼ばれるパッケージ半導体装置の断面図である。配線基板１上に半導体素子２がフリップチップ方式で接合されており、配線基板１と半導体素子２との間隙および半導体素子２の周囲は封止樹脂３で封止され、配線基板１の下面にはボール状の外部接続端子４が格子状に配列されている。 As mobile information devices and the like have become smaller and lighter, semiconductor devices have been required to have higher density, smaller size, and thinner thickness. To meet these demands, semiconductor elements have been miniaturized and semiconductor devices have been miniaturized. Package semiconductor devices in which elements are mounted in a flip-chip manner have been developed. (For example, Patent Document 1)
FIG. 9 is a cross-sectional view of a package semiconductor device called a chip size package (CSP). A semiconductor element 2 is bonded to the wiring board 1 by a flip chip method, and the gap between the wiring board 1 and the semiconductor element 2 and the periphery of the semiconductor element 2 are sealed with a sealing resin 3. The ball-shaped external connection terminals 4 are arranged in a grid pattern.

半導体素子２には、その一側面の周縁部に周方向に沿って複数の電極端子５が配列され、各電極端子５上にワイヤボンディング技術を利用して二段突起状のバンプ６（スタッドバンプとも言われる）が形成されている。   In the semiconductor element 2, a plurality of electrode terminals 5 are arranged along the circumferential direction on the peripheral edge portion of one side surface thereof, and bumps 6 (stud bumps) having a two-stage protrusion are formed on each electrode terminal 5 by using a wire bonding technique. Is also formed).

配線基板１の上面には、半導体素子２の複数の電極端子５とバンプ６を介して電気的導通をとるための複数の接続端子７が、半導体素子２の電極端子５，バンプ６に対応する配置で形成されている。各接続端子７は一定の厚みで平坦な形状をしていて、図１０にも示すように、矩形の半導体素子２の搭載領域８の内側から外側にわたって延びている。
このようなパッケージ半導体装置を製造するフリップチップ実装技術の一例に、封止樹脂３となる絶縁性樹脂フィルム（絶縁性樹脂シート、ＮＣＦなどとも呼ばれる）を配線基板１と半導体素子２との間に介在させた状態で熱と荷重とをかけることにより、半導体素子２のバンプ６を変形させながら配線基板１の接続端子７に圧着させ、このバンプ６と接続端子７との接触状態を絶縁性樹脂フィルムの熱硬化によって保持する技術（圧接工法）がある。
特開平５−１７５２７５号公報 On the upper surface of the wiring substrate 1, a plurality of connection terminals 7 for establishing electrical continuity via a plurality of electrode terminals 5 and bumps 6 of the semiconductor element 2 correspond to the electrode terminals 5 and bumps 6 of the semiconductor element 2. It is formed by arrangement. Each connection terminal 7 has a flat shape with a constant thickness, and extends from the inside to the outside of the mounting region 8 of the rectangular semiconductor element 2 as shown in FIG.
As an example of a flip chip mounting technique for manufacturing such a package semiconductor device, an insulating resin film (also referred to as an insulating resin sheet, NCF) serving as a sealing resin 3 is provided between the wiring substrate 1 and the semiconductor element 2. By applying heat and a load in the interposed state, the bump 6 of the semiconductor element 2 is crimped to the connection terminal 7 of the wiring substrate 1 while being deformed, and the contact state between the bump 6 and the connection terminal 7 is insulative resin. There is a technique (pressure welding method) that holds the film by heat curing.
JP-A-5-175275

上記した圧接工法を実施する場合、半導体素子２の電極端子５上に金線を用いてバンプ６を形成しておくのであるが、金製のバンプ６には半田バンプのような接続時セルフアライメント作用はないため、熱圧着時に図１１に示すように金バンプ６が矢印方向にずれ易い。３ａは絶縁性樹脂フィルムである。
一方、半導体素子２の微細化に伴って接合ピッチが狭くなってきており、半導体素子２の電極端子５、金バンプ６が狭パッドピッチ（ファインピッチ）化されるに応じて、配線基板１の接続端子７の設置ピッチも狭くなってきている。
これらのことから、電気的ショートや未接続などの不具合を防止するために、マウント時の半導体素子２と配線基板１との位置合わせを極めて精度よく行わなければならないという問題がある。 When the above-described pressure welding method is carried out, bumps 6 are formed on the electrode terminals 5 of the semiconductor element 2 using gold wires, but the gold bumps 6 are self-aligned during connection such as solder bumps. Since there is no action, the gold bump 6 is likely to be displaced in the direction of the arrow as shown in FIG. 3a is an insulating resin film.
On the other hand, as the semiconductor element 2 is miniaturized, the bonding pitch is narrowed, and as the electrode terminals 5 and the gold bumps 6 of the semiconductor element 2 are narrowed to a fine pad pitch (fine pitch), The installation pitch of the connection terminals 7 is also becoming narrower.
For these reasons, there is a problem that alignment of the semiconductor element 2 and the wiring board 1 at the time of mounting must be performed with extremely high precision in order to prevent problems such as electrical shorts and unconnection.

本発明は上記問題を解決するもので、フリップチップ実装する半導体素子と配線基板との位置合わせ精度の緩和し、かつ、半導体素子のバンプと配線基板の接続端子との接続位置精度および接続信頼性を向上させることを目的とする。   The present invention solves the above-mentioned problems, relaxes the alignment accuracy between the semiconductor element to be flip-chip mounted and the wiring board, and also connects the bumps of the semiconductor element and the connection terminals of the wiring board and the connection reliability. It aims at improving.

上記課題を解決するために本発明は、半導体素子をフリップチップ実装する配線基板を、前記半導体素子の複数の電極端子上に形成されたバンプがそれぞれ接続される複数の接続端子を有し、各接続端子のバンプ対向位置に開口端から斜め下向きに内側へ傾斜した傾斜面を持った凹部が形成された構造としたことを特徴とする。   In order to solve the above problems, the present invention provides a wiring board on which a semiconductor element is flip-chip mounted, a plurality of connection terminals to which bumps formed on the plurality of electrode terminals of the semiconductor element are respectively connected, It is characterized in that a concave portion having an inclined surface inclined inwardly downward from the opening end is formed at the bump facing position of the connection terminal.

接続端子の凹部はエッチングによって形成することができる。
また本発明の半導体装置は、複数の電極端子上にバンプが形成された半導体素子と、前記半導体素子の複数のバンプがそれぞれ接続される複数の接続端子を有し、各接続端子のバンプ対向位置に開口端から斜め下向きに内側へ傾斜した傾斜面を持った凹部が形成された配線基板と、前記半導体素子と配線基板との間隙を封止した封止樹脂とを備え、前記半導体素子の各バンプの先端部が前記配線基板の各接続端子の凹部内に位置決めされて接続され、前記バンプと接続端子との接続が前記封止樹脂で保持された構造としたことを特徴とする。 The concave portion of the connection terminal can be formed by etching.
The semiconductor device of the present invention has a semiconductor element having bumps formed on a plurality of electrode terminals, and a plurality of connection terminals to which the plurality of bumps of the semiconductor element are respectively connected. A wiring board in which a recess having an inclined surface inclined obliquely downwardly from the opening end is formed, and a sealing resin that seals a gap between the semiconductor element and the wiring board. It is characterized in that the front end of the bump is positioned and connected in the recess of each connection terminal of the wiring board, and the connection between the bump and the connection terminal is held by the sealing resin.

接続端子の凹部はエッチングによって形成することができる。
封止樹脂は半導体素子と配線基板との間に配置された熱硬化性樹脂フィルムの熱硬化物であってよい。 The concave portion of the connection terminal can be formed by etching.
The sealing resin may be a thermosetting product of a thermosetting resin film disposed between the semiconductor element and the wiring board.

上記した配線基板によれば、半導体装置を構成する際に、マウントする半導体素子の電極端子上のバンプの先端部を配線基板の接続端子の凹部内へと傾斜面にて案内して位置決めすることができる。よって、半導体素子と配線基板との位置合わせ精度を従来よりも緩和しながら、バンプを接続端子に対して位置精度よく位置決めすることができる。バンプの接続端子への接触面積も従来の平坦な接続端子に対するよりも大きくなるため、接続信頼性が向上する。   According to the wiring board described above, when the semiconductor device is configured, the tip of the bump on the electrode terminal of the semiconductor element to be mounted is guided and positioned on the inclined surface into the recess of the connection terminal of the wiring board. Can do. Therefore, it is possible to position the bump with respect to the connection terminal with high positional accuracy while relaxing the alignment accuracy between the semiconductor element and the wiring board as compared with the conventional case. Since the contact area of the bump to the connection terminal is larger than that of the conventional flat connection terminal, the connection reliability is improved.

本発明の配線基板は、接続端子のバンプ対向位置に凹部を設けたことにより、半導体素子のマウント時にバンプの先端部を接続端子の凹部内に案内するセルフアライメント効果を奏することができる。よって、半導体素子と配線基板との位置合わせ精度を従来よりも緩和し、フリップチップ実装におけるスループットを向上できる。またバンプと接続端子との接続位置精度および接続信頼性を向上させることができ、それにより、ファインピッチ化された半導体素子および配線基板を用いて構成する半導体装置においても、電気的ショートや未接続などの不具合を防止することができ、フリップチップ実装における歩留りを向上できる。   The wiring board according to the present invention can provide a self-alignment effect that guides the tip of the bump into the recess of the connection terminal when the semiconductor element is mounted by providing the recess at the bump facing position of the connection terminal. Therefore, the alignment accuracy between the semiconductor element and the wiring board can be relaxed as compared with the conventional case, and the throughput in flip chip mounting can be improved. In addition, it is possible to improve the connection position accuracy and connection reliability between the bumps and the connection terminals, so that even in semiconductor devices configured using fine pitch semiconductor elements and wiring boards, electrical shorts and unconnected Can be prevented, and the yield in flip chip mounting can be improved.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。
図１は本発明の第１の実施形態における配線基板の平面図であり、図２は同配線基板を用いた本発明の半導体装置であって、チップサイズパッケージと呼ばれるパッケージ半導体装置の断面図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view of a wiring board according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a package semiconductor device called a chip size package, which is a semiconductor device of the present invention using the wiring board. is there.

図２に示す半導体装置において、配線基板１上に半導体素子２がフリップチップ方式で接合されており、配線基板１と半導体素子２との間隙および半導体素子２の周囲は封止樹脂３で封止され、配線基板１の下面にはボール状の外部接続端子４が格子状に配列されている。   In the semiconductor device shown in FIG. 2, a semiconductor element 2 is bonded to the wiring board 1 by a flip chip method, and the gap between the wiring board 1 and the semiconductor element 2 and the periphery of the semiconductor element 2 are sealed with a sealing resin 3. In addition, ball-like external connection terminals 4 are arranged in a lattice pattern on the lower surface of the wiring board 1.

半導体素子２には、その一側面の周縁部に周方向に沿って複数の電極端子５が配列され、各電極端子５上にワイヤボンディング技術を利用して二段突起状のバンプ６が形成されている。
配線基板１の上面には、半導体素子２の複数の電極端子５とバンプ６を介して電気的導通をとるための複数の接続端子７が形成されている。各接続端子７は一定の厚みで平坦な形状をしており、図１にも示すように、矩形の半導体素子２の搭載領域８内で半導体素子２の各電極端子５，バンプ６に対向可能に配列されて、搭載領域８の内側から外側にわたって延びている。
各接続端子７におけるバンプ対向位置には凹部９が形成されている。各凹部９は、開口端から斜め下向きに傾斜した傾斜面を持つように、またバンプ６の先端部を内部に収容可能な大きさを持つように形成される。たとえば凹部９は、図３（図１におけるＡ−Ａ´断面）に示すように、接続端子７の長手方向に沿う断面が逆三角形をなす三角柱形状に窪んで形成され、２つの傾斜面９ａを内側面として有する。
たとえば接続端子７が幅（長手方向の寸法）２０〜４０μｍ、厚み１０〜２０μｍに形成され、バンプ径が４０〜６０μｍである場合、凹部９は幅１０〜３０μｍに形成される。かかる凹部９は、接続端子７の全体を平坦に形成した後にエッチング技術を用いて形成するのが好都合である。これにより接合面積が増え、信頼性が向上する。凹部９を含めた接続端子７の表面はＡｕなどの貴金属からなるメッキ膜で覆っておくのが望ましい。 In the semiconductor element 2, a plurality of electrode terminals 5 are arranged along the circumferential direction on the peripheral edge of one side surface, and bumps 6 having a two-stage protrusion are formed on each electrode terminal 5 by using a wire bonding technique. ing.
On the upper surface of the wiring substrate 1, a plurality of connection terminals 7 are formed for electrical continuity through a plurality of electrode terminals 5 and bumps 6 of the semiconductor element 2. Each connection terminal 7 is flat with a constant thickness, and can be opposed to each electrode terminal 5 and bump 6 of the semiconductor element 2 within the mounting region 8 of the rectangular semiconductor element 2 as shown in FIG. And extends from the inside to the outside of the mounting area 8.
A concave portion 9 is formed at the bump facing position in each connection terminal 7. Each recess 9 is formed so as to have an inclined surface inclined obliquely downward from the opening end, and to have a size capable of accommodating the tip of the bump 6 therein. For example, as shown in FIG. 3 (AA ′ cross section in FIG. 1), the concave portion 9 is formed such that a cross section along the longitudinal direction of the connection terminal 7 is recessed in a triangular prism shape forming an inverted triangle, and two inclined surfaces 9a are formed. Has as an inner surface.
For example, when the connection terminal 7 is formed with a width (dimension in the longitudinal direction) of 20 to 40 μm and a thickness of 10 to 20 μm, and the bump diameter is 40 to 60 μm, the recess 9 is formed with a width of 10 to 30 μm. Such a recess 9 is conveniently formed using an etching technique after the entire connection terminal 7 is formed flat. This increases the bonding area and improves the reliability. The surface of the connection terminal 7 including the recess 9 is preferably covered with a plating film made of a noble metal such as Au.

上記半導体装置を製造するフリップチップ実装工程を図４を参照しながら説明する。
まず、図４（ａ）に示すように、配線基板１を図示しない加熱ステージ上に設置する。
次に、図４（ｂ）に示すように、配線基板１の半導体素子搭載領域８に熱硬化性を有する絶縁性樹脂フィルム３ａを配置する。この絶縁性樹脂フィルム３ａは上述した封止樹脂３となるものであるが、絶縁性樹脂フィルム３ａに代えて柔らかな熱硬化性樹脂ペーストを所定量塗布してもよい。 A flip chip mounting process for manufacturing the semiconductor device will be described with reference to FIG.
First, as shown to Fig.4 (a), the wiring board 1 is installed on the heating stage which is not shown in figure.
Next, as shown in FIG. 4B, a thermosetting insulating resin film 3 a is disposed in the semiconductor element mounting region 8 of the wiring board 1. Although this insulating resin film 3a becomes the sealing resin 3 described above, a predetermined amount of a soft thermosetting resin paste may be applied instead of the insulating resin film 3a.

次に、図４（ｃ）に示すように、半導体素子２をフェイスダウンにして絶縁性フィルム３ａ上に載せる。その際には、半導体素子２の各電極端子５上のバンプ６の先端部が配線基板１の各接続端子７の凹部９の上方に位置するように、半導体素子２と配線基板１とをそれぞれに予め付した目印（マーク）などを利用して位置合わせする。   Next, as shown in FIG. 4C, the semiconductor element 2 is placed face down and placed on the insulating film 3a. At that time, the semiconductor element 2 and the wiring board 1 are respectively placed so that the tip ends of the bumps 6 on the electrode terminals 5 of the semiconductor element 2 are located above the recesses 9 of the connection terminals 7 of the wiring board 1. The position is aligned using a mark or the like previously attached to.

次に、図４（ｄ）に示すように、半導体素子２の背面から図示しない加熱ブロックなどによって所定の熱および荷重を加えることにより、加熱ステージ上の配線基板１に半導体素子２をフリップチップ接合させる。
その際に、半導体素子２のバンプ６が絶縁性樹脂フィルム３ａの溶融物を押し退けながら配線基板１上の接続端子７に向かい、半田などの金属的接合とは異なって接続端子７と機械的に接触して変形しながら圧着し、この機械的な接触状態が、絶縁性樹脂フィルム３ａが熱硬化する際の収縮力によって保持される。 Next, as shown in FIG. 4 (d), the semiconductor element 2 is flip-chip bonded to the wiring substrate 1 on the heating stage by applying predetermined heat and load from the back surface of the semiconductor element 2 with a heating block (not shown). Let
At that time, the bump 6 of the semiconductor element 2 moves toward the connection terminal 7 on the wiring board 1 while pushing away the melt of the insulating resin film 3a, and mechanically connects with the connection terminal 7 unlike metal bonding such as solder. The mechanical contact state is maintained by the contraction force when the insulating resin film 3a is thermally cured.

詳細には、図５（ａ）に示すように、半導体素子２のバンプ６の先端部が凹部９内に入り込み、続いて凹部９の傾斜面９ａで案内されて徐々に底部側へと進入し、最終的に図５（ｂ）に示すように完全に凹部９内に嵌入する。つまりバンプ６は、凹部３によって位置矯正され、凹部３と同軸上に精度よく位置決めされる。逆に凹部３は、バンプ６を凹部３内へ案内するセルフアライメントと、バンプ６と接続端子７との接続位置の高精度化とに機能する。
よって、半導体素子２と配線基板１との位置合わせ精度を従来よりも緩和しても、接続位置精度および接続信頼性を確保することができ、フリップチップ実装におけるスループットを向上できるとともに、ファインピッチ化された半導体素子２と配線基板１とを用いる場合も、電気的ショートや未接続などの不具合を防止することができ、ＦＣＢ（フリップチップボンディング）実装における歩留りを向上できる。
なお、上記した三角柱形状の凹部９に代えて、図６に示すように、断面が台形をなす四角柱形状にて窪んだ凹部１０を接続端子７に形成して配線基板１を構成してもよい。この四角柱形状の凹部１０は幅が例えば２０μｍ程度となるようにエッチングすることで形成される。
この配線基板１でも、熱圧着時に、図７（ａ）に示すように、半導体素子２のバンプ６の先端部が凹部１０内に入り込み、続いて凹部１０の傾斜面１０ａで案内されて徐々に底部側へと進入し、最終的に図７（ｂ）に示すように完全に凹部１０内に嵌入する結果、バンプ６が凹部１０と同軸上に精度よく位置決めされる。 Specifically, as shown in FIG. 5 (a), the tip of the bump 6 of the semiconductor element 2 enters the recess 9, and is then guided by the inclined surface 9a of the recess 9 and gradually enters the bottom. Finally, as shown in FIG. 5B, it is completely inserted into the recess 9. That is, the position of the bump 6 is corrected by the recess 3 and is positioned on the same axis as the recess 3 with high accuracy. On the contrary, the concave portion 3 functions for self-alignment for guiding the bump 6 into the concave portion 3 and for increasing the accuracy of the connection position between the bump 6 and the connection terminal 7.
Therefore, even if the alignment accuracy between the semiconductor element 2 and the wiring board 1 is relaxed as compared with the conventional case, the connection position accuracy and the connection reliability can be ensured, the throughput in flip chip mounting can be improved, and the fine pitch can be increased. Even when the semiconductor element 2 and the wiring substrate 1 are used, it is possible to prevent problems such as electrical shorts and unconnection, and to improve the yield in FCB (flip chip bonding) mounting.
In place of the triangular prism-shaped recess 9 described above, the wiring board 1 may be configured by forming the recess 10 in the connection terminal 7 as shown in FIG. Good. The rectangular columnar recess 10 is formed by etching so that the width becomes, for example, about 20 μm.
Also in this wiring board 1, at the time of thermocompression bonding, as shown in FIG. 7A, the tip end portion of the bump 6 of the semiconductor element 2 enters the recess 10 and is then guided by the inclined surface 10a of the recess 10 and gradually. As a result of entering the bottom side and finally being completely inserted into the recess 10 as shown in FIG. 7B, the bump 6 is accurately positioned coaxially with the recess 10.

図８は複数の半導体素子を搭載した半導体装置の断面図である。
この半導体装置では、先に図２を用いて説明した半導体装置と同様に、配線基板１上に半導体素子２がフリップチップ方式で接合され、配線基板１と半導体素子２との間隙および半導体素子２の周囲が封止樹脂３で封止されている。 FIG. 8 is a cross-sectional view of a semiconductor device on which a plurality of semiconductor elements are mounted.
In this semiconductor device, similarly to the semiconductor device described above with reference to FIG. 2, the semiconductor element 2 is joined on the wiring substrate 1 by the flip chip method, and the gap between the wiring substrate 1 and the semiconductor element 2 and the semiconductor element 2. Is sealed with a sealing resin 3.

そしてさらに、半導体素子２の上に第２の半導体素子１１が積層され、この第２の半導体素子１１の電極端子１２がボンディングワイヤー１３によって配線基板１上に形成された第２の接続端子１４と接続され、配線基板１上の半導体素子２と第２の半導体素子１１とボンディングワイヤー１３などの接続部の全体を保護するように第２の封止樹脂１５で覆われている。   Further, the second semiconductor element 11 is laminated on the semiconductor element 2, and the electrode terminal 12 of the second semiconductor element 11 is connected to the second connection terminal 14 formed on the wiring substrate 1 by the bonding wire 13. It is connected and covered with a second sealing resin 15 so as to protect the entire connection portion such as the semiconductor element 2, the second semiconductor element 11, and the bonding wire 13 on the wiring substrate 1.

このような半導体装置でも、配線基板１の接続端子７の凹部３が、バンプ６を凹部３内へ案内するセルフアライメントと、バンプ６と接続端子７との接続位置の高精度化の機能を担う。   Even in such a semiconductor device, the concave portion 3 of the connection terminal 7 of the wiring board 1 has a function of self-alignment for guiding the bump 6 into the concave portion 3 and a high accuracy of the connection position of the bump 6 and the connection terminal 7. .

本発明の配線基板は、半導体素子をフリップチップ方式で接合させるのに有用であり、特に、ファインピッチ化された半導体素子を用いて半導体装置を構成するのに有用である。   The wiring board of the present invention is useful for bonding semiconductor elements by a flip-chip method, and is particularly useful for configuring a semiconductor device using a fine pitch semiconductor element.

本発明の一実施形態における配線基板の平面図The top view of the wiring board in one embodiment of the present invention 図１の配線基板を用いた半導体装置の断面図Sectional drawing of the semiconductor device using the wiring board of FIG. 図１の配線基板の接続端子を示す拡大断面図FIG. 1 is an enlarged sectional view showing connection terminals of the wiring board of FIG. 図２の半導体装置を製造するフリップチップ実装工程を説明する工程断面図Process sectional drawing explaining the flip chip mounting process which manufactures the semiconductor device of FIG. 図２の半導体装置のフリップチップ接合部の（ａ）熱圧着時および（ｂ）接合終了時の拡大断面図2A is an enlarged cross-sectional view of the flip chip bonding portion of the semiconductor device of FIG. 本発明の他の実施形態における配線基板の接続端子を示す拡大断面図The expanded sectional view which shows the connection terminal of the wiring board in other embodiment of this invention 図６の配線基板を用いた本発明の半導体装置のフリップチップ接合部の（ａ）熱圧着時および（ｂ）接合終了時の拡大断面図6A is an enlarged cross-sectional view of a flip chip bonding portion of the semiconductor device of the present invention using the wiring board of FIG. 6 at the time of (a) thermocompression bonding and (b) at the end of bonding. 本発明のさらに他の実施形態における配線基板を用いた半導体装置の断面図Sectional drawing of the semiconductor device using the wiring board in other embodiment of this invention. 従来の半導体装置の断面図Sectional view of a conventional semiconductor device 図９の半導体装置に用いられた配線基板の平面図FIG. 9 is a plan view of a wiring board used in the semiconductor device of FIG. 図９の半導体装置のフリップチップ接合部の拡大断面図FIG. 9 is an enlarged cross-sectional view of a flip chip bonding portion of the semiconductor device of FIG.

符号の説明Explanation of symbols

１・・・配線基板
２・・・半導体素子
３・・・封止樹脂
3a・・・絶縁性樹脂フィルム
５・・・電極端子
６・・・バンプ
７・・・接続端子
９・・・凹部
9a・・・傾斜面
10・・・凹部
10a ・・傾斜面
11・・・第２の半導体素子
14・・・第２の接続端子 DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Semiconductor element 3 ... Sealing resin
3a ... Insulating resin film 5 ... Electrode terminal 6 ... Bump 7 ... Connection terminal 9 ... Recess
9a ・ ・ ・ Inclined surface
10 ... Recess
10a ..Inclined surface
11 ... Second semiconductor element
14 ... Second connection terminal

Claims (5)

半導体素子をフリップチップ実装する配線基板であって、
前記半導体素子の複数の電極端子上に形成されたバンプがそれぞれ接続される複数の接続端子を有し、各接続端子のバンプ対向位置に開口端から斜め下向きに内側へ傾斜した傾斜面を持った凹部が形成された配線基板。 A wiring board for flip-chip mounting a semiconductor element,
Bumps formed on a plurality of electrode terminals of the semiconductor element each have a plurality of connection terminals to be connected, and each connection terminal has an inclined surface inclined inwardly downward from the opening end at a bump facing position of each connection terminal. A wiring board having a recess. 接続端子の凹部がエッチングによって形成された請求項１記載の配線基板。   The wiring board according to claim 1, wherein the concave portion of the connection terminal is formed by etching. 複数の電極端子上にバンプが形成された半導体素子と、
前記半導体素子の複数のバンプがそれぞれ接続される複数の接続端子を有し、各接続端子のバンプ対向位置に開口端から斜め下向きに内側へ傾斜した傾斜面を持った凹部が形成された配線基板と、
前記半導体素子と配線基板との間隙を封止した封止樹脂とを備え、
前記半導体素子の各バンプの先端部が前記配線基板の各接続端子の凹部内に位置決めされて接続され、前記バンプと接続端子との接続が前記封止樹脂で保持された
半導体装置。 A semiconductor element having bumps formed on a plurality of electrode terminals;
A wiring board having a plurality of connection terminals to which a plurality of bumps of the semiconductor element are respectively connected, and a recess having an inclined surface inclined obliquely inwardly downward from an opening end at a bump facing position of each connection terminal When,
A sealing resin that seals a gap between the semiconductor element and the wiring board;
A semiconductor device in which a tip portion of each bump of the semiconductor element is positioned and connected in a recess of each connection terminal of the wiring board, and the connection between the bump and the connection terminal is held by the sealing resin. 接続端子の凹部がエッチングによって形成された請求項３記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the recess of the connection terminal is formed by etching. 封止樹脂が半導体素子と配線基板との間に配置された熱硬化性樹脂フィルムの熱硬化物である請求項３または請求項４のいずれかに記載の半導体装置。   The semiconductor device according to claim 3, wherein the sealing resin is a thermoset of a thermosetting resin film disposed between the semiconductor element and the wiring board.
JP2004173276A 2004-06-11 2004-06-11 Wiring board and semiconductor device using the same Withdrawn JP2005353854A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173738A (en) * 2005-12-26 2007-07-05 Fuji Xerox Co Ltd Wiring board and flip-chip mounting structure
JP2008021751A (en) * 2006-07-11 2008-01-31 National Institute Of Advanced Industrial & Technology Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method
JP2008270639A (en) * 2007-04-24 2008-11-06 Toppan Forms Co Ltd Conductive connection structure, and method of manufacturing the same
JP2011077345A (en) * 2009-09-30 2011-04-14 Sanyo Electric Co Ltd Device mounting board, semiconductor module and portable apparatus
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
CN112151665A (en) * 2019-06-27 2020-12-29 成都辰显光电有限公司 Micro light-emitting diode device and preparation method thereof, display panel and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173738A (en) * 2005-12-26 2007-07-05 Fuji Xerox Co Ltd Wiring board and flip-chip mounting structure
JP2008021751A (en) * 2006-07-11 2008-01-31 National Institute Of Advanced Industrial & Technology Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method
JP2008270639A (en) * 2007-04-24 2008-11-06 Toppan Forms Co Ltd Conductive connection structure, and method of manufacturing the same
JP2011077345A (en) * 2009-09-30 2011-04-14 Sanyo Electric Co Ltd Device mounting board, semiconductor module and portable apparatus
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
CN112151665A (en) * 2019-06-27 2020-12-29 成都辰显光电有限公司 Micro light-emitting diode device and preparation method thereof, display panel and manufacturing method thereof
CN112151665B (en) * 2019-06-27 2022-03-08 成都辰显光电有限公司 Micro light-emitting diode device and preparation method thereof, display panel and manufacturing method thereof

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