JP2001035886A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2001035886A JP2001035886A JP20833099A JP20833099A JP2001035886A JP 2001035886 A JP2001035886 A JP 2001035886A JP 20833099 A JP20833099 A JP 20833099A JP 20833099 A JP20833099 A JP 20833099A JP 2001035886 A JP2001035886 A JP 2001035886A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring pattern
- substrate
- semiconductor element
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、より詳細には、特にフレキシブル基
板に半導体素子を、フェースダウンボンディング法で、
しかも、従来のようにバンプを要せずに形成されて、形
成時の残留熱ストレス（歪み）が著しく低減され、信頼
性を向上させる半導体装置及びその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device on a flexible substrate by a face-down bonding method.
In addition, the present invention relates to a semiconductor device which is formed without the need for a bump as in the prior art, has significantly reduced residual thermal stress (strain) during formation, and has improved reliability, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来から、半導体集積回路等の半導体チ
ップをパアッケージ又は配線上に組み込むに際して、半
導体チップをフェースダウンさせる、すなわち、下向き
にして電極部との接続を、ワイヤでなく、基板上に配
す、特に面状の配線パターン面との面接続で行うフェー
スダウンボンディング法が一般的に用いられている。2. Description of the Related Art Conventionally, when a semiconductor chip such as a semiconductor integrated circuit is mounted on a package or a wiring, the semiconductor chip is face-down, that is, the semiconductor chip is faced down, and the connection with an electrode portion is formed on a substrate instead of a wire. A face-down bonding method of arranging, in particular, performing surface connection with a planar wiring pattern surface is generally used.
【０００３】このボンディングは、ワイヤボンディング
で行うフェースアップボンディング法に比べて、接続後
の機械的強度が強く、接続回数も１回で済むことから、
種々の観点から有益な半導体装置の製造方法である。[0003] This bonding has a higher mechanical strength after connection and requires only one connection, as compared with the face-up bonding method performed by wire bonding.
This is a method for manufacturing a semiconductor device that is useful from various viewpoints.
【０００４】そこで、この種の半導体装置では、特開平
８−２７９５７１号に開示されているように半導体素子
と基板とをバンプを介して接続することが重要な要素の
一つとなっている。Therefore, in this type of semiconductor device, it is one of the important elements to connect a semiconductor element and a substrate via a bump as disclosed in Japanese Patent Application Laid-Open No. 8-279571.
【０００５】この目的のために、通常、あらかじめ半導
体素子の電極上にメッキ法やボールボンディング法によ
ってバンプを形成し、そのバンプを介して基板と半導体
素子とを接続するという手法が採用されている。[0005] For this purpose, a method is usually adopted in which bumps are formed on electrodes of a semiconductor element in advance by plating or ball bonding, and the substrate and the semiconductor element are connected via the bumps. .
【０００６】しかしながら、この手法では、バンプを介
して２種類の異なる熱膨張係数を有する材料、すなわち
半導体素子と基板とを接続する構造となるので、半導体
装置と基板とを組立てる際にかかる熱によって生じる熱
応力は、バンプとそれぞれの接続部界面に集中すること
となる。However, in this method, since a material having two kinds of different thermal expansion coefficients via bumps, that is, a structure for connecting a semiconductor element and a substrate is used, heat generated when assembling the semiconductor device and the substrate is obtained. The generated thermal stress is concentrated on the interface between the bump and each connection portion.
【０００７】このため、熱応力による破壊を防ぐために
半導体素子と基板との間に樹脂を封入することが一般的
である。樹脂を封入して熱応力を低減させたとしても強
固に接続されたバンプ部には熱応力がかかり接続部を破
壊から防ぐことに、十分に対応できるものいではない。For this reason, it is common to seal a resin between the semiconductor element and the substrate in order to prevent destruction due to thermal stress. Even if the thermal stress is reduced by encapsulating the resin, it is not sufficient to prevent the strongly connected bump portion from being damaged by the thermal stress applied to the connected portion.
【０００８】そこで、例えば特願平７−１９１７３７号
には、半導体素子の電極上に形成されたバンプと基板と
を、その間に封入された樹脂の硬化時の収縮力を利用し
て接触により接続を行う方法が記載されている。Therefore, for example, Japanese Patent Application No. 7-191737 discloses that a bump formed on an electrode of a semiconductor element and a substrate are connected by contact using a contraction force at the time of curing of a resin sealed therebetween. Are described.
【０００９】この方法では、半導体素子と基板とを強固
に接合させないことから、熱応力によるバンプ接続部の
破壊に対しては、一応、解消できる傾向にある。According to this method, since the semiconductor element and the substrate are not firmly joined, there is a tendency that breakage of the bump connection portion due to thermal stress can be temporarily eliminated.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、半導体
素子の電極上に形成されたバンプと基板とを樹脂の硬化
収縮力によって接続する方法において、従来は、バンプ
を設けてボールボンディング法により、電極を接続させ
るに際して、新たに形成するバンプの電極と半導体素子
との界面に、熱的及び機械的ストレスを与えることにな
り、その界面が破壊される問題を起こす傾向にあった。However, in a method of connecting a bump formed on an electrode of a semiconductor element to a substrate by a curing shrinkage force of a resin, conventionally, a bump is provided and the electrode is formed by a ball bonding method. At the time of connection, thermal and mechanical stress is applied to the interface between the electrode of the newly formed bump and the semiconductor element, and the interface tends to be broken.
【００１１】これは、近年、半導体素子の高集積化に伴
い、素子間の配線幅が、著しく狭く微細化されており、
このような微細化形成により、形成される配線膜も薄く
なり、結果的に形成される配線の膜厚も薄膜になること
から、ボールボンディングする際の熱及び機械的なスト
レスが、直接、電極と半導体素子の界面に及ぼすことに
なるのである。In recent years, the wiring width between elements has been extremely narrow and miniaturized with the recent increase in the degree of integration of semiconductor elements.
By such a miniaturization formation, the formed wiring film becomes thinner, and as a result, the thickness of the formed wiring becomes thinner, so that heat and mechanical stress at the time of ball bonding are directly applied to the electrode. And the interface of the semiconductor element.
【００１２】これらの対策として、半導体素子の拡散工
程を追加して電極部の膜厚を厚くすることは可能である
が、半導体素子の製造コストを高めることになる。As a countermeasure against this, it is possible to increase the film thickness of the electrode portion by adding a diffusion step of the semiconductor element, but this increases the manufacturing cost of the semiconductor element.
【００１３】しかも、近年のように、更なる高集積化が
進んだ半導体素子へ対処するには、半導体素子の小面積
化に伴い、半導体素子上に形成される電極のサイズも更
に縮小されるためからバンプを形成するには、微小ボー
ルを形成しボンディングしなければならないという問題
を発生する。In addition, in order to cope with a semiconductor element with higher integration as in recent years, the size of an electrode formed on the semiconductor element is further reduced as the area of the semiconductor element is reduced. Therefore, in order to form a bump, there arises a problem that a minute ball must be formed and bonded.
【００１４】そこで、本発明の目的は、フェースダウン
ボンディング法による半導体装置であって、半導体素子
とフレキシブル基板とを接続する部位にかかる熱応力を
極力低減させることができ、高い信頼性を有する半導体
装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device using a face-down bonding method, in which a thermal stress applied to a portion connecting a semiconductor element and a flexible substrate can be reduced as much as possible, and the semiconductor device has high reliability. It is to provide a device.
【００１５】また、本発明の他の目的として、半導体素
子上の電極にバンプを形成させずに電極を強固に密着接
続をさせることができ、しかも、電極の狭ピッチ化の対
応可能な半導体装置の製造方法を提供することにある。Another object of the present invention is to provide a semiconductor device capable of firmly and closely connecting electrodes without forming bumps on the electrodes on the semiconductor element and capable of coping with the narrow pitch of the electrodes. It is to provide a manufacturing method of.
【００１６】[0016]
【課題を解決する手段】そこで、本発明者らは、上記課
題を鑑みて、鋭意検討した結果、従来のように特にバン
プを設けることなく、フレキシブル基板上にフェースダ
ウンボンディング法で、半導体素子と配線パターンとを
密着接続できる方法を見出して、本発明を完成させるに
至った。Means for Solving the Problems In view of the above problems, the present inventors have conducted intensive studies. As a result, the present invention has succeeded in forming a semiconductor element by a face-down bonding method on a flexible substrate without providing a bump as in the prior art. The present inventor has found a method capable of tightly connecting to a wiring pattern, and has completed the present invention.
【００１７】すなわち、本発明は、両端下部に電極端子
を配する半導体素子を、フレキシブル基板上にフェース
ダウンボンディング法で、形成される半導体装置におい
て、前記フレキシブル基板上に所定の間隔で、互いに対
向して配線パターンを配し、互いに対向する側の端部か
ら所定の部位に所定幅で凹部の溝パターンを設けている
ことを特徴とする。That is, according to the present invention, in a semiconductor device formed by face-down bonding on a flexible substrate with electrode terminals disposed at both lower ends, a semiconductor device is opposed to the flexible substrate at a predetermined interval. And a groove pattern of a concave portion having a predetermined width is provided at a predetermined portion from an end on the side facing each other.
【００１８】このように配線パターン上に凹部の溝パタ
ーンを設けるにより、対向して配するこの前記配線パタ
ーンの対向側の端部は、従来のダンプに相当し、同様の
役割果たす、あたかも凸部面を形成したことになる。By providing the groove pattern of the concave portion on the wiring pattern in this manner, the opposite end of the wiring pattern disposed oppositely corresponds to a conventional dump, and has the same role as a convex portion. This means that a surface has been formed.
【００１９】これにより、前記半導体素子と前記フレキ
シブル基板とが、前記基板上に対向して配す前記配線パ
ターンの間に施す樹脂封止材を介して、前記両電極端子
の面と前記各配線パターンの端部の面とを、容易に面合
わせするように密着接触される。Thus, the surface of the two electrode terminals and each of the wirings are provided between the semiconductor element and the flexible substrate via a resin sealing material provided between the wiring patterns disposed on the substrate so as to face each other. The pattern is brought into close contact with the end face of the pattern so as to easily meet.
【００２０】更に、前記半導体素子の両側が、前記配線
パターンに設ける凹部の溝に埋め込まれてなる樹脂法面
でカバーされて、絶縁性とその側面保護をすることを特
徴とする半導体装置を提供する。Further, a semiconductor device is provided in which both sides of the semiconductor element are covered with a resin slope embedded in a groove of a concave portion provided in the wiring pattern to provide insulation and side protection. I do.
【００２１】また、本発明は、このような半導体装置を
形成させる製造方法として、すなわち、前記フレキシブ
ル基板上に、所定の間隔で互いに対向する配線パターン
を形成し、且つこれらの前記配線パターンには、予め前
記基板上で互いに対向する側の端部から所定幅の部位に
凹部の溝パターンを形成する。The present invention also provides a manufacturing method for forming such a semiconductor device, that is, forming wiring patterns facing each other at a predetermined interval on the flexible substrate, and forming the wiring patterns on the flexible substrate. First, a groove pattern of a concave portion is formed in a portion having a predetermined width from an end on the side facing each other on the substrate.
【００２２】次いで、前記基板上の前記配線パターンに
よる間に、液状の樹脂封止材を垂らした後、半導体素子
の両端下部に配する電極端子の面を、前記配線パターン
の互いに対向する側の端部面に面合わせ接触させて、上
部からの加圧下に加熱させて第１次の接触固定をさせ
る。Next, after a liquid resin encapsulant is dropped between the wiring patterns on the substrate, the surfaces of the electrode terminals disposed at the lower ends of both ends of the semiconductor element are brought into contact with the opposite side of the wiring pattern. The end surfaces are brought into face-to-face contact, and heated under pressure from above to perform primary contact fixing.
【００２３】次いで、前記配線パターン上の凹部の溝パ
ターンに、前記液状の樹脂封止材を垂らして、毛細管現
象を介して、前記第１次の接触固定時に生ずる隙間に封
入させ、加熱下に第２次の接触固定をさせる。ここで、
この樹脂の熱硬化時の収縮力により、前記電極端子面と
前記配線パターンの両端部の面とを、強固に密着接続さ
せることを特徴とする半導体装置の製造方法を提供す
る。Next, the liquid resin encapsulant is dropped on the groove pattern of the concave portion on the wiring pattern, and sealed in the gap generated at the time of the first contact fixing through a capillary phenomenon, and then heated. The second contact fixing is performed. here,
A method for manufacturing a semiconductor device, characterized in that the electrode terminal surface and both end surfaces of the wiring pattern are firmly and closely connected to each other by a shrinkage force of the resin at the time of thermosetting.
【００２４】これにより、本発明による半導体装置は、
半導体素子とフレキシブル基板と封止樹脂とから構成さ
れ、基板上の配線パターンが半導体素子上の電極端子面
だけに、フェースダウン方式で接触させることが可能
な、パターン処理を介してなる構造になる。As a result, the semiconductor device according to the present invention
It is composed of a semiconductor element, a flexible substrate, and a sealing resin. The wiring pattern on the substrate can be brought into contact with only the electrode terminal surface on the semiconductor element in a face-down manner. .
【００２５】このように、基板上に配する配線上にエッ
チング処理による凹部の溝パターンを形成することで、
この凹部内側の端部は、従来のバンプに相当する、前記
半導体素子の電極端子だけを接触させられる凸部になる
のである。As described above, by forming the groove pattern of the concave portion by the etching process on the wiring arranged on the substrate,
The end inside the recess becomes a projection corresponding to a conventional bump, which can be brought into contact with only the electrode terminal of the semiconductor element.
【００２６】また、このような凹部の溝パターンを介す
ることで、前記配線パターンが、前記電極端子の面以
外、半導体素子との接触がなくなり、電気的にショート
不良を発生させない効果をもたらしている。Further, through the groove pattern of the concave portion, the wiring pattern does not come into contact with the semiconductor element other than the surface of the electrode terminal, thereby providing an effect of preventing an electrical short circuit from occurring. .
【００２７】従って、本発明の半導体装置及びその製造
方法においては、半導体素子と基板とを接続するための
従来のようなバンプを形成させる必要がないことから、
狭ピッチな電極にも容易に接続させることが可能で、ま
た、電極端子と配線パターンとの接続は封止樹脂の熱硬
化時の収縮力による、密着接触であるため接続部には、
従来のようなストレスがかかり難く、高い信頼性を有す
る半導体装置及びその製造方法である。Therefore, in the semiconductor device and the method of manufacturing the same according to the present invention, it is not necessary to form a bump for connecting a semiconductor element and a substrate as in the prior art.
It is possible to easily connect to narrow pitch electrodes, and because the connection between the electrode terminals and the wiring pattern is in close contact due to the contraction force during thermosetting of the sealing resin, the connection part has
A semiconductor device and a method for manufacturing the same, which are less likely to receive stress as in the related art and have high reliability.
【００２８】[0028]
【発明の実施の形態】以下に、図１〜図３を参照して、
本発明によるフェースダウンボンディング法による半導
体装置及びその製造方法の実施の形態を更に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
Embodiments of a semiconductor device by a face-down bonding method and a method of manufacturing the same according to the present invention will be further described.
【００２９】そこで、図１に示す、本発明による半導体
装置の概念断面図において、フレキシブル基板２上の配
線３は、この基板上に互いに対向するように設けられて
いる。また、この配線パターンには、パターンエッチン
グにより凹部４ａの溝パターンが、この配線パターンの
互いに対向する両側端部から所定の近傍部位に、所定幅
で設けられている。この凹部４ａの溝パターンにより、
図１から明らかなように、凹部４ａの互いに対向する方
向先端部位が、結果的に突起するような凸部面５なる構
造になる。Therefore, in the conceptual sectional view of the semiconductor device according to the present invention shown in FIG. 1, the wirings 3 on the flexible substrate 2 are provided on the substrate so as to face each other. Further, in this wiring pattern, a groove pattern of the concave portion 4a is provided with a predetermined width at a predetermined nearby portion from both side ends of the wiring pattern facing each other by pattern etching. By the groove pattern of the concave portion 4a,
As is clear from FIG. 1, the distal end portions of the concave portions 4 a in the opposing directions have a structure in which the convex surface 5 is projected as a result.
【００３０】そこで、本発明において、半導体素子１上
に形成され電極端子６は、フェースダウンボンディング
法においては、この凸部面５と半導体素子の電極端子６
とは、特別な面合わせを要せずに封止樹脂８の熱硬化時
の収縮力により適宜に密着接触させることができる。Therefore, in the present invention, in the face-down bonding method, the electrode terminal 6 formed on the semiconductor element 1 is connected to the convex surface 5 and the electrode terminal 6 of the semiconductor element.
In this case, the sealing resin 8 can be brought into close contact with the sealing resin 8 by a shrinkage force at the time of thermosetting without special surface matching.
【００３１】また、本発明において、上述する如くの凸
部面５の面幅は、好ましくは、少なくとも前記電極端子
の幅に同等であればよい。また、この面は、上述する凹
部の溝パターンをパターンエッチングする時に、容易に
設定形成されるものである。In the present invention, the surface width of the convex surface 5 as described above is preferably at least equal to the width of the electrode terminal. This surface is easily set and formed when the above-described groove pattern of the concave portion is pattern-etched.
【００３２】また、本発明において、半導体装置が半田
ボールボンデイング型である場合に、図１に示す如く、
前記基板上に互いに対向して配している前記配線パター
ンの、一方の両端部近傍は、基板に設けるスルーホール
に埋め込まれる半田ボール７によって、接合されると共
に、配線パターン３をフレキシブル基板２に安定に固定
されることになる。In the present invention, when the semiconductor device is a solder ball bonding type, as shown in FIG.
The vicinity of one end of each of the wiring patterns disposed opposite to each other on the substrate is joined by solder balls 7 embedded in through holes provided in the substrate, and the wiring pattern 3 is attached to the flexible substrate 2. It will be fixed stably.
【００３３】また、本発明において、半導体装置がアウ
ターボンデイング型である場合には、図３に示す如く、
上述すると同様の前記配線パターン３の対向する端部の
一方の両端部が外部端子となり、この両外部端子にはア
ウターボンデイング１０を容易に設けることができるも
のである。In the present invention, when the semiconductor device is of an outer bonding type, as shown in FIG.
As described above, one end of one of the opposite ends of the wiring pattern 3 becomes an external terminal, and the outer bonding 10 can be easily provided on both external terminals.
【００３４】また、本発明においては、上述する如く半
導体素子を配線パターンを有する基板上に、封止樹脂８
で密着固定させた後、図１及び図３に示す如く、前記配
線パターンの両凹部の溝パターンには、絶縁樹脂であれ
ば特に限定されないが、少なくとも、上述する封止用樹
脂をこの凹部を埋めるように施して、更に前記半導体素
子の両側に法面を形成するように樹脂カバーをすること
が好適である。Further, in the present invention, as described above, the semiconductor element is formed on a substrate having a wiring pattern by encapsulating resin 8.
1 and FIG. 3, the groove pattern of the two concave portions of the wiring pattern is not particularly limited as long as it is an insulating resin. It is preferable that the resin cover is applied so as to fill the gap and that a slope is formed on both sides of the semiconductor element.
【００３５】以上のような、本発明による半導体装置を
製造する実施形態として、図２（ａ）〜（ｄ）に示す製
造工程図を参照すると、図２（ａ）において、例えば、
フレキシブル基板２として、ポリイミドフィルム等の高
耐熱性を有するフィルムをベースとしたフレキシブル基
板１を適宜好適に用いることができる。この基板の両端
部位にパターンエッチングによりスルーホール９を形成
する。ここで、このスルーホール９は、フレキシブル基
板１をレーザー加工、打ち抜き加工、エッチィング加工
等で、容易に穴を開けることができ、既に上述する半田
ボールボンデイング型の外部端子である半田ボール７が
埋め込まれる。As an embodiment for manufacturing a semiconductor device according to the present invention as described above, referring to the manufacturing process diagrams shown in FIGS. 2A to 2D, for example, in FIG.
As the flexible substrate 2, a flexible substrate 1 based on a film having high heat resistance such as a polyimide film can be suitably used as appropriate. Through holes 9 are formed at both ends of the substrate by pattern etching. Here, the through hole 9 can be easily formed by laser processing, punching processing, etching processing, or the like of the flexible substrate 1. Embedded.
【００３６】次いで、この基板上に所定の間隔で互いに
対向するパターンで配線パターン３（以下、単に配線と
記すこともある）を形成する。Next, wiring patterns 3 (hereinafter, sometimes simply referred to as wirings) are formed on the substrate in a pattern facing each other at predetermined intervals.
【００３７】すなわち、この配線パターン３は、予めフ
レキシブル基板２上に貼設された銅箔などの金属箔をパ
ターンエッチングするか、フレキシブル基板２上にレジ
ストを用いたアディティブメッキ法等で形成する方法を
挙げることができる。That is, the wiring pattern 3 is formed by pattern-etching a metal foil such as a copper foil that has been pasted on the flexible substrate 2 in advance, or by forming the wiring pattern 3 on the flexible substrate 2 by an additive plating method using a resist. Can be mentioned.
【００３８】また、この配線３の凹部４の溝パターン
は、ＴＡＢテープ等で用いられているメサエッチィング
法によって形成することができる。The groove pattern of the concave portion 4 of the wiring 3 can be formed by a mesa etching method used for a TAB tape or the like.
【００３９】次いで、図１（ａ）に示す如く、基板１上
の両配線３間に、少量の液状の封止樹脂８を垂らす。こ
の封止樹脂は、半導体素子１とフレキシブル基板２との
間隙を、半導体素子１及びその接続近傍を外的な環境雰
囲気との直接的な接触をなくして、保護するための封止
樹脂である。また、これらの樹脂として、絶縁性の熱硬
化性樹脂であれば、特に限定することなく使用される。Next, as shown in FIG. 1A, a small amount of liquid sealing resin 8 is dripped between the wirings 3 on the substrate 1. This sealing resin is a sealing resin for protecting the gap between the semiconductor element 1 and the flexible substrate 2 by eliminating direct contact between the semiconductor element 1 and the vicinity of the connection between the semiconductor element 1 and the external environment. . In addition, as these resins, any insulating thermosetting resin can be used without particular limitation.
【００４０】次いで、図１（ｂ）に示す如く、この封止
樹脂８は半導体素子１とフレキシブル基板２とを仮固定
（第１次の接触固化）させるもので、フレキシブル基板
２の所定の位置に半導体素子１を配して、圧力下に加熱
させて封止樹脂８を熱硬化させる。しかる後、図２
（ｃ）に示すように半導体素子１の両端に位置する凹部
４に樹脂液を垂らし、更に毛細管現象を利用して半導体
素子１とフレキシブル基板２と間に生じている間隙に封
入する。次いで、第１次の接触固化と同様にこの封止樹
脂８を熱硬化させることにより、第２次の接触固化がな
されて、図２（ｃ）に示すように封止固定される。Next, as shown in FIG. 1B, the sealing resin 8 temporarily fixes the semiconductor element 1 and the flexible substrate 2 (first contact solidification), and a predetermined position of the flexible substrate 2 Then, the semiconductor element 1 is disposed and heated under pressure to thermally cure the sealing resin 8. After a while, FIG.
As shown in (c), a resin liquid is dripped into the concave portions 4 located at both ends of the semiconductor element 1, and the resin liquid is filled in a gap formed between the semiconductor element 1 and the flexible substrate 2 by utilizing a capillary phenomenon. Next, similarly to the first contact solidification, the sealing resin 8 is thermally cured, so that the second contact solidification is performed and the sealing resin is sealed and fixed as shown in FIG.
【００４１】ここで、本発明においては、封入された液
状での封止用の樹脂は、加熱により硬化する際、既に上
述する如く、硬化収縮されて、その収縮力により電極端
子６と配線の凸部面５とが、密着接続されるものであ
る。Here, in the present invention, when the sealing resin in a sealed liquid state is cured by heating, it is cured and contracted as already described above, and the contraction force causes the contraction of the electrode terminal 6 and the wiring. The convex surface 5 is closely connected.
【００４２】従って、従来の同種の半導体装置の接続方
法として用いられている合金接続のような強固な接続で
はないため、このように半導体装置の組立時に発生する
熱応力が集中して接続部にかかることがない。従って、
本発明による製造方法によって、従来のこのような製造
過程での熱ストレス（又は残留歪み）を生ずることを効
果的に防止することができるのである。Therefore, since the connection is not as strong as the alloy connection used as a conventional connection method for the same type of semiconductor device, the thermal stress generated during the assembly of the semiconductor device is concentrated on the connection portion. There is no such thing. Therefore,
With the manufacturing method according to the present invention, it is possible to effectively prevent the occurrence of thermal stress (or residual strain) in such a conventional manufacturing process.
【００４３】また、既に上述する如く、この樹脂による
封止、密着接続において、第１次で、予め少量の封止樹
脂を用いて半導体素子とフレキシブル基板とを仮固定し
た後に、第２次として封止樹脂を封入させることから、
接続部にこの樹脂を巻き込むことはなくなる。In addition, as already described above, in the sealing and close contact connection with the resin, after the semiconductor element and the flexible substrate are temporarily fixed in advance using a small amount of sealing resin in advance, the second connection is performed. Since the sealing resin is enclosed,
This resin does not get caught in the connection part.
【００４４】また、本発明においては、このような半田
ボール型の他に、既に上述する如く、図３に示す如く、
リード状の外部端子を有するアウターボンディング型の
半導体装置についても適応することができる。図３から
明らかなように、配線パターンがそのまま外部端子とな
り、ポリイミドを用いたフレキシブル基板２の場合は、
ＴＣＰ（Tape Carrier Package）と呼ばれる半導体装
置となる。In the present invention, in addition to such a solder ball type, as described above, as shown in FIG.
The present invention is also applicable to an outer bonding type semiconductor device having lead-like external terminals. As is clear from FIG. 3, in the case of the flexible substrate 2 using polyimide, the wiring pattern becomes the external terminal as it is,
The semiconductor device is called a TCP (Tape Carrier Package).
【００４５】[0045]
【発明の効果】以上から、本発明によれば、凹部の溝パ
ターンが形成される配線パターンを有するフレキシブル
基板と半導体素子の電極端子とを封止樹脂の熱硬化時の
収縮力により密着接続させることにより、従来のように
接続面にかかる熱応力を著しく低減させられて、高い信
頼性を可能にするフェースダウンボンディング型の半導
体装置を提供することができる。As described above, according to the present invention, the flexible substrate having the wiring pattern in which the groove pattern of the concave portion is formed and the electrode terminal of the semiconductor element are closely connected by the contraction force of the sealing resin during thermosetting. This makes it possible to provide a face-down bonding type semiconductor device in which the thermal stress applied to the connection surface is significantly reduced unlike the related art, and high reliability can be achieved.
【００４６】また、特に、配線パターン上に、このよう
な凹部を設ける配線パターンを、フレキシブル基板上に
対向させて形成させることにより、この凹部の溝パター
ンを介して、従来のように新たにバンプを設けることな
く、半導体素子の電極端子と配線パターンをフレキシブ
ル基板と半導体素子とを封止樹脂させる熱硬化時の収縮
力により、この両者を強固に密着接続させることができ
るフェースダウンボンディング型の半導体装置製造方法
を提供することができる。In particular, by forming a wiring pattern for providing such a concave portion on the wiring pattern so as to face the flexible substrate, a new bump is formed through the groove pattern of the concave portion as in the prior art. A face-down bonding type semiconductor that can tightly and tightly connect both the electrode terminals of a semiconductor element and a wiring pattern by a contraction force at the time of thermosetting to seal and seal the flexible board and the semiconductor element without providing the semiconductor element. An apparatus manufacturing method can be provided.
【図１】本発明の実施形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本発明の実施形態の製造工程を示す断面図であ
る。FIG. 2 is a cross-sectional view illustrating a manufacturing process according to the embodiment of the present invention.
【図３】本発明の実施形態の他の例を示す断面図であ
る。FIG. 3 is a sectional view showing another example of the embodiment of the present invention.
１ 半導体素子 ２ フレキシブル基板 ３ 配線パターン ４ａ 凹部の溝パターン ４ｂ 樹脂法面 ５ 凸部面 ６ 電極端子 ７ 半田ボール ８ 封止樹脂 ９ スルーホール １０ アウターボンデイング DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Flexible board 3 Wiring pattern 4a Groove pattern of concave part 4b Resin slope 5 Convex part 6 Electrode terminal 7 Solder ball 8 Sealing resin 9 Through hole 10 Outer bonding
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M109 AA01 BA04 CA05 DA03 DA07 DB16 5F044 KK03 KK12 LL11 LL15 RR18 5F061 AA01 BA04 CA05 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M109 AA01 BA04 CA05 DA03 DA07 DB16 5F044 KK03 KK12 LL11 LL15 RR18 5F061 AA01 BA04 CA05
Claims (10)
置において、半導体素子の両端下部に電極端子を配し、
前記フレキシブル基板上に所定の間隔で対向する配線パ
ターンを配し、前記配線パターンには、互いに対向する
側の端部から所定幅の部位に凹部の溝パターンを有し、
且つ前記半導体素子と前記フレキシブル基板とが、対向
する前記配線パターンの間に施す樹脂封止材を介して、
前記両電極端子の面と前記配線パターンの対向側の端部
上面とが面合わせするように密着接触され、更に前記半
導体素子の両側面が、前記配線パターンの凹部の溝パタ
ーンに埋め込まれてなる樹脂法面でカバーされているこ
とを特徴とする半導体装置。In a semiconductor device formed on a flexible substrate, electrode terminals are arranged at lower portions on both ends of a semiconductor element.
Disposed wiring patterns facing each other at a predetermined interval on the flexible substrate, the wiring pattern has a groove pattern of a concave portion in a portion of a predetermined width from the end on the side facing each other,
And the semiconductor element and the flexible substrate, via a resin sealing material applied between the opposed wiring patterns,
The surfaces of the two electrode terminals and the upper surface of the end on the opposite side of the wiring pattern are in close contact with each other so as to face each other, and both side surfaces of the semiconductor element are embedded in the groove pattern of the concave portion of the wiring pattern. A semiconductor device covered by a resin slope.
幅に同等であることを特徴とする請求項１に記載の半導
体装置。2. The semiconductor device according to claim 1, wherein said predetermined width is at least equal to a width of said electrode terminal.
であることを特徴とする請求項１又は２に記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the resin sealing material is an insulating thermosetting resin.
ンの反対側の端部下部面が、前記基板に設けるスルーホ
ールに埋め込まれている半田ボールに接合していること
を特徴とする請求項１〜３の何れかに記載の半導体装
置。4. The semiconductor device according to claim 1, wherein a lower surface of the opposite end of said wiring pattern arranged opposite to each other is joined to a solder ball embedded in a through hole provided in said substrate. Item 4. The semiconductor device according to any one of Items 1 to 3.
記配線パターンの各外側の端部が、外部端子であって、
且つアウターボンデイングされていることを特徴とする
請求項１〜３の何れかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein each of the outer ends of the wiring patterns disposed on the substrate so as to face each other is an external terminal,
The semiconductor device according to claim 1, further comprising an outer bond.
せる製造方法において、 前記フレキシブル基板上に、所定の間隔で互いに対向さ
せて、配線パターンを形成し、且つ前記配線パターンに
は、予め前記基板上で互いに対向する側の端部から所定
幅の部位に凹部の溝パターンを形成し、 次いで、前記基板上の前記配線パターンの間に、液状の
樹脂封止材を垂らした後、両端下部面に電極端子を配す
る半導体素子を、前記両電極端子の面と前記配線パター
ンの互いに対向する側の端部の上面とを面合わせ接触さ
せ、上部からの加圧下に加熱させて第１次の接触固定を
させ、 次いで、前記配線パターン上の凹部の溝パターンに前記
液状の樹脂封止材を垂らして、毛細管現象を介して、前
記第１次の接触固定時に生ずる隙間に封入させ、加熱下
に熱硬化収縮させて第２次の接触固定をさせて、前記電
極端子の面と前記配線パターンの両端部の面とを密着接
続させることを特徴とする半導体装置の製造方法。6. A manufacturing method for forming a semiconductor device on a flexible substrate, wherein a wiring pattern is formed on the flexible substrate so as to be opposed to each other at a predetermined interval, and the wiring pattern is formed on the substrate in advance. A groove pattern of a concave portion is formed in a portion of a predetermined width from an end portion on the side opposite to each other, and then a liquid resin sealing material is dropped between the wiring patterns on the substrate, and then a lower surface of both ends is formed. The semiconductor element on which the electrode terminals are arranged is brought into face-to-face contact with the surfaces of the two electrode terminals and the upper surfaces of the ends on the opposite sides of the wiring pattern, and is heated under pressure from the top to cause the first contact. Then, the liquid resin encapsulant is dropped on the groove pattern of the concave portion on the wiring pattern, and is sealed in a gap generated at the time of the first contact fixing through a capillary phenomenon. By a secondary contact fixing by heat-curing shrinkage, a method of manufacturing a semiconductor device, characterized in that for adhering connection between the surface of both end portions of the surface and the wiring pattern of the electrode terminal.
樹脂を施し、前記半導体素子の両側に法面を形成させて
カバーすることを特徴とする請求項６に記載の半導体装
置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein a resin is applied to a groove pattern of a concave portion of each of the wiring patterns, and a slope is formed on both sides of the semiconductor element to cover the semiconductor element.
ッチング法で形成することを特徴とする請求項６〜７の
何れかに記載の半導体装置の製造方法。8. The method of manufacturing a semiconductor device according to claim 6, wherein the groove of the concave portion of each wiring pattern is formed by a mesa etching method.
記配線パターンの反対側の端部下部面を、記基板に設け
るスルーホールに埋め込まれている半田ボールに接合さ
せることを特徴する請求項６〜８の何れかに記載の半導
体装置の製造方法。9. A solder ball embedded in a through hole provided in the substrate, wherein a lower surface of an opposite end of the wiring pattern disposed on the substrate so as to face each other is joined. A method for manufacturing a semiconductor device according to claim 6.
前記各配線パターンの外側の端部を外部端子とし、且つ
前記外部端子とアウターボンデイングすることを特徴と
する請求項６〜８の何れかに記載の半導体装置の製造方
法。10. The semiconductor device according to claim 6, wherein the outer end of each of said wiring patterns disposed on said substrate so as to face each other is used as an external terminal, and is externally bonded to said external terminal. A method for manufacturing a semiconductor device according to any one of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20833099A JP2001035886A (en) | 1999-07-23 | 1999-07-23 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20833099A JP2001035886A (en) | 1999-07-23 | 1999-07-23 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001035886A true JP2001035886A (en) | 2001-02-09 |
Family
ID=16554491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20833099A Pending JP2001035886A (en) | 1999-07-23 | 1999-07-23 | Semiconductor device and its manufacture |
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| Country | Link |
|---|---|
| JP (1) | JP2001035886A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002305361A (en) * | 2001-04-05 | 2002-10-18 | Casio Micronics Co Ltd | Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor |
| JP2006278724A (en) * | 2005-03-29 | 2006-10-12 | Seiko Epson Corp | Semiconductor device and its manufacturing process |
| US7157308B2 (en) | 2003-02-26 | 2007-01-02 | Seiko Epson Corporation | Circuit substrates, semiconductor devices, semiconductor manufacturing apparatus methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices |
| JP2007103853A (en) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | Semiconductor device |
| WO2009050891A1 (en) * | 2007-10-17 | 2009-04-23 | Panasonic Corporation | Mounting structure |
| US8110933B2 (en) | 2006-12-26 | 2012-02-07 | Panasonic Corporation | Semiconductor device mounted structure and semiconductor device mounted method |
-
1999
- 1999-07-23 JP JP20833099A patent/JP2001035886A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002305361A (en) * | 2001-04-05 | 2002-10-18 | Casio Micronics Co Ltd | Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor |
| US7157308B2 (en) | 2003-02-26 | 2007-01-02 | Seiko Epson Corporation | Circuit substrates, semiconductor devices, semiconductor manufacturing apparatus methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices |
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