JP2006210591A - Semiconductor apparatus and its manufacturing method - Google Patents

Semiconductor apparatus and its manufacturing method Download PDF

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JP2006210591A
JP2006210591A JP2005019710A JP2005019710A JP2006210591A JP 2006210591 A JP2006210591 A JP 2006210591A JP 2005019710 A JP2005019710 A JP 2005019710A JP 2005019710 A JP2005019710 A JP 2005019710A JP 2006210591 A JP2006210591 A JP 2006210591A
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semiconductor element
circuit board
semiconductor device
sealing resin
land
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JP4573657B2 (en
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Rikiya Okimoto
力也 沖本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385Shape, e.g. interlocking features

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus which can ensure electrical connection in high reliability without dislocation between a projecting electrode and a land while the joint is filled with a sealing resin without voids. <P>SOLUTION: The semiconductor apparatus is formed by flip-chip mounting a semiconductor device 1 on a circuit board 2, and filling a sealing resin 7 between the semiconductor device 1 and the circuit board 2. In this case, a projecting electrode 4 is provided on the electrode 3 of the semiconductor device 1. A position regulating projection 6 such as an interrupting annular projection is provided to form an open groove 9 for opening to the side a recessed hole 8 and the internal space of the recessed hole 8 to which the tip end of the projecting electrode 4 is inserted, in a land 5 to be bonded with the projecting electrode 4 of the circuit board 2. The dislocation of the projecting electrode 4 can be prevented by the position regulating projection 6, and the sealing resin 7 can be charged by the open groove 9 without producing voids. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof.

実装技術の分野においては、電子機器の小型化・高機能化に伴い、高密度な実装が要求されている。その中で、半導体素子に突起電極を設け、回路基板のランドにフリップチップ実装して成る半導体装置が開発されている。   In the field of packaging technology, high-density packaging is required as electronic devices become smaller and more functional. Among them, a semiconductor device has been developed in which a protruding electrode is provided on a semiconductor element and flip-chip mounting is performed on a land of a circuit board.

従来のこの種の半導体装置の製造方法について、図6を参照して説明する。まず、図6(a)に示すように、周知の技術である成膜工程、リソグラフィ工程、エッチング工程を経て任意の回路が形成されている半導体素子21の電極22上に、この半導体素子21を実装する回路基板との電気的な接続を図るための突起電極25が形成される。突起電極25は、キャピラリー23の貫通孔を通して突出させた金、アルミニウムなどの金属線24の先端部に放電電流を流して金属ボールを形成した状態で、キャピラリー23にて金属ボールを半導体素子21の電極22に接触させ、加圧力及び超音波振動を加えることにより、電極22と金属ボールを接合させた後、キャピラリー23を上昇させて金属線24を破断することで形成される。   A conventional method of manufacturing this type of semiconductor device will be described with reference to FIG. First, as shown in FIG. 6A, the semiconductor element 21 is formed on the electrode 22 of the semiconductor element 21 in which an arbitrary circuit is formed through a film forming process, a lithography process, and an etching process, which are well-known techniques. A protruding electrode 25 is formed for electrical connection with a circuit board to be mounted. The protruding electrode 25 is formed in a state in which a metal ball is formed by flowing a discharge current through the tip of a metal wire 24 such as gold or aluminum protruding through the through hole of the capillary 23. The electrode 22 is brought into contact with the electrode 22 and subjected to pressure and ultrasonic vibration to join the electrode 22 and the metal ball, and then the capillary 23 is raised to break the metal wire 24.

一方、図6(b)に示すように、回路基板26の半導体素子21を実装する面上に封止用の樹脂シート27を配置し、貼付ツール28を用いて加熱、加圧を行って、半導体素子21が実装される領域に樹脂シート27を貼り付ける。次に、図6(c)に示すように、回路基板26のランド29と半導体素子21の突起電極25とが対向するように、回路基板26上に半導体素子21を位置合わせし、半導体素子21を搭載する。   On the other hand, as shown in FIG. 6B, a sealing resin sheet 27 is disposed on the surface of the circuit board 26 on which the semiconductor element 21 is mounted, and heating and pressing are performed using a pasting tool 28. A resin sheet 27 is attached to a region where the semiconductor element 21 is mounted. Next, as shown in FIG. 6C, the semiconductor element 21 is aligned on the circuit board 26 so that the land 29 of the circuit board 26 and the protruding electrode 25 of the semiconductor element 21 face each other. Is installed.

次に、図6(d)に示すように、熱圧着ツール30により加圧、加熱を行う。これにより、突起電極25がレベリングされながらランド29に電気的及び機械的に接合され、同時に樹脂シート27の溶融・硬化反応が行われ、半導体素子21と回路基板26とが封止される。   Next, as shown in FIG. 6D, pressurization and heating are performed with a thermocompression bonding tool 30. As a result, the protruding electrode 25 is electrically and mechanically joined to the land 29 while being leveled, and at the same time, the resin sheet 27 is melted and cured to seal the semiconductor element 21 and the circuit board 26.

このとき、突起電極25の形成時の位置精度、半導体素子21の装着時の位置合わせ精度、ランド29の形状、熱圧着ツール30の平行度等の誤差の複合によって、図6(e)に示すように、半導体素子21の突起電極25がランド29の上を滑って対応するランド29に対して位置ずれし、半導体素子21の回路基板26に対する電気的な接続の信頼性が大幅に低下するという問題があった。   At this time, as shown in FIG. 6E due to a combination of errors such as the positional accuracy when the protruding electrode 25 is formed, the alignment accuracy when the semiconductor element 21 is mounted, the shape of the land 29, the parallelism of the thermocompression bonding tool 30, and the like. As described above, the protruding electrode 25 of the semiconductor element 21 slides on the land 29 and is displaced with respect to the corresponding land 29, and the reliability of the electrical connection of the semiconductor element 21 to the circuit board 26 is greatly reduced. There was a problem.

このような問題を解決する半導体装置も既に提案されている(例えば、特許文献1参照。)。次に、この特許文献1に開示された半導体装置を図7を参照して説明する。   A semiconductor device that solves such a problem has already been proposed (see, for example, Patent Document 1). Next, the semiconductor device disclosed in Patent Document 1 will be described with reference to FIG.

図7において、半導体装置31は、半導体素子32と回路基板35を電気的及び機械的に接続し、半導体素子32と回路基板35との間を封止樹脂38にて封止して構成されている。半導体素子32の電極33上には、例えば金から成る突起電極34が形成され、この突起電極34を回路基板35の対応する各ランド36に形成された凹孔37にて受けた状態で、突起電極34とランド36を機械的及び電気的に接合することにより、半導体素子32と回路基板35が機械的及び電気的に接続されている。また、封止樹脂38にて、突起電極34とランド36の接続部が保護されている。このように、回路基板35のランド36に凹孔37を形成し、その凹孔37にて突起電極34を受けることで、突起電極34がランド36上を滑って位置ずれすることを防止する構成とされている。
特開平10−189655号公報
In FIG. 7, a semiconductor device 31 is configured by electrically and mechanically connecting a semiconductor element 32 and a circuit board 35 and sealing between the semiconductor element 32 and the circuit board 35 with a sealing resin 38. Yes. A protruding electrode 34 made of, for example, gold is formed on the electrode 33 of the semiconductor element 32, and the protruding electrode 34 is received in a recessed hole 37 formed in each corresponding land 36 of the circuit board 35. The semiconductor element 32 and the circuit board 35 are mechanically and electrically connected by mechanically and electrically joining the electrode 34 and the land 36. Further, the connecting portion between the protruding electrode 34 and the land 36 is protected by the sealing resin 38. As described above, the concave hole 37 is formed in the land 36 of the circuit board 35, and the protruding electrode 34 is received in the concave hole 37, thereby preventing the protruding electrode 34 from slipping and being displaced on the land 36. It is said that.
Japanese Patent Laid-Open No. 10-189655

しかしながら、図7に示すような構成では、ランド36に形成した凹孔37内まで封止樹脂38が均一に充填されず、未充填部分が発生することがある。ランドと突起電極の接合部に封止樹脂の未充填部分が存在すると、一般的に行われる吸湿リフロー試験等で、この未充填部分に浸入した水分が水蒸気爆発を起こし、接続不良を発生する恐れがあり、回路基板35に対する半導体素子32の電気的な接続の信頼性が大幅に低下するという問題がある。   However, in the configuration shown in FIG. 7, the sealing resin 38 is not uniformly filled into the concave hole 37 formed in the land 36, and an unfilled portion may occur. If there is an unfilled part of the sealing resin at the joint between the land and the protruding electrode, moisture that has entered the unfilled part may cause a steam explosion in a moisture absorption reflow test, etc. There is a problem that the reliability of the electrical connection of the semiconductor element 32 to the circuit board 35 is significantly reduced.

本発明は、上記従来の課題を解決するもので、突起電極とランドの位置ずれを生じずかつその接続部に封止樹脂が空房を生じることなく充填されて電気的接続に高い信頼性を確保できる半導体装置及びその製造方法を提供することを目的とする。   The present invention solves the above-described conventional problems, and does not cause misalignment between the projecting electrode and the land, and the sealing resin is filled in the connection portion without causing vacancies, thereby ensuring high reliability in electrical connection. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

本発明の半導体装置は、半導体素子を回路基板上にフリップチップ実装し、半導体素子と回路基板との間に封止樹脂を充填して成る半導体装置であって、半導体素子の各電極にそれぞれ突起電極を設け、各突起電極を接合する回路基板のランドの内の少なくとも複数のランドに、突起電極の先端部側面の一部と対向して突起電極を位置規制する位置規制突部を設けたものである。   A semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is flip-chip mounted on a circuit board, and a sealing resin is filled between the semiconductor element and the circuit board, and a protrusion is formed on each electrode of the semiconductor element. Provided with electrodes, and at least a plurality of lands of the circuit board to which the protruding electrodes are joined, are provided with position restricting protrusions that position the protruding electrodes so as to face part of the side surfaces of the protruding electrodes. It is.

この構成によれば、半導体素子の各突起電極が回路基板の対応するランドに対向するように半導体素子を位置決めして回路基板に搭載すると、複数の突起電極が位置規制突部で位置規制されることで、半導体素子の各突起電極と回路基板の各ランドを確実に位置決めすることができ、半導体素子を位置ずれを生じることなく回路基板に搭載でき、かつ半導体素子と回路基板の間に封止樹脂を充填する際に封止樹脂は位置規制突部以外の部分からランド上に円滑かつ確実に流入し、また余分な封止樹脂が円滑に流出するため、空房を噛み込まず、各突起電極の周囲に封止樹脂を均一に充填できるため、信頼性の高い電気的接続を確保することができる。   According to this configuration, when the semiconductor element is positioned and mounted on the circuit board so that each protruding electrode of the semiconductor element faces the corresponding land of the circuit board, the position of the plurality of protruding electrodes is restricted by the position restricting protrusions. Thus, each protruding electrode of the semiconductor element and each land of the circuit board can be reliably positioned, the semiconductor element can be mounted on the circuit board without causing a positional shift, and the sealing between the semiconductor element and the circuit board is possible. When filling the resin, the sealing resin flows smoothly and surely from the part other than the position restricting protrusions, and the excess sealing resin flows out smoothly. Since the sealing resin can be uniformly filled in the periphery, a highly reliable electrical connection can be ensured.

また、位置規制突部は、突起電極の先端部が挿入される凹孔と、その凹孔内空間を側方に開放する開放溝とを形成する断続環状突部から成るのが好適である。この構成によれば、半導体素子の突起電極を凹孔に挿入することで、突起電極とランドを確実に位置決めでき、また封止樹脂の充填時にも封止樹脂が開放溝を通して凹孔内に確実に流入し、また余分な封止樹脂が円滑に流出するため、空房を噛み込まず、各突起電極の周囲に封止樹脂を均一に充填できる。   In addition, the position restricting protrusion preferably includes an intermittent annular protrusion that forms a concave hole into which the tip end portion of the protruding electrode is inserted and an open groove that opens the inner space of the concave hole to the side. According to this configuration, the protruding electrode and the land can be reliably positioned by inserting the protruding electrode of the semiconductor element into the recessed hole, and the sealing resin can be reliably inserted into the recessed hole through the open groove even when the sealing resin is filled. In addition, since excess sealing resin flows out smoothly, the sealing resin can be uniformly filled around each protruding electrode without biting the vacancies.

また、ランド間で開放溝の開口方向が異なるものを存在させることで、各凹孔内に挿入した各突起電極が開放溝の開放方向に一様に移動し、開放溝を通して凹孔内から抜け出すというような事態によって位置ずれを生じるのを防止することができる。   In addition, by causing the lands to have different opening directions of the open grooves, the protruding electrodes inserted into the recessed holes move uniformly in the opening direction of the open grooves and come out of the recessed holes through the open grooves. It is possible to prevent the occurrence of displacement due to such a situation.

また、一部又は全部のランドにおいて、その凹孔から複数の方向に開放溝を形成すると、凹孔内に封止樹脂が均一に充填され易く、未充填部の発生を抑制することができる。   In addition, in some or all of the lands, when the open grooves are formed in a plurality of directions from the concave holes, the concave resin is easily filled with the sealing resin, and generation of unfilled portions can be suppressed.

また、凹孔内が金メッキ処理されていると、半導体素子の突起電極との接合を安定して行うことができる。   Moreover, when the inside of the concave hole is gold-plated, it is possible to stably perform bonding with the protruding electrode of the semiconductor element.

また、凹孔が上方に向けて広がるテーパ状に形成されていると、突起電極がテーパ状の側壁部を滑って円滑に凹孔内に挿入され、確実に凹孔内に位置決めすることができる。   In addition, when the concave hole is formed in a tapered shape that spreads upward, the protruding electrode can be smoothly inserted into the concave hole by sliding on the tapered side wall portion, and can be reliably positioned in the concave hole. .

また、本発明の半導体装置の製造方法は、半導体素子を回路基板上にフリップチップ実装し、半導体素子と回路基板との間に封止樹脂を充填して成る半導体装置の製造方法であって、半導体素子の回路面上に形成された各電極にそれぞれ突起電極を形成する突起電極形成工程と、回路基板に、電子部品の各突起電極をそれぞれ接合するランドを形成するとともに、少なくとも一部の複数のランドに、突起電極の先端部側面の一部と対向して突起電極を位置規制する位置規制突部を形成するランド形成工程と、回路基板上の半導体素子実装領域に封止樹脂を配置する封止樹脂配置工程と、半導体素子の突起電極とランドを位置決めした状態で半導体素子を回路基板に搭載する半導体素子搭載工程と、搭載した半導体素子を所定の圧着温度及び圧着圧力で所定の圧着時間回路基板に熱圧着する圧着工程とを備えたものである。   The semiconductor device manufacturing method of the present invention is a semiconductor device manufacturing method in which a semiconductor element is flip-chip mounted on a circuit board, and a sealing resin is filled between the semiconductor element and the circuit board. A protruding electrode forming step for forming a protruding electrode on each electrode formed on the circuit surface of the semiconductor element, a land for bonding each protruding electrode of the electronic component to each circuit board, and at least some of the plurality A land forming step for forming a position restricting protrusion for restricting the position of the protruding electrode on a land of the protruding electrode so as to face a part of the side surface of the tip of the protruding electrode, and disposing a sealing resin in a semiconductor element mounting region on the circuit board A sealing resin arranging step, a semiconductor element mounting step of mounting the semiconductor element on the circuit board in a state where the protruding electrode and the land of the semiconductor element are positioned, and the mounted semiconductor element is subjected to a predetermined pressure and temperature. It is obtained by a crimping step of thermocompression bonding at a predetermined bonding time circuit board with a pressure.

この構成によると、半導体素子の複数の突起電極を回路基板の対応するランドに形成された位置規制突部にて位置決めして半導体素子を回路基板に搭載した後、半導体素子を回路基板に対して熱圧着して半導体素子の電極を回路基板の対応するランドに接合することにより、熱圧着時に半導体素子の突起電極が位置規制突部で位置規制されていることで半導体素子の突起電極がランド上を滑って対応するランドに対して位置ずれするのを抑制することができ、またランド上を円滑に封止樹脂が流動できるので封止樹脂に空房を噛み込まず、封止樹脂が均一に充填され、信頼性の高い半導体装置を得ることができる。   According to this configuration, after the plurality of protruding electrodes of the semiconductor element are positioned by the position restricting protrusions formed on the corresponding lands of the circuit board and the semiconductor element is mounted on the circuit board, the semiconductor element is mounted on the circuit board. By bonding the electrode of the semiconductor element to the corresponding land of the circuit board by thermocompression bonding, the protruding electrode of the semiconductor element is regulated on the land by the position regulating projection at the time of thermocompression bonding. Can be prevented from slipping relative to the corresponding land, and the sealing resin can flow smoothly on the land, so the sealing resin does not bite into the sealing resin and fills the sealing resin uniformly. Thus, a highly reliable semiconductor device can be obtained.

本発明の半導体装置及びその製造方法によれば、半導体素子の複数の突起電極を回路基板の対応するランドに形成された位置規制突部で位置規制することで、半導体素子を位置ずれを生じることなく回路基板に搭載できる。また、半導体素子と回路基板の間に封止樹脂を充填する際にランド上を封止樹脂が円滑に流動するため、封止樹脂に空房を噛み込まず、突起電極の周囲に封止樹脂を均一に充填できる。かくして、信頼性の高い電気的接続を確保した半導体装置を得ることができる。   According to the semiconductor device and the manufacturing method thereof of the present invention, the position of the plurality of protruding electrodes of the semiconductor element is regulated by the position regulating projections formed on the corresponding land of the circuit board, thereby causing the semiconductor element to be displaced. And can be mounted on a circuit board. Also, since the sealing resin smoothly flows on the land when the sealing resin is filled between the semiconductor element and the circuit board, the sealing resin is not surrounded by the sealing resin, and the sealing resin is placed around the protruding electrodes. Can be filled uniformly. Thus, a semiconductor device that ensures highly reliable electrical connection can be obtained.

以下、本発明の半導体装置及びその製造方法の一実施形態について、図1〜図5を参照しながら説明する。   Hereinafter, an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS.

図1(a)において、1は、周知の技術である成膜工程、リソグラフィ工程、エッチング工程を経て任意の回路が形成された半導体素子であり、回路基板2との電気的な接続を図るための電極3上に、ワイヤボンディング法やメッキ法により突起電極4が形成されている。   In FIG. 1A, reference numeral 1 denotes a semiconductor element in which an arbitrary circuit is formed through a well-known technique of a film forming process, a lithography process, and an etching process, in order to achieve electrical connection with the circuit board 2. A protruding electrode 4 is formed on the electrode 3 by wire bonding or plating.

回路基板2は、周知の技術であるリソグラフィ工程、エッチング工程を経て任意の回路が形成されており、突起電極4に対応するランド5には2段エッチング法、ハーフエッチング法、メッキ法等により、位置規制突部6が形成されている。本実施形態では、位置規制突部6は、図1(b)に示すように、中央部に凹孔8を形成するとともに凹孔8の内部空間を側方に開放する開放溝9を形成する断続環状突部にて構成されている。その凹孔8内に突起電極4を挿入した後加圧力と熱を加えることで、突起電極4がレベリングされた状態で突起電極4とランド5が熱圧着され、半導体素子1と回路基板2が電気的に接続されている。   An arbitrary circuit is formed on the circuit board 2 through a known lithography process and etching process, and the land 5 corresponding to the protruding electrode 4 is formed by a two-stage etching method, a half etching method, a plating method, or the like. A position restricting protrusion 6 is formed. In this embodiment, as shown in FIG. 1B, the position restricting protrusion 6 forms a concave hole 8 at the center and an open groove 9 that opens the inner space of the concave hole 8 sideways. It is comprised by the intermittent annular protrusion. By inserting the protruding electrode 4 into the concave hole 8 and then applying pressure and heat, the protruding electrode 4 and the land 5 are thermocompression bonded with the protruding electrode 4 being leveled, so that the semiconductor element 1 and the circuit board 2 are connected. Electrically connected.

このようにランド5に形成した位置規制突部6にて突起電極4を位置規制しているため、半導体素子1を回路基板2上に搭載する際に半導体素子1が回路基板2に対して傾斜している場合や、半導体素子1を回路基板2に加圧する際に半導体素子1の突起電極4に対する圧力のかけ方が均一でない場合でも、半導体素子1がランド5上を滑って位置ずれすることを抑制することができる。   Since the protruding electrode 4 is regulated by the position regulating projection 6 formed on the land 5 in this way, the semiconductor element 1 is inclined with respect to the circuit board 2 when the semiconductor element 1 is mounted on the circuit board 2. Even when the semiconductor element 1 is pressed against the circuit board 2 or when the pressure applied to the protruding electrode 4 of the semiconductor element 1 is not uniform, the semiconductor element 1 slips on the land 5 and is displaced. Can be suppressed.

半導体素子1と回路基板2との間には、封止樹脂7が充填されている。封止樹脂7は、熱硬化性樹脂を用いており、硬化温度以下で加熱することで溶融し、同時に加圧することで半導体素子1と回路基板2との間を周囲に向けて流動する。さらに加熱し、硬化温度以上となると硬化し、半導体素子1と回路基板2とを強固に接着させる。   A sealing resin 7 is filled between the semiconductor element 1 and the circuit board 2. The sealing resin 7 uses a thermosetting resin, melts by heating at a temperature equal to or lower than the curing temperature, and flows between the semiconductor element 1 and the circuit board 2 toward the periphery by simultaneously applying pressure. Further heating is performed and the semiconductor element 1 and the circuit board 2 are firmly bonded to each other when the temperature exceeds the curing temperature.

本実施形態では、ランド5に、凹孔8とその内部空間を側方に開放する開放溝9が形成されているため、封止樹脂7の溶融時に開放溝9を通して溶融樹脂が凹孔8内に流入し、また余分な溶融樹脂が流出するため、凹孔8内に封止樹脂7の未充填部が発生しない。   In the present embodiment, the land 5 is formed with the concave hole 8 and an open groove 9 that opens the internal space to the side, so that when the sealing resin 7 is melted, the molten resin passes through the open groove 9 to enter the concave hole 8. In addition, since excess molten resin flows out, no unfilled portion of the sealing resin 7 is generated in the concave hole 8.

なお、図2(a)に示すように、ランド5に形成された凹孔8の開放溝9による開放方向を全て同一方向とするのではなく、図2(b)に示すように、ランド5の配置領域の中心から略放射状に向いた方向にするなど、多様な方向とするのが好ましい。なぜなら、図2(a)に示すように開放方向が同一方向である場合は、半導体素子1の実装時に開放溝9より突起電極4がずれ落ちる恐れがあるが、開放溝9による凹孔8の開放方向を多様にすることで、半導体素子1が位置ずれすることを抑制することができる。   As shown in FIG. 2A, the opening directions of the recessed holes 8 formed in the lands 5 by the opening grooves 9 are not all the same, but as shown in FIG. It is preferable to have various directions such as a direction that is substantially radially directed from the center of the arrangement region. 2A, when the opening direction is the same direction, the protruding electrode 4 may be displaced from the opening groove 9 when the semiconductor element 1 is mounted. By diversifying the opening directions, it is possible to suppress the displacement of the semiconductor element 1.

また、ランド5における凹孔8の開放溝9を、図3に示すように複数設けるのが好ましい。なぜなら、開放溝9が複数設けられることで、封止樹脂7が溶融した際に凹孔8内に流入、流出し易いため、封止樹脂7の未充填部の発生を大幅に抑制することができるからである。図示例では、開放溝9を3方向に形成しているが、2方向でも、4方向以上でも良い。封止樹脂7の充填され易さからは、開放溝9が多い程よいが、多過ぎると突起電極4が抜け出す確率が高くなるため好ましくなく、突起電極4の形状・大きさによって適切に設計される。また、開放溝9による凹孔8の開放方向が多くても、その開放方向をランド5間で適当に異ならせることで突起電極4を抜け出しを防止することは可能である。   Moreover, it is preferable to provide a plurality of open grooves 9 for the recessed holes 8 in the land 5 as shown in FIG. This is because the provision of a plurality of open grooves 9 makes it easy to flow into and out of the concave hole 8 when the sealing resin 7 is melted, so that the occurrence of unfilled portions of the sealing resin 7 can be significantly suppressed. Because it can. In the illustrated example, the open grooves 9 are formed in three directions, but may be two directions or four or more directions. From the viewpoint of easy filling of the sealing resin 7, it is better that the number of the open grooves 9 is larger. However, if the number is too large, the probability that the protruding electrode 4 comes out increases, which is not preferable, and is appropriately designed depending on the shape and size of the protruding electrode 4. . Even if the opening direction of the recessed hole 8 by the opening groove 9 is large, it is possible to prevent the protruding electrode 4 from coming out by appropriately changing the opening direction between the lands 5.

なお、凹孔8内には、金メッキ処理が施されているのが好ましい。なぜなら、ランド5と突起電極4との安定した電気的接触を得ることができるからである。また、凹孔8はテーパ状に形成されることが好ましい。なぜなら、半導体素子1の実装時に、突起被電極4がテーパ状の側壁部を滑って凹孔8内に案内され、突起被電極4を確実に凹孔8内に位置決めできるからである。   The concave hole 8 is preferably subjected to a gold plating process. This is because stable electrical contact between the land 5 and the protruding electrode 4 can be obtained. Moreover, it is preferable that the concave hole 8 is formed in a taper shape. This is because when the semiconductor element 1 is mounted, the protruding electrode 4 slides along the tapered side wall and is guided into the recessed hole 8, so that the protruding electrode 4 can be reliably positioned in the recessed hole 8.

以上の半導体装置の構成によれば、回路基板2のランド5に形成した凹孔8で半導体素子1の電極3に形成した突起電極4を受けるため、半導体素子1を回路基板2に搭載する際に、半導体素子1が回路基板2に対して傾斜している場合や、半導体素子1の加圧時に突起電極4に対する圧力のかけ方が均一でない場合でも、半導体素子1がランド5上を滑って対応するランド5に対して位置ずれすることを抑制することができ、さらに凹孔8内の空間を側方に開放する開放溝9を形成しているので、凹孔8内に封止樹脂7を未充填部を発生させることなく充填することができ、信頼性を向上し得る半導体装置を得ることができる。   According to the configuration of the semiconductor device described above, since the protruding electrode 4 formed on the electrode 3 of the semiconductor element 1 is received by the concave hole 8 formed in the land 5 of the circuit board 2, the semiconductor element 1 is mounted on the circuit board 2. Even when the semiconductor element 1 is inclined with respect to the circuit board 2 or when the pressure applied to the protruding electrode 4 is not uniform when the semiconductor element 1 is pressed, the semiconductor element 1 slides on the land 5. It is possible to suppress displacement with respect to the corresponding land 5, and furthermore, since the open groove 9 that opens the space in the recessed hole 8 to the side is formed, the sealing resin 7 is formed in the recessed hole 8. Can be filled without generating an unfilled portion, and a semiconductor device capable of improving reliability can be obtained.

次に、以上の構成の半導体装置の製造工程を図4を参照して説明する。   Next, a manufacturing process of the semiconductor device having the above configuration will be described with reference to FIG.

まず、図4(a)に示すように、半導体素子1は、周知の技術である成膜工程、リソグラフィ工程、エッチング工程を経て任意の回路が形成されており、回路基板2との電気的な接続を図るための突起電極4を電極3上に形成する。   First, as shown in FIG. 4A, an arbitrary circuit is formed in the semiconductor element 1 through a film forming process, a lithography process, and an etching process, which are well-known techniques. A protruding electrode 4 for connection is formed on the electrode 3.

本実施形態では、ワイヤボンディング法にて突起電極4を形成するため、キャピラリー11の貫通孔を通して突出させた金、アルミニウムなどの金属線12の先端部に放電電流を流して溶融させ、金ボールを形成した状態で、キャピラリー11にて金ボールを電極3に接触させ、加圧力及び超音波振動を加えることにより、電極3と金ボールとを接合し、その後キャピラリー11を上昇させ、金属線12を金ボールとの境界部近傍で破断することで、突起電極4が電極3上に形成される。具体例を示すと、金属線12として直径0.025mmの金線を用いることで、台座径が0.08mm、台座高さが0.02mm、頭頂高さが0.08mmの突起電極4を形成することができる。   In this embodiment, in order to form the protruding electrode 4 by the wire bonding method, the gold ball is melted by flowing a discharge current to the tip of the metal wire 12 such as gold or aluminum protruding through the through hole of the capillary 11. In the formed state, a gold ball is brought into contact with the electrode 3 with the capillary 11 and an applied pressure and ultrasonic vibration are applied to join the electrode 3 and the gold ball. Thereafter, the capillary 11 is raised, and the metal wire 12 is connected. The protruding electrode 4 is formed on the electrode 3 by breaking near the boundary with the gold ball. As a specific example, by using a gold wire having a diameter of 0.025 mm as the metal wire 12, the protruding electrode 4 having a pedestal diameter of 0.08 mm, a pedestal height of 0.02 mm, and a top height of 0.08 mm is formed. can do.

一方、回路基板2には、図4(b)に示すように、周知の技術であるリソグラフィ工程、エッチング工程を経て任意の回路が形成されており、半導体素子1の突起電極4に対応するランド5には、2段エッチング法やハーフエッチング法、メッキ法等により、断続環状突部から成る位置規制突部6が形成され、この断続環状突部にて開放溝9を有する凹孔8が構成されている。次に、この回路基板2の半導体素子1が実装される面上に樹脂シート13を配置し、貼付けツール14を用いて加熱、加圧を行って、図4(c)に示すように半導体素子1が実装される領域に貼り付けられたシート状の封止樹脂7を設ける。   On the other hand, as shown in FIG. 4B, an arbitrary circuit is formed on the circuit board 2 through a lithography process and an etching process, which are well-known techniques, and the land corresponding to the protruding electrode 4 of the semiconductor element 1 is formed. 5, a position restricting projection 6 comprising an intermittent annular projection is formed by a two-stage etching method, a half-etching method, a plating method, etc., and a concave hole 8 having an open groove 9 is formed by this intermittent annular projection. Has been. Next, a resin sheet 13 is placed on the surface of the circuit board 2 on which the semiconductor element 1 is mounted, and heated and pressurized using the affixing tool 14 to obtain the semiconductor element as shown in FIG. A sheet-shaped sealing resin 7 attached to a region where 1 is mounted is provided.

具体例を示すと、ランド5は、厚みが0.012mm、直径が0.08mmとし、凹孔8はリソグラフィ法により直径0.05mm、開放溝9の幅を0.02mmのものを形成した。また、シート状の封止樹脂13として、厚みが0.04mmのエポキシ系の熱硬化性樹脂シートを使用し、80℃、3sec、44kPaの条件で貼り付けを行い、封止樹脂7を形成した。   As a specific example, the land 5 has a thickness of 0.012 mm and a diameter of 0.08 mm, and the concave hole 8 has a diameter of 0.05 mm and the open groove 9 has a width of 0.02 mm by lithography. Further, an epoxy thermosetting resin sheet having a thickness of 0.04 mm was used as the sheet-shaped sealing resin 13, and pasting was performed under conditions of 80 ° C., 3 sec, and 44 kPa to form the sealing resin 7. .

次に、図4(c)に示すように、ランド5と突起電極4が対向するように、封止樹脂7を貼付けた回路基板2上に突起電極4を有する半導体素子1を位置合わせし、半導体素子1を回路基板2に搭載する。その際に、本実施形態では、ランド5における凹孔8の開放溝9の幅を、突起電極4の頭頂部径である金属線12の直径0.025mmよりも小さい0.02mmとしていることで、開放溝9を通して突起電極4がずれ落ちるのを抑制することができる。   Next, as shown in FIG. 4C, the semiconductor element 1 having the protruding electrode 4 is aligned on the circuit board 2 on which the sealing resin 7 is pasted so that the land 5 and the protruding electrode 4 face each other. The semiconductor element 1 is mounted on the circuit board 2. At this time, in this embodiment, the width of the open groove 9 of the concave hole 8 in the land 5 is set to 0.02 mm which is smaller than the diameter 0.025 mm of the metal wire 12 which is the diameter of the top of the protruding electrode 4. The protruding electrode 4 can be prevented from slipping through the open groove 9.

次に、図4(d)に示すように、熱圧着ツール15にて加圧、加熱を行うことにより、突起電極4が潰されてレベリングされながら、ランド5に電気的及び機械的に接合され、同時に封止樹脂7が溶融、硬化する。熱圧着条件は、210℃、20sec、220kPaとした。   Next, as shown in FIG. 4D, by applying pressure and heating with the thermocompression bonding tool 15, the protruding electrode 4 is electrically and mechanically joined to the land 5 while being crushed and leveled. At the same time, the sealing resin 7 is melted and cured. The thermocompression bonding conditions were 210 ° C., 20 sec, and 220 kPa.

本実施形態によれば、回路基板2のランド5に形成した位置規制突部6にて構成された凹孔8で突起電極4を受けるため、突起電極4の形成時の位置精度、半導体素子1の実装時の位置合わせ精度、ランド5の形状、熱圧着ツール15の平行度等が多少ずれていても、位置ずれすることなく、確実に突起電極4とランド5とを接合することができる。   According to the present embodiment, since the protruding electrode 4 is received by the recessed hole 8 formed by the position restricting protrusion 6 formed on the land 5 of the circuit board 2, the positional accuracy when forming the protruding electrode 4, the semiconductor element 1. Even if the alignment accuracy at the time of mounting, the shape of the land 5, the parallelism of the thermocompression bonding tool 15 and the like are slightly deviated, the protruding electrode 4 and the land 5 can be reliably bonded without being deviated.

また、凹孔8が開放溝9にて側方に開放されているため、開放溝9から溶融した封止樹脂7が流入、流出し易いため、封止樹脂7の未充填部の発生を抑制することができる。   Moreover, since the concave hole 8 is opened laterally by the open groove 9, the sealing resin 7 melted from the open groove 9 is likely to flow in and out, so that generation of unfilled portions of the sealing resin 7 is suppressed. can do.

上記実施形態では、図2(b)に示したように、矩形状の半導体素子1の四辺に沿って配設された全てのランド5に、位置規制突部6として断続環状突部を形成することで開放溝9を有する凹孔8を形成し、かつその開放溝9の開放方向を略放射状に配設した例を示したが、複数のランド5、例えば各辺の少なくとも1つのランド5にだけ開放溝9を有する凹孔8を形成し、その開放溝9の開放方向を互いに異ならせた構成としても良い。しかし、全てのランド5に凹孔8を形成することで、すべての突起電極4のそれぞれを挿入して位置決めできるため、より信頼性の高い電気的接続を確保することができる。   In the above-described embodiment, as shown in FIG. 2B, intermittent annular protrusions are formed as the position restricting protrusions 6 on all the lands 5 arranged along the four sides of the rectangular semiconductor element 1. In this example, the concave hole 8 having the open groove 9 is formed, and the open direction of the open groove 9 is arranged in a substantially radial manner. However, a plurality of lands 5, for example, at least one land 5 on each side is provided. It is also possible to form a concave hole 8 having only an open groove 9 and to open the open grooves 9 in different directions. However, by forming the recessed holes 8 in all the lands 5, it is possible to insert and position all the protruding electrodes 4, and thus it is possible to ensure a more reliable electrical connection.

更に、位置規制突部6は、開放溝9を有する凹孔8を形成する断続環状突部に限定されるものではなく、例えば、図5に示すように、矩形状に配列されたランド5の四隅部に位置するランド5の矩形状配列の角部分に、円弧状の位置規制突部6を設けた構成としても良い。   Furthermore, the position restricting protrusion 6 is not limited to the intermittent annular protrusion that forms the concave hole 8 having the open groove 9. For example, as illustrated in FIG. 5, the position restricting protrusion 6 includes the land 5 arranged in a rectangular shape. It is good also as a structure which provided the circular-arc-shaped position control protrusion 6 in the corner | angular part of the rectangular array of the land 5 located in four corners.

なお、以上の実施形態の説明では、予め回路基板2上にシート状の封止樹脂7を貼付けた後、半導体素子1を実装し、熱圧着を行ったが、半導体素子1を搭載した後に、ペースト状の封止樹脂を回路基板2と半導体素子1との間に流し込んで充填する方法であっても同様の効果を奏することができる。   In the above description of the embodiment, the sheet-shaped sealing resin 7 is pasted on the circuit board 2 in advance, and then the semiconductor element 1 is mounted and thermocompression bonded. However, after the semiconductor element 1 is mounted, The same effect can be obtained even by a method in which a paste-like sealing resin is poured between the circuit board 2 and the semiconductor element 1 and filled.

本発明の半導体装置及びその製造方法によれば、半導体素子の複数の突起電極を回路基板の対応するランドに形成された位置規制突部で位置規制することで、半導体素子を位置ずれを生じることなく回路基板に搭載でき、かつ半導体素子と回路基板の間に封止樹脂を充填する際にランド上を封止樹脂が円滑に流動するため、封止樹脂に空房を噛み込まず、突起電極の周囲に封止樹脂を均一に充填できるため、信頼性を向上し得る半導体装置を得るのに有用である。   According to the semiconductor device and the manufacturing method thereof of the present invention, the position of the plurality of protruding electrodes of the semiconductor element is regulated by the position regulating projections formed on the corresponding land of the circuit board, thereby causing the semiconductor element to be displaced. Can be mounted on the circuit board without any trouble, and when the sealing resin is filled between the semiconductor element and the circuit board, the sealing resin smoothly flows on the land. Since the periphery can be uniformly filled with a sealing resin, it is useful for obtaining a semiconductor device capable of improving reliability.

本発明の一実施形態における半導体装置の構成を示し、(a)は断面図、(b)は回路基板のランドの形状を示す斜視図。1A and 1B show a configuration of a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a cross-sectional view, and FIG. 同実施形態のランドに形成する位置規制突部の開放溝の方向の説明図。Explanatory drawing of the direction of the open groove | channel of the position control protrusion formed in the land of the embodiment. 同実施形態における位置規制突部の開放溝の他の形成例を示す斜視図。The perspective view which shows the other example of formation of the open groove | channel of the position control protrusion in the embodiment. 同実施形態における半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device in the embodiment. 同実施形態における位置規制突部の他の例を示す平面図。The top view which shows the other example of the position control protrusion in the embodiment. 従来例の半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device of a prior art example. 他の従来例の半導体装置の断面図。Sectional drawing of the semiconductor device of another prior art example.

符号の説明Explanation of symbols

1 半導体素子
2 回路基板
3 電極
4 突起電極
5 ランド
6 位置規制突部(断続環状突部)
7 封止樹脂
8 凹孔
9 開放溝
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Circuit board 3 Electrode 4 Projection electrode 5 Land 6 Position control protrusion (intermittent annular protrusion)
7 Sealing resin 8 Concave hole 9 Open groove

Claims (7)

半導体素子を回路基板上にフリップチップ実装し、半導体素子と回路基板との間に封止樹脂を充填して成る半導体装置であって、
半導体素子の各電極にそれぞれ突起電極を設け、各突起電極を接合する回路基板のランドの内の少なくとも複数のランドに、突起電極の先端部側面の一部と対向して突起電極を位置規制する位置規制突部を設けた
ことを特徴とする半導体装置。
A semiconductor device in which a semiconductor element is flip-chip mounted on a circuit board, and a sealing resin is filled between the semiconductor element and the circuit board,
Protrusion electrodes are provided on the respective electrodes of the semiconductor element, and the position of the protrusion electrodes is restricted to at least a plurality of lands of the circuit board to which the respective protrusion electrodes are bonded so as to face a part of the side surface of the tip portion of the protrusion electrode. A semiconductor device comprising a position restricting protrusion.
位置規制突部は、突起電極の先端部が挿入される凹孔と、その凹孔内空間を側方に開放する開放溝とを形成する断続環状突部から成ることを特徴とする請求項1記載の半導体装置。   2. The position restricting protrusion comprises an intermittent annular protrusion that forms a concave hole into which a tip end portion of the protruding electrode is inserted and an open groove that opens the inner space of the concave hole to the side. The semiconductor device described. ランド間で開放溝の開口方向が異なるものが存在することを特徴とする請求項2記載の半導体装置。   The semiconductor device according to claim 2, wherein there are those in which the opening direction of the open groove differs between lands. 一部又は全部のランドにおいて、その凹孔から複数の方向に開放溝が形成されていることを特徴とする請求項2記載の半導体装置。   3. The semiconductor device according to claim 2, wherein in some or all of the lands, open grooves are formed in a plurality of directions from the recessed holes. 凹孔内が金メッキ処理されていることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein the inside of the concave hole is gold-plated. 凹孔は上方に向けて広がるテーパ状に形成されていることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein the concave hole is formed in a tapered shape that widens upward. 半導体素子を回路基板上にフリップチップ実装し、半導体素子と回路基板との間に封止樹脂を充填して成る半導体装置の製造方法であって、
半導体素子の回路面上に形成された各電極にそれぞれ突起電極を形成する突起電極形成工程と、
回路基板に、電子部品の各突起電極をそれぞれ接合するランドを形成するとともに、少なくとも一部の複数のランドに、突起電極の先端部側面の一部と対向して突起電極を位置規制する位置規制突部を形成するランド形成工程と、
回路基板上の半導体素子実装領域に封止樹脂を配置する封止樹脂配置工程と、
半導体素子の突起電極とランドを位置決めした状態で半導体素子を回路基板に搭載する半導体素子搭載工程と、
搭載した半導体素子を所定の圧着温度及び圧着圧力で所定の圧着時間回路基板に熱圧着する圧着工程とを備えた
ことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device comprising flip-chip mounting a semiconductor element on a circuit board and filling a sealing resin between the semiconductor element and the circuit board,
A protruding electrode forming step of forming a protruding electrode on each of the electrodes formed on the circuit surface of the semiconductor element;
Position regulation for forming a land for joining each bump electrode of an electronic component on the circuit board and for regulating the position of the bump electrode on at least a part of the plurality of lands facing a part of the side surface of the tip portion of the bump electrode A land forming step for forming a protrusion; and
A sealing resin arrangement step of arranging a sealing resin in a semiconductor element mounting region on the circuit board;
A semiconductor element mounting step of mounting the semiconductor element on the circuit board in a state where the protruding electrode and the land of the semiconductor element are positioned;
A method of manufacturing a semiconductor device, comprising: a step of thermocompression bonding a mounted semiconductor element to a circuit board at a predetermined pressure bonding temperature and pressure for a predetermined pressure bonding time.
JP2005019710A 2005-01-27 2005-01-27 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4573657B2 (en)

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