JP2001068509A - Semiconductor mounting method and semiconductor device - Google Patents
Semiconductor mounting method and semiconductor deviceInfo
- Publication number
- JP2001068509A JP2001068509A JP23797399A JP23797399A JP2001068509A JP 2001068509 A JP2001068509 A JP 2001068509A JP 23797399 A JP23797399 A JP 23797399A JP 23797399 A JP23797399 A JP 23797399A JP 2001068509 A JP2001068509 A JP 2001068509A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- circuit board
- bump
- semiconductor
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
- H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
- H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
- H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81194—Lateral distribution of the bump connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を回路
基板に接合する半導体実装方法、およびその半導体実装
方法により得られる半導体デバイスに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting method for joining a semiconductor element to a circuit board, and a semiconductor device obtained by the semiconductor mounting method.
【０００２】[0002]
【従来の技術】近年、半導体素子を回路基板に実装する
方法としては、半導体素子上に設けたパッド部と回路基
板上に設けた電極を、予め半導体素子のパッド部に形成
したバンプを介して接合する半導体実装方法が用いられ
ていた。またバンプをパッド部に形成する方法としては
ボールボンディング法およびメッキ法等が用いられてい
た。2. Description of the Related Art In recent years, as a method of mounting a semiconductor element on a circuit board, a pad portion provided on the semiconductor element and an electrode provided on the circuit board are connected to each other through a bump previously formed on the pad section of the semiconductor element. A semiconductor mounting method for bonding has been used. As a method of forming bumps on pad portions, a ball bonding method, a plating method, or the like has been used.
【０００３】以下に図５を参照しながら、従来の半導体
実装方法について説明する。A conventional semiconductor mounting method will be described below with reference to FIG.
【０００４】予め半導体素子１のパッド部２上にボール
ボンディング法等によりバンプ３を形成し、この半導体
素子１に形成されたバンプ３を、接合する回路基板４上
の所定の電極５に対向するように位置決めする。次いで
バンプ３を、所定の電極５に超音波振動を加えながら接
触させた後、半導体素子１の背面より加熱ツール７にて
加圧加熱する。この圧力および熱エネルギはバンプ３ま
で伝達して、電極５との接合部９を昇温し、バンプ３を
電極５に拡散させる。これにより半導体素子１のパッド
部２と回路基板４の電極５とを接合させていた。A bump 3 is previously formed on a pad portion 2 of a semiconductor element 1 by a ball bonding method or the like, and the bump 3 formed on the semiconductor element 1 faces a predetermined electrode 5 on a circuit board 4 to be joined. Positioning. Next, the bump 3 is brought into contact with a predetermined electrode 5 while applying ultrasonic vibration, and then the semiconductor element 1 is heated under pressure by a heating tool 7 from the back. The pressure and the heat energy are transmitted to the bump 3, the temperature of the junction 9 with the electrode 5 is increased, and the bump 3 is diffused to the electrode 5. Thus, the pad portion 2 of the semiconductor element 1 and the electrode 5 of the circuit board 4 are joined.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記の
ような半導体実装方法において得られた半導体デバイス
は、下記のような問題が生じていた。However, the semiconductor device obtained by the above-described semiconductor mounting method has the following problems.
【０００６】半導体素子を回路基板に接合する際、半導
体素子に超音波振動を加えながら回路基板の所定の電極
に接触させ、次いで加熱ツールにより加圧加熱するた
め、この接合部はバンプの変形によって、接合部内に強
い応力が発生し、半導体素子のパッド部に過大な負荷と
なり、パッド部にクラック現象を発生させる問題点があ
った。特に砒化ガリウム、インジウムリンの材質により
構成された半導体素子は柔らかくて傷が付きやすく、し
かも、もろくて欠けや割れも生じやすいため、よりクラ
ック現象を発生させていた。この結果、従来の半導体実
装方法において得られる半導体デバイスは、品質の劣化
したものであったり、また製造歩留りの低いものであっ
た。When a semiconductor element is bonded to a circuit board, the semiconductor element is brought into contact with a predetermined electrode of the circuit board while applying ultrasonic vibrations, and then heated under pressure by a heating tool. Also, there is a problem that a strong stress is generated in the joint portion, which causes an excessive load on the pad portion of the semiconductor element and causes a crack phenomenon on the pad portion. Particularly, a semiconductor element made of gallium arsenide or indium phosphide is soft and easily damaged, and is fragile and easily chipped or cracked. As a result, the semiconductor device obtained by the conventional semiconductor mounting method has a deteriorated quality or a low production yield.
【０００７】本発明は上記問題点に鑑み、半導体素子と
回路基板を接合する際、半導体素子に形成したバンプの
変形を最小限にすることで、接合部内の応力を緩和し、
パッド部への負荷を軽減し、かつ接合強度の高い、実装
品質に優れた半導体デバイスを得ることのできる半導体
実装方法を提供することを目的とする。In view of the above problems, the present invention minimizes the deformation of bumps formed on a semiconductor element when joining a semiconductor element and a circuit board, thereby alleviating the stress in the joint.
It is an object of the present invention to provide a semiconductor mounting method capable of reducing a load on a pad portion and obtaining a semiconductor device having high bonding strength and excellent mounting quality.
【０００８】[0008]
【課題を解決するための手段】本発明は上記目的を達成
するために、半導体素子のパッド部上に形成されたバン
プを、回路基板上の電極に接触させた状態で、前記バン
プを加圧加熱することにより、半導体素子を回路基板に
接合する半導体実装方法において、前記電極上の前記バ
ンプの頂部を囲む位置に、複数の基板側バンプを予め形
成し、半導体素子側のバンプを前記複数の基板側バンプ
の内側に接触した状態で前記バンプおよび基板側バンプ
を加圧加熱することにより、半導体素子を回路基板に接
合させることを特徴とする。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method in which a bump formed on a pad portion of a semiconductor element is brought into contact with an electrode on a circuit board, and the bump is pressed. In the semiconductor mounting method of bonding a semiconductor element to a circuit board by heating, a plurality of substrate-side bumps are formed in advance at positions surrounding the tops of the bumps on the electrodes, and the plurality of bumps on the semiconductor element are connected to the plurality of bumps. The semiconductor element is bonded to the circuit board by pressurizing and heating the bump and the substrate-side bump while being in contact with the inside of the substrate-side bump.
【０００９】また、半導体素子側に形成したバンプの材
質と、回路基板側に形成した基板側バンプの材質が異な
ることを特徴とし、さらに前記基板側バンプが前記バン
プの一箇所に対し、少なくとも三箇所以上において、前
記バンプの頂部を囲むように形成されることを特徴とす
る。Further, the material of the bump formed on the semiconductor element side and the material of the substrate side bump formed on the circuit board side are different from each other. It is characterized in that it is formed so as to surround the top of the bump at a location or more.
【００１０】本発明によれば、予め半導体素子にバンプ
を形成し、なおかつ回路基板においても、予め基板側バ
ンプを形成している。このような構成を備えた半導体素
子と回路基板とを接合する際、この接合部において、バ
ンプと基板側バンプとが互いに金属拡散して接合してな
る半導体デバイスを得ることができる。According to the present invention, a bump is formed on a semiconductor element in advance, and a substrate-side bump is also formed on a circuit board in advance. When a semiconductor element having such a configuration is joined to a circuit board, a semiconductor device can be obtained in which the bump and the board-side bump are metal-diffused and joined at the joint.
【００１１】上記のような本発明の半導体デバイスの接
合部は、従来の半導体実装方法において得られる半導体
デバイスの接合部と比較すると、基板側バンプはバンプ
の頂部を囲むように形成されているため、バンプと基板
側バンプは嵌合構造を形成しており、垂直方向のみなら
ず水平方向に対しても、強固な接合を得ることができ、
また半導体素子と回路基板との距離（接合部の大きさ）
を基板側バンプを有していることにより大とすることが
できる結果、半導体素子と回路基板との間の熱膨張率の
差によって生ずる接合部の変形による応力が緩和され、
半導体素子のパッド部にかかる負荷が軽減される。In the above-described junction of the semiconductor device of the present invention, the substrate-side bump is formed so as to surround the top of the bump, as compared with the junction of the semiconductor device obtained by the conventional semiconductor mounting method. , The bumps and the board-side bumps form a fitting structure, so that not only in the vertical direction but also in the horizontal direction, a strong joint can be obtained,
The distance between the semiconductor element and the circuit board (the size of the joint)
As a result, the stress due to the deformation of the joint caused by the difference in the coefficient of thermal expansion between the semiconductor element and the circuit board is reduced,
The load on the pad portion of the semiconductor element is reduced.
【００１２】[0012]
【発明の実施の形態】以下に本発明の実施形態を図１〜
図４に基づいて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.
This will be described in detail with reference to FIG.
【００１３】図１の（ａ）（ｂ）は本実施形態の半導体
実装方法によって得られる半導体デバイスの構成を示し
たものである。FIGS. 1A and 1B show the configuration of a semiconductor device obtained by the semiconductor mounting method of the present embodiment.
【００１４】図１において、１は半導体素子、２はパッ
ド部、３はバンプ、４は回路基板、５は電極、６は基板
側バンプ、７は加熱ツール、８は接合部、１０は前記バ
ンプ３の頂部である。In FIG. 1, 1 is a semiconductor device, 2 is a pad portion, 3 is a bump, 4 is a circuit board, 5 is an electrode, 6 is a substrate side bump, 7 is a heating tool, 8 is a bonding portion, and 10 is the bump. 3 is the top.
【００１５】次にこれらの基本構成のもとに、本実施形
態の半導体実装方法について説明する。Next, a semiconductor mounting method according to this embodiment will be described based on these basic configurations.
【００１６】半導体素子１を回路基板４上に接合させる
半導体実装方法としては、図２に示すように、半導体素
子１のパッド部２上に、予めボールボンディング法など
によりバンプ３を形成する。また図３に示すように、前
記バンプ３を接合する回路基板４の所定の電極５におい
ても、予めボールボンディング法などにより基板側バン
プ６を形成する。このとき、基板側バンプ６の形成状態
は、図１の（ｂ）に示すように、半導体素子１のパッド
部２上に形成されたバンプ３の一箇所に対して、回路基
板４の所定の電極５に形成された基板側バンプ６が、少
なくとも三箇所以上（図示例では三箇所）において前記
バンプ３の頂部１０を囲むように形成する。またバンプ
３と基板側バンプ６との材質は各々異なる材質で形成さ
れている。この材質に関しては、詳しくは後述する。As a semiconductor mounting method for bonding the semiconductor element 1 to the circuit board 4, as shown in FIG. 2, bumps 3 are previously formed on the pad portions 2 of the semiconductor element 1 by a ball bonding method or the like. Further, as shown in FIG. 3, the substrate-side bumps 6 are also formed in advance on the predetermined electrodes 5 of the circuit board 4 to which the bumps 3 are joined by a ball bonding method or the like. At this time, the formation state of the substrate-side bumps 6 is such that, as shown in FIG. 1B, a predetermined position of the circuit board 4 corresponds to one position of the bumps 3 formed on the pad portions 2 of the semiconductor element 1. The substrate-side bumps 6 formed on the electrodes 5 are formed so as to surround the tops 10 of the bumps 3 at least at three or more places (three places in the illustrated example). The materials of the bumps 3 and the substrate-side bumps 6 are made of different materials. This material will be described later in detail.
【００１７】このように形成された半導体素子１のバン
プ３を図４に示すように、接合する回路基板４側に形成
した基板側バンプ６に対向するように位置決めする。次
いで半導体素子１に回路基板４の所定の電極５に接触さ
せた後、半導体素子１の背面より加熱ツール７にて加圧
加熱する。この圧力および熱エネルギはバンプ３および
基板側バンプ６に伝達して、電極５との接合部８を昇温
し、バンプ３および基板側バンプ６を拡散させる。これ
により半導体素子１のパッド部２と回路基板４の電極５
とを接合することができる。The bumps 3 of the semiconductor element 1 thus formed are positioned so as to face the board-side bumps 6 formed on the circuit board 4 to be joined, as shown in FIG. Next, after the semiconductor element 1 is brought into contact with a predetermined electrode 5 of the circuit board 4, the semiconductor element 1 is heated under pressure by a heating tool 7 from the back surface of the semiconductor element 1. This pressure and heat energy are transmitted to the bumps 3 and the substrate-side bumps 6 to raise the temperature of the junction 8 with the electrodes 5 and diffuse the bumps 3 and the substrate-side bumps 6. Thus, the pad portion 2 of the semiconductor element 1 and the electrode 5 of the circuit board 4
And can be joined.
【００１８】次に本実施形態のバンプ３と基板側バンプ
６の材質について説明する。Next, the materials of the bumps 3 and the substrate-side bumps 6 of the present embodiment will be described.
【００１９】まず基板側バンプ６の材質は純度９９．９
９％の高純度金（Ａｕ）による金属ワイヤより形成し
た。このようにして形成された基板側バンプ６の硬度
は、マイクロビッカース硬度計において計測すると、指
示値８０が得られた。First, the material of the substrate-side bump 6 has a purity of 99.9.
It was formed from a metal wire of 9% high-purity gold (Au). The hardness of the substrate-side bumps 6 thus formed was measured with a micro-Vickers hardness meter, and the indicated value 80 was obtained.
【００２０】次に半導体素子１側のバンプ３の材質は、
純度９９．９９％の高純度金（Ａｕ）にパラジウムを１
％程度添加した高張力金属ワイヤより形成した。このよ
うにして形成されたバンプ３の硬度はマイクロビッカー
ス硬度計において計測すると、指示値９０が得られた。Next, the material of the bump 3 on the semiconductor element 1 side is
Palladium on high purity gold (Au) with 99.99% purity
% Of a high tensile metal wire. The hardness of the bump 3 thus formed was measured with a micro-Vickers hardness meter, and an indicated value 90 was obtained.
【００２１】このようにバンプ３と基板側バンプ６を各
々異なる材質で形成することにより、硬度差を設けるこ
とができる。これにより半導体素子１と回路基板４を接
合する際、接合部８における回路基板４側の基板側バン
プ６が半導体素子１側のバンプ３より低硬度のため、超
音波振動を加える際に生じる負荷を吸収する作用が働
く。さらに、加圧加熱を加える際、半導体素子１の熱膨
張率と回路基板４の熱膨張率の差により生じる負荷にお
いても、緩和することができ半導体素子１のパッド部２
への負荷の集中を防止して、パッド部２に生じるクラッ
クを防ぐことができる。これにより、半導体素子１の材
質としてシリコンだけでなく、機械的強度の低い砒化ガ
リウムやインジウムリン等の材質により構成された半導
体素子１に対しても有効である。By forming the bumps 3 and the substrate-side bumps 6 from different materials in this way, a difference in hardness can be provided. As a result, when the semiconductor element 1 and the circuit board 4 are joined, since the substrate-side bumps 6 on the circuit board 4 side at the joints 8 have a lower hardness than the bumps 3 on the semiconductor element 1 side, a load generated when ultrasonic vibration is applied. The action of absorbing works. Furthermore, when applying pressure and heating, the load caused by the difference between the coefficient of thermal expansion of the semiconductor element 1 and the coefficient of thermal expansion of the circuit board 4 can be reduced, and the pad portion 2 of the semiconductor element 1 can be reduced.
It is possible to prevent the concentration of the load on the pad portion 2 and to prevent cracks generated in the pad portion 2. This is effective not only for the semiconductor element 1 made of a material such as gallium arsenide or indium phosphide having low mechanical strength but also for the semiconductor element 1 made of a material having a low mechanical strength.
【００２２】本発明は上記の実施形態に示すほか種々の
態様に構成することができる。例えば、本実施形態にお
いて、ボールボンディング法を用いてバンプ３および基
板側バンプ６を形成したが、メッキ法を用いても本実施
形態と同様の効果を得ることができる。また本実施形態
において、バンプおよび基板側バンプを形成する際、バ
ンプまたは基板側バンプのどちらか一方、もしくは双方
に、高さを一定化させるレベリング工程あるいはフラッ
タニング工程を施しておくと、より効果的である。The present invention can be configured in various modes in addition to the embodiments described above. For example, in the present embodiment, the bumps 3 and the substrate-side bumps 6 are formed by using the ball bonding method. However, the same effect as in the present embodiment can be obtained by using the plating method. Further, in the present embodiment, when forming the bump and the substrate-side bump, it is more effective to perform a leveling step or a flattening step to make the height of one or both of the bump and the substrate-side bump constant. It is a target.
【００２３】[0023]
【発明の効果】本発明によれば、接合強度が大で、クラ
ック現象の生じにくい高品質な半導体デバイスを得るこ
とのできる半導体実装方法を実現できる。According to the present invention, it is possible to realize a semiconductor mounting method capable of obtaining a high-quality semiconductor device having high bonding strength and hardly causing a crack phenomenon.
【図１】（ａ）本発明による半導体実装方法において得
られる半導体デバイスの断面図である。 （ｂ）本発明による半導体実装方法において接合位置を
示す斜視図である。FIG. 1A is a cross-sectional view of a semiconductor device obtained by a semiconductor mounting method according to the present invention. FIG. 4B is a perspective view showing a bonding position in the semiconductor mounting method according to the present invention.
【図２】（ａ）半導体素子の断面図である。 （ｂ）半導体素子上にバンプを形成した断面図である。FIG. 2A is a cross-sectional view of a semiconductor device. (B) It is sectional drawing which formed the bump on the semiconductor element.
【図３】（ａ）回路基板の断面図である。 （ｂ）本発明による回路基板上に基板側バンプを形成し
た断面図である。FIG. 3A is a cross-sectional view of a circuit board. FIG. 3B is a cross-sectional view illustrating a substrate-side bump formed on a circuit board according to the present invention.
【図４】半導体素子を回路基板に接合するプロセスを示
す図である。FIG. 4 is a view showing a process of joining a semiconductor element to a circuit board.
【図５】従来の半導体実装方法において得られる半導体
デバイスの断面図である。FIG. 5 is a sectional view of a semiconductor device obtained by a conventional semiconductor mounting method.
１ 半導体素子 ２ パッド部 ３ バンプ ４ 回路基板 ５ 電極 ６ 基板側バンプ ７ 加熱ツール ８ 接合部 １０ 頂部 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Pad part 3 Bump 4 Circuit board 5 Electrode 6 Substrate side bump 7 Heating tool 8 Joining part 10 Top part
Claims (4)
ンプを、回路基板上の電極に接触させた状態で、前記バ
ンプを加圧加熱することにより、半導体素子を回路基板
に接合する半導体実装方法において、前記電極上の前記
バンプの頂部を囲む位置に、複数の基板側バンプを予め
形成し、半導体素子側のバンプを前記複数の基板側バン
プの内側に接触した状態で前記バンプおよび基板側バン
プを加圧加熱することにより、半導体素子を回路基板に
接合させることを特徴とする半導体実装方法。1. A semiconductor package for joining a semiconductor element to a circuit board by pressing and heating the bump formed on a pad portion of the semiconductor element in contact with an electrode on the circuit board. In the method, a plurality of substrate-side bumps are previously formed at positions surrounding the tops of the bumps on the electrode, and the bumps on the substrate and the semiconductor element-side bumps are in contact with the inside of the plurality of substrate-side bumps. A semiconductor mounting method, wherein a semiconductor element is joined to a circuit board by pressurizing and heating a bump.
と、回路基板側に形成した基板側バンプの材質が異なる
ことを特徴とする請求項１記載の半導体実装方法。2. The semiconductor mounting method according to claim 1, wherein the material of the bump formed on the semiconductor element side is different from the material of the substrate-side bump formed on the circuit board side.
半導体素子側に形成したバンプの一箇所に対し、少なく
とも三箇所以上において、前記バンプの頂部を囲むよう
に形成されることを特徴とする請求項１または２記載の
半導体実装方法。3. A board-side bump formed on a circuit board side,
3. The semiconductor mounting method according to claim 1, wherein at least three or more positions of the bump formed on the semiconductor element side are formed so as to surround the top of the bump.
体実装方法を用いて得られる半導体デバイス。4. A semiconductor device obtained by using the semiconductor mounting method according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23797399A JP4165970B2 (en) | 1999-08-25 | 1999-08-25 | Semiconductor mounting method and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23797399A JP4165970B2 (en) | 1999-08-25 | 1999-08-25 | Semiconductor mounting method and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001068509A true JP2001068509A (en) | 2001-03-16 |
| JP4165970B2 JP4165970B2 (en) | 2008-10-15 |
Family
ID=17023227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23797399A Expired - Fee Related JP4165970B2 (en) | 1999-08-25 | 1999-08-25 | Semiconductor mounting method and semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP4165970B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210591A (en) * | 2005-01-27 | 2006-08-10 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus and its manufacturing method |
| JP2006318974A (en) * | 2005-05-10 | 2006-11-24 | Toshiba Components Co Ltd | Semiconductor device using bump structure and its manufacturing method |
| JP2007043065A (en) * | 2005-06-28 | 2007-02-15 | Fujitsu Ltd | Semiconductor device |
| JP2007266555A (en) * | 2006-03-30 | 2007-10-11 | Denso Corp | Manufacturing method for bump bonding laminate |
| JP2007324386A (en) * | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | Semiconductor device, and its manufacturing method |
| JP2018195673A (en) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | Bump and forming method thereof, and substrate |
| WO2021261013A1 (en) * | 2020-06-23 | 2021-12-30 | 日立Astemo株式会社 | Electronic control device and method for manufacturing electronic control device |
-
1999
- 1999-08-25 JP JP23797399A patent/JP4165970B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210591A (en) * | 2005-01-27 | 2006-08-10 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus and its manufacturing method |
| JP4573657B2 (en) * | 2005-01-27 | 2010-11-04 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006318974A (en) * | 2005-05-10 | 2006-11-24 | Toshiba Components Co Ltd | Semiconductor device using bump structure and its manufacturing method |
| JP2007043065A (en) * | 2005-06-28 | 2007-02-15 | Fujitsu Ltd | Semiconductor device |
| JP2007266555A (en) * | 2006-03-30 | 2007-10-11 | Denso Corp | Manufacturing method for bump bonding laminate |
| JP4661657B2 (en) * | 2006-03-30 | 2011-03-30 | 株式会社デンソー | Bump bonded body manufacturing method |
| JP2007324386A (en) * | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | Semiconductor device, and its manufacturing method |
| JP2018195673A (en) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | Bump and forming method thereof, and substrate |
| WO2021261013A1 (en) * | 2020-06-23 | 2021-12-30 | 日立Astemo株式会社 | Electronic control device and method for manufacturing electronic control device |
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| Publication number | Publication date |
|---|---|
| JP4165970B2 (en) | 2008-10-15 |
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