JP2003197672A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2003197672A
JP2003197672A JP2001392400A JP2001392400A JP2003197672A JP 2003197672 A JP2003197672 A JP 2003197672A JP 2001392400 A JP2001392400 A JP 2001392400A JP 2001392400 A JP2001392400 A JP 2001392400A JP 2003197672 A JP2003197672 A JP 2003197672A
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacturing
substrates
conductive
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001392400A
Other languages
Japanese (ja)
Inventor
Seiya Isozaki
誠也 磯崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2001392400A priority Critical patent/JP2003197672A/en
Publication of JP2003197672A publication Critical patent/JP2003197672A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a disadvantage that an interval, between a semiconductor chip and a chip mounting object, becomes narrower, which is generated when excessive pressure and heat are applied in order to connect connecting portions while absorbing fluctuations of heights of bumps in the flattening process of the connecting portion, which is performed to increase a contact area by making it flat and connecting the connecting portions of both connecting objects to assure good contact conditions at the time of connecting the bumps formed by a wire bonding apparatus. <P>SOLUTION: Projected metal portions 3, 13 are provided on an electrode pad of a semiconductor element 1 and a connecting pad of a chip mounting object 11, and either of projected portions is formed to have a sharp end point, while the other is formed to have a flat end point. Accordingly, positioning accuracy between the projected metal portions can be alleviated and the projected metal portions have allowances to absorb deviations generated at the connecting portions due to the difference of thermal expansion coefficients of the semiconductor element 1 and the chip mounting object 11. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置、特
に、低コストで実現できるフェースダウン実装した半導
体装置及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a face-down mounted semiconductor device which can be realized at low cost and a method for manufacturing the same.

【0002】[0002]

【従来の技術】本発明が関する半導体装置の製造方法で
は、接続対象物の両方に凸型の金属突起と平坦な金属突
起とを設けることが重要な要素の一つとなっておいる。
2. Description of the Related Art In a method of manufacturing a semiconductor device according to the present invention, it is an important factor to provide a convex metal projection and a flat metal projection on both objects to be connected.

【0003】この目的のために通常は図4に示すよう
に、ワイヤーボンディング装置を利用して半導体チップ
61及びチップ被搭載物71に含金バンプ63、73を
それぞれ形成し、含金バンプ同士を対向させフリップチ
ップボンディングをする。フリップチップボンディング
は常温から200℃までで行われ、両側の含金バンプは
あらかじめフラットニング処理をしてもよい。このよう
な構成で、被搭載物に半導体チップを用いチップ間の間
隙に封止材を充填させたチップオンチップ構造体の製造
方法や、被搭載物に基板を用いチップ間の間隙に封止材
を充填させたチップオンボード構造体の製造方法という
手法が採用されている。
For this purpose, usually, as shown in FIG. 4, a wire bonding device is used to form gold-containing bumps 63 and 73 on a semiconductor chip 61 and a chip-to-be-mounted object 71, respectively. Face each other and perform flip chip bonding. Flip chip bonding is performed at room temperature to 200 ° C., and the gold-containing bumps on both sides may be subjected to a flattening process in advance. With such a configuration, a method of manufacturing a chip-on-chip structure in which a semiconductor chip is used as a mounted object and a gap between the chips is filled with a sealing material, and a substrate is mounted as the mounted object and the gap between the chips is sealed. A method called a method of manufacturing a chip-on-board structure filled with a material is adopted.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、この手
法では、ワイヤーボンディング装置で形成したバンプ同
士を接続する際、良好な接続を得る為には接続対象物の
両方の接続部を平坦にして接合する際の接触面積を増や
すために接続部のフラットニング処理が必要である。接
続部をフラットニング処理すると、バンプ間の高さばら
つきを吸収して接続部同志を接続させるには過度の加圧
と加熱が必要となり、その結果半導体チップとチップ被
搭載物との間隙が狭くなると言う不具合が生じる。もう
少し詳細に説明すると、次のようになる。
However, in this method, when the bumps formed by the wire bonding apparatus are connected to each other, both connection parts of the connection object are flattened and bonded in order to obtain a good connection. In order to increase the contact area at the time, it is necessary to perform a flattening process on the connection part. When the connection part is flattened, excessive pressure and heating are required to absorb the height variation between the bumps and connect the connection parts. As a result, the gap between the semiconductor chip and the chip mounted object becomes narrow. There will be a problem. More detailed explanation is as follows.

【0005】理想的なフラットニング処理であればバン
プの高さはすべて同一となるが、実際に製造されたバン
プに対してこのような処置をする際、例えば、2枚の平
板を用意し片側の板の上にチップを載せ、もう一方の板
を下降させチップ上のバンプをフラットニングする場
合、板の平面度は数μm程度の公差があり,2枚の平板
の平行度にも数μm程度の公差がある。結果として,一
番高いバンプと低いバンプとでは数μm(経験的には1
0mm四方の面積に渡って形成されたバンプの高さの差
が最大5μm程度)の差を生じる.この現象は接合させ
る両側の接続対象物のバンプに対して生じることであ
り、最悪の組合わせとして、接続対象物の最も高いバン
プ同士と最も低いバンプ同士が対向して接続される場合
には、高いバンプ同士が接触した時点で低いバンプ同士
の間隙は十数μmにもなる。
In the case of an ideal flattening process, all bumps have the same height, but when such a process is applied to an actually manufactured bump, for example, two flat plates are prepared and one side is prepared. When the chip is placed on the plate and the other plate is lowered to flatten the bumps on the chip, the flatness of the plate has a tolerance of several μm, and the parallelism of the two flat plates is several μm. There is some tolerance. As a result, the highest bump and the lowest bump are several μm (empirically 1
The difference in height of bumps formed over an area of 0 mm square is about 5 μm at maximum). This phenomenon occurs with respect to the bumps of the connection objects on both sides to be joined, and in the worst combination, when the highest bumps and the lowest bumps of the connection objects are connected to face each other, When the high bumps come into contact with each other, the gap between the low bumps becomes as much as ten and several μm.

【0006】したがって、この間隙をなくし低いバンプ
同士を接続させるためには高いバンプを十数μm潰す必
要がある。よって、既にバンプにレベリングを実施して
接続部を平坦にして接合する際の接触面積を増やしてあ
る場合には、レベリング前の接触面積が小さい時のバン
プに比べると過度の加圧と加熱が必要となる.また、フ
ラットニング処理されたバンプ同士を用いた場合、半導
体チップとチップ被搭載物との間隙に入れる液状封止材
をあらかじめ供給する方法や、フィルム状の封止材を用
いる方法には適さない。しかし、ワイヤーボンディング
装置で形成したバンプをフラットニング処理せずに接続
させる場合、バンプ先端が数μm程度の径となるため、
これらを精度よく位置合わせすることは困難を極める。
従って、フラットニング処理が必要となるが、高さ精度
よく処理したとしても数μm程度のばらつきは生じてし
まうため、これらの高さばらつきを吸収して接続させる
には過度の加圧と加熱は必要となる。その結果、半導体
チップとチップ被搭載物との間隙が狭くなると言う不具
合が生じる。また、フラットニング処理されたバンプ同
士を用いた場合、バンプの変形がほとんど無いために変
形による封止材排除の効果は期待できない。すなわち、
フラットニング処理された接合されるバンプ同士に着目
した場合、バンプの接合面の平行度に関してはバンプの
直径が数十μm程度であるため、ほとんど平行とみなせ
る。したがって,このような接合されるバンプ間に樹脂
が一度入り込んでしまうと、単純に片側の接続対象物を
他方の接続対象物に対して押し込むだけではこの樹脂を
接合されるバンプ間から排除することは困難である。従
って、接続対象物を接合する前に接続対象物のバンプ同
士にフラットニング処理を行う方法は、液状封止樹脂を
あらかじめ供給する方法や、フィルム状の封止樹脂を用
いる方法には適さない。
Therefore, in order to eliminate this gap and connect the low bumps to each other, it is necessary to crush the high bumps by several tens of μm. Therefore, if the bumps have already been leveled to increase the contact area when flattening and joining the connection parts, excessive pressure and heating will occur compared to the bumps when the contact area before leveling is small. It is necessary. Further, when the bumps subjected to the flattening treatment are used, it is not suitable for a method of previously supplying a liquid encapsulating material to be put into a gap between the semiconductor chip and the chip mounted object or a method of using a film encapsulating material . However, when connecting the bumps formed by the wire bonding device without performing the flattening process, the tip of the bump has a diameter of about several μm.
Accurately aligning these is extremely difficult.
Therefore, a flattening process is required, but even if the height is accurately processed, a variation of about several μm occurs. Therefore, excessive pressure and heating are required to absorb the variation in height and connect. Will be needed. As a result, there arises a problem that the gap between the semiconductor chip and the chip mounted object becomes narrow. Further, when the bumps subjected to the flattening process are used, since the bumps are hardly deformed, the effect of eliminating the sealing material due to the deformation cannot be expected. That is,
When attention is paid to the bumps to be joined that have been subjected to the flattening process, the parallelism of the joint surfaces of the bumps can be regarded as almost parallel because the diameter of the bump is several tens of μm. Therefore, once the resin has entered between the bumps to be joined, the resin can be excluded from the bumps to be joined by simply pushing the connecting object on one side against the connecting object on the other side. It is difficult. Therefore, the method of performing the flattening process on the bumps of the connection target before the connection of the connection target is not suitable for the method of previously supplying the liquid sealing resin or the method of using the film-shaped sealing resin.

【0007】本発明の主な目的の一つは、金属突起の高
さバラツキを吸収し、さらに間隙を広く取ることで接続
の信頼性を向上させた半導体装置を提供することにあ
る。
One of the main objects of the present invention is to provide a semiconductor device which improves the reliability of connection by absorbing the height variation of the metal projections and further widening the gap.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、第1の導電性凸部を有する第1の基板と第2
の導電性凸部を有する第2の基板とを前記第1及び第2
の導電性凸部を互いに接合させることにより前記第1及
び第2の基板を互いに対向配置させる半導体装置の製造
方法であって、前記第1の導電性凸部は頂上面が平坦な
形状に、前記第2の導電性凸部は先端が突出する形状に
それぞれ形成され、前記第1及び第2の導電性凸部の接
合が、前記第2の導電性凸部の先端を前記第1の導電性
凸部の平坦な頂上面内に平面的に収まる位置に前記第1
及び第2の基板を配置し、その後、前記第1及び第2の
基板の対向間隔が縮まる方向に前記第1及び第2の基板
のうち少なくとも一方の基板を加圧することにより行わ
れることを特徴とする。本発明の半導体装置は次のよう
な好適な適用形態を有している。
A method of manufacturing a semiconductor device according to the present invention comprises a first substrate having a first conductive protrusion and a second substrate.
And a second substrate having a conductive convex portion of the first and second
Is a method for manufacturing a semiconductor device in which the first and second substrates are arranged to face each other by bonding the conductive protrusions to each other, wherein the first conductive protrusion has a flat top surface, Each of the second conductive protrusions is formed in a shape with a protruding tip, and the first conductive protrusion and the second conductive protrusion are joined to each other such that the tip of the second conductive protrusion is connected to the first conductive protrusion. The first protrusion is placed at a position that is planarly accommodated in the flat top surface of the convex portion.
And the second substrate are arranged, and thereafter, at least one of the first and second substrates is pressed in a direction in which the facing distance between the first and second substrates is reduced. And The semiconductor device of the present invention has the following suitable application modes.

【0009】まず第1に、前記第2の導電性凸部の硬度
が、前記第1の導電性凸部の硬度よりも高い。
First, the hardness of the second conductive protrusion is higher than the hardness of the first conductive protrusion.

【0010】第2に、前記第1及び第2の基板のうち、
少なくとも一方の基板は半導体基板である。
Secondly, of the first and second substrates,
At least one of the substrates is a semiconductor substrate.

【0011】第3に、 前記第1及び第2の導電性凸部
の接合の後に、前記第1の導前記第1及び第2の基板の
間に樹脂を注入し、硬化させることにより前記樹脂が前
記第1の導前記第1及び第2の基板の間を封止する。
Thirdly, after the first and second conductive convex portions are joined, a resin is injected between the first conductive substrate and the second conductive substrate to cure the resin. Seals between the first and second substrates.

【0012】第4に、前記第1及び第2の導電性凸部の
接合の前に、前記第1の導前記第1及び第2の基板のう
ち、少なくとも一方の基板の導電性凸部よりも基板の内
側に樹脂が形成され、前記第1及び第2の導電性凸部の
接合が行われることにより前記樹脂が前記第1の導前記
第1及び第2の基板の間を封止する。
Fourth, before joining the first and second conductive convex portions, the conductive convex portion of at least one of the first conductive substrate and the second conductive substrate is removed. Also, a resin is formed inside the substrate, and the resin seals between the first and second substrates by bonding the first and second conductive protrusions. .

【0013】第5に、前記第1の導電性凸部はメッキ法
により、前記第2の導電性凸部はボールボンディング法
により、それぞれ形成される請求項1乃至5のいずれか
一に記載の半導体装置の製造方法。
Fifth, the first conductive convex portion is formed by a plating method, and the second conductive convex portion is formed by a ball bonding method, respectively. Manufacturing method of semiconductor device.

【0014】第6に、前記第1及び第2の基板のうち少
なくとも一方の基板を加圧する工程が、加熱を伴う加圧
である。
Sixth, the step of pressurizing at least one of the first and second substrates is pressurization involving heating.

【0015】第7に、前記第1及び第2の基板のうち少
なくとも一方の基板を加圧する工程が、超音波接続を伴
う加圧である。
Seventh, the step of pressurizing at least one of the first and second substrates is pressurization involving ultrasonic connection.

【0016】[0016]

【発明の実施の形態】本発明の半導体装置の製造方法の
第1の実施形態を図1の製造工程断面図を参照して説明
する。
BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to sectional views of manufacturing steps shown in FIG.

【0017】第1の半導体素子1の電極パッド(図示せ
ず)上にはボールボンディング法により凸型の金属突部
2が形成されており、続いて、金属突部2の頂部形状と
異なる先端が尖った形状の金属突起3が形成されてい
る。一方、第2の半導体素子11の電極パッド(図示せ
ず)上には、ボールボンディング法により凸型の金属突
起を形成し、続いて、金属突起よりも硬い平面板を用い
て金属突起を加圧により平坦化して金属突部13とする
(図1(a))。
A convex metal projection 2 is formed on the electrode pad (not shown) of the first semiconductor element 1 by a ball bonding method, and then a tip different from the top shape of the metal projection 2 is formed. A metal projection 3 having a pointed shape is formed. On the other hand, a convex metal protrusion is formed on the electrode pad (not shown) of the second semiconductor element 11 by a ball bonding method, and then the metal protrusion is added using a flat plate that is harder than the metal protrusion. The metal projection 13 is flattened by pressure (FIG. 1A).

【0018】そして、第1の半導体素子1上の金属突起
3と、第2の半導体素子11の金属突部13とを対向さ
せ位置合わせした後(図1(b))、第1の半導体素子
1及び第2の半導体素子11のいずれか、または、双方
に荷重を印加する(図1(c))。このとき、荷重に加
えて、加熱、超音波のいずれか、もしくは全てを印加
し、金属突起3と金属突部13同士を接続する。
After the metal protrusions 3 on the first semiconductor element 1 and the metal protrusions 13 of the second semiconductor element 11 are opposed to each other and aligned (FIG. 1 (b)), the first semiconductor element is then aligned. A load is applied to either or both of the first and second semiconductor elements 11 (FIG. 1C). At this time, in addition to the load, any or all of heating and ultrasonic waves are applied to connect the metal projections 3 and the metal projections 13 to each other.

【0019】接続完了後に、液状の封止樹脂を第1の半
導体素子1及び第2の半導体素子11の間隙に毛細管現
象を利用して流し込み、封止樹脂14を加熱硬化させる
(図1(d))。
After the connection is completed, the liquid sealing resin is poured into the gap between the first semiconductor element 1 and the second semiconductor element 11 by utilizing the capillary phenomenon to heat and cure the sealing resin 14 (FIG. 1 (d). )).

【0020】この様にして作製した半導体素子は、従来
の1つの半導体素子と同様に扱うことが可能で、この
後、従来の製造方法に従って完成される。
The semiconductor element thus manufactured can be handled in the same manner as one conventional semiconductor element, and then completed by the conventional manufacturing method.

【0021】本実施形態による方法では、頂部が尖った
金属突起3と頂部が平坦な金属突部13とを組合せて用
いているため、金属突起3及び金属突部13間の位置合
わせにおいて、金属突部13が金属突起3に対して大き
な的となり、金属突起3の位置合わせ精度を緩和しても
金属突起3及び金属突部13間の良好な接続が得られる
という利点がある。
In the method according to the present embodiment, since the metal projection 3 having a pointed top and the metal projection 13 having a flat top are used in combination, the metal projection 3 and the metal projection 13 are aligned with each other. There is an advantage that the projection 13 becomes larger than the metal projection 3 and good connection between the metal projection 3 and the metal projection 13 can be obtained even if the positioning accuracy of the metal projection 3 is relaxed.

【0022】また、頂部が尖った金属突起3を用いるこ
とで自身の突起の高さばらつき及び接続相手の金属突部
13の高さばらつきを尖った先端部の変形で吸収するこ
とが可能となるため、全体として、第1の半導体素子1
及び第2の半導体素子11間の接合金属の高さバラツキ
を吸収して第1の半導体素子1及び第2の半導体素子1
1間の安定した接続を得ることが出来る。
Further, by using the metal protrusion 3 having a pointed top, it is possible to absorb the height variation of the protrusion itself and the height variation of the metal protrusion 13 of the connection partner by the deformation of the pointed tip. Therefore, as a whole, the first semiconductor element 1
The first semiconductor element 1 and the second semiconductor element 1 by absorbing the height variation of the joining metal between the second semiconductor element 11 and the second semiconductor element 11.
A stable connection between 1 can be obtained.

【0023】上記実施形態において、金属突部13はメ
ッキ法を用いて形成してもよい。
In the above embodiment, the metal protrusion 13 may be formed by using a plating method.

【0024】さらに、頂部が尖った金属突起3の硬度を
金属突部13よりも高くすることで、金属突起3の頂部
を金属突部13の平坦部に食い込ませることが可能とな
り、アンカー効果を有する安定した接続を得ることが出
来る。金属突部13をメッキ法によって形成した場合
は、その硬さをアニール処理により調整することが可能
であり、硬度も低いものを得ることが出来る。
Further, by making the hardness of the metal projection 3 having a sharp top higher than that of the metal projection 13, it is possible to make the top of the metal projection 3 bite into the flat portion of the metal projection 13 and to provide an anchor effect. A stable connection can be obtained. When the metal protrusion 13 is formed by the plating method, the hardness thereof can be adjusted by the annealing treatment, and the one having a low hardness can be obtained.

【0025】次に、本発明の半導体装置の製造方法の第
2の実施形態を図2の製造工程断面図を参照して説明す
る。
Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG.

【0026】前実施形態では、本発明を半導体素子同士
の接続に適用したが、本実施形態では、半導体素子と配
線基板との接続についても適用したものである。
In the previous embodiment, the present invention was applied to the connection between semiconductor elements, but in the present embodiment, it is also applied to the connection between a semiconductor element and a wiring board.

【0027】半導体素子21の電極パッド(図示せず)
上にはメッキ法を用いて平坦な金属突部22が形成され
ており、配線基板31の配線パッド35上には、ボール
ボンディング法により、まず頂部の平坦な金属突部32
が形成され、金属突部32よりも硬い先端の尖った金属
突起33が形成されている。また、半導体素子21と反
対側の配線基板31に接続プラグ36を介して裏面パッ
ド37が設けられている。
Electrode pads of the semiconductor element 21 (not shown)
The flat metal projections 22 are formed on the top of the wiring board 35 on the wiring board 31 by a ball bonding method.
Is formed, and a metal projection 33 having a sharp tip, which is harder than the metal projection 32, is formed. A back surface pad 37 is provided on the wiring board 31 on the side opposite to the semiconductor element 21 via a connection plug 36.

【0028】次に、半導体素子21上の金属突部23と
配線基板31上の金属突起33とを対向させ位置合わせ
した後(図2(a))、半導体素子21及び配線基板3
1のいずれか、または、双方に荷重を印加する。このと
き、荷重に加えて、加熱、超音波のいずれか、もしくは
全てを印加し、金属突部23と金属突起33同士を接続
する。
Next, after the metal projections 23 on the semiconductor element 21 and the metal projections 33 on the wiring board 31 are opposed to each other and aligned (FIG. 2A), the semiconductor element 21 and the wiring board 3 are aligned.
The load is applied to either or both of No. 1 and No. 1. At this time, in addition to the load, any or all of heating and ultrasonic waves are applied to connect the metal projections 23 and the metal projections 33.

【0029】接続完了後に、液状の封止樹脂34を半導
体素子21及び配線基板31の間隙に毛細管現象を利用
して流し込み、封止樹脂34を加熱硬化させる(図2
(b))。
After the connection is completed, the liquid sealing resin 34 is poured into the gap between the semiconductor element 21 and the wiring board 31 by utilizing the capillary phenomenon to heat and cure the sealing resin 34 (FIG. 2).
(B)).

【0030】その後、例えば、半導体素子21と反対側
の配線基板31に接続プラグ36を介して裏面パッド3
7及び外部端子38を形成し半導体装置を得る。
Thereafter, for example, the back surface pad 3 is provided on the wiring substrate 31 on the side opposite to the semiconductor element 21 via the connection plug 36.
7 and the external terminal 38 are formed to obtain a semiconductor device.

【0031】従って、この半導体素子21と配線基板3
1との接続では、配線基板31の配線パッド35上に金
属突部及び金属突起を形成するため、配線パッド35の
表面仕上げに例えばフラッシュ金メッキのような安価な
メッキを採用しても半導体素子21と配線基板31との
間の良好な接続を得ることが可能となる。
Therefore, the semiconductor element 21 and the wiring board 3 are
In the connection with 1, the metal projections and the metal projections are formed on the wiring pads 35 of the wiring board 31, so that even if inexpensive plating such as flash gold plating is adopted for the surface finish of the wiring pads 35, the semiconductor element 21 is formed. It is possible to obtain a good connection between the wiring board 31 and the wiring board 31.

【0032】しかも、配線基板31の配線パッド35上
に金属突部を形成するため、半導体素子21と配線基板
31との間隙が広くなる。従って、半導体素子21と配
線基板31との熱膨張差から生じ接続部にかかる応力を
緩和することが可能となり接続信頼性が向上するという
効果も得られる。
In addition, since the metal protrusion is formed on the wiring pad 35 of the wiring board 31, the gap between the semiconductor element 21 and the wiring board 31 is widened. Therefore, it is possible to relieve the stress applied to the connection portion due to the difference in thermal expansion between the semiconductor element 21 and the wiring board 31, and the connection reliability is improved.

【0033】次に、本発明の半導体装置の製造方法の第
3の実施形態を図3の製造工程断面図を参照して説明す
る。本実施形態は、封止樹脂をあらかじめ接続対象物の
一方に供給しておいた上で接続対象物を接合させる場合
を示したものである。
Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG. The present embodiment shows a case where the sealing resin is supplied to one of the connection objects in advance and then the connection objects are joined.

【0034】第1の半導体素子41の電極パッド(図示
せず)上にはボールボンディング法により凸型の金属突
部42が形成されており、続いて、金属突部42の頂部
形状と異なる先端が尖った形状の金属突起43が形成さ
れている。一方、第2の半導体素子51の電極パッド
(図示せず)の電極パッド上にはメッキ法を用いて平坦
な金属突部53が形成されている。
A convex metal projection 42 is formed on the electrode pad (not shown) of the first semiconductor element 41 by a ball bonding method, and subsequently, a tip different from the top shape of the metal projection 42 is formed. A metal projection 43 having a pointed shape is formed. On the other hand, a flat metal projection 53 is formed on the electrode pad (not shown) of the second semiconductor element 51 by a plating method.

【0035】次に、第2の半導体素子51上に封止樹脂
54を塗布した後、第1の半導体素子41上の金属突起
43と、第2の半導体素子上の金属突部53とを対向さ
せ位置合わせした後(図3(a))、第1の半導体素子
41及び第2の半導体素子51のいずれか、または、双
方に荷重を印加し、金属突起43と金属突部53同士を
接続すると同時に封止樹脂54を加熱硬化させる。この
際、超音波を併用してもよい。必要であればこの後さら
に熱を加え、封止樹脂54を完全に硬化させる。
Next, after the sealing resin 54 is applied on the second semiconductor element 51, the metal protrusion 43 on the first semiconductor element 41 and the metal protrusion 53 on the second semiconductor element face each other. And aligning (FIG. 3A), a load is applied to either or both of the first semiconductor element 41 and the second semiconductor element 51 to connect the metal protrusion 43 and the metal protrusion 53 to each other. At the same time, the sealing resin 54 is cured by heating. At this time, ultrasonic waves may be used together. If necessary, heat is further applied thereafter to completely cure the sealing resin 54.

【0036】従って、封止樹脂54をあらかじめ供給す
る以外は上記第1、2の実施形態と同じ構成となり、本
発明の目的が達成される。また、第2の半導体素子の電
極パッド上にはメッキ法を用いて平坦な金属突部が形成
されているので、金属突部の高さ分だけ封止樹脂が金属
突部の表面に這い上がるのを妨げることが出来る。さら
に、先端の尖った金属突起53を用いるので、この先端
部で封止樹脂54を排除しながら第1の半導体素子41
及び第2の半導体素子51を接続させることが出来るた
め,金属突起43と金属突部53との間に封止樹脂54
を挟み込む可能性を著しく低減することが可能であると
いう相乗的な効果を奏する。また、封止樹脂54をフィ
ルム状で供給した場合は、金属突部43表面への樹脂の
這い上がりを妨げることはできないものの、金属突起5
3の先端部で充分に封止樹脂54を排除することが可能
である。
Therefore, the structure is the same as that of the first and second embodiments except that the sealing resin 54 is supplied in advance, and the object of the present invention is achieved. In addition, since the flat metal projection is formed on the electrode pad of the second semiconductor element by using the plating method, the sealing resin creeps up to the surface of the metal projection by the height of the metal projection. Can be prevented. Further, since the metal protrusion 53 having a sharp tip is used, the first semiconductor element 41 is eliminated while the sealing resin 54 is removed at this tip.
Since the second semiconductor element 51 and the second semiconductor element 51 can be connected, the sealing resin 54 is provided between the metal protrusion 43 and the metal protrusion 53.
There is a synergistic effect that it is possible to significantly reduce the possibility of sandwiching. Further, when the sealing resin 54 is supplied in the form of a film, it is not possible to prevent the resin from climbing up to the surface of the metal projection 43, but the metal projection 5
It is possible to sufficiently remove the sealing resin 54 at the tip of 3.

【0037】以上のように、本実施形態では、接続対象
物の一方に形成される接合用のバンプの先端を尖った形
状にすると、この尖った部分は、接合時に横方向にせり
出してくる樹脂を掻き分けながら他方の接続対象物のバ
ンプに突き刺さるので、尖ったバンプの先端ともう一方
のバンプとの間に樹脂は存在しない。
As described above, in the present embodiment, when the tip of the bonding bump formed on one of the objects to be connected has a sharp shape, this sharp portion is a resin protruding laterally at the time of bonding. Since it sticks to the bump of the other connection target while scraping off, the resin does not exist between the tip of the sharp bump and the other bump.

【0038】以上のように、本発明による半導体装置の
製造方法によれば、半導体素子と被搭載物とを金属突起
を介して接続する際に、半導体素子の電極パッド上と被
搭載物の接続パッド上に金属突部を設け、そのいずれか
の突部を先端の尖った形状にし他方を頂部が平坦な形状
として、これらの金属突部同志を接合させて両者の接続
をしている。この金属突部の形状の違いは、金属突部同
士の位置合わせ精度を緩和するという役目を果たす。ま
た、これらの金属突部は、電気的に接続する役目を果た
すと同時に、半導体素子と被搭載物との熱膨張の差によ
り接続部にずれが生じても、そのずれ分を吸収できるだ
けの許容度を有している。
As described above, according to the method of manufacturing a semiconductor device of the present invention, when the semiconductor element and the object to be mounted are connected through the metal projection, the electrode pad of the semiconductor element is connected to the object to be mounted. Metal protrusions are provided on the pads, and one of the protrusions has a sharp tip and the other has a flat top, and these metal protrusions are joined together to connect the two. The difference in the shape of the metal protrusions serves to ease the alignment accuracy between the metal protrusions. Further, these metal protrusions serve to electrically connect, and at the same time, even if the connection portion is displaced due to the difference in thermal expansion between the semiconductor element and the mounted object, it is acceptable to absorb the displacement. Have a degree.

【0039】さらに、金属突部材料の硬度に差を持たせ
ることで、硬い尖った金属突起を柔らかい平坦な金属突
部に食い込ませた構造が得られる。
Furthermore, by providing different hardnesses for the metal projection materials, it is possible to obtain a structure in which hard, pointed metal projections are bitten into a soft flat metal projection.

【0040】従って、位置合わせ精度を緩和することが
可能なため、高い歩留りが得られ、熱膨張による差を緩
和出来るため、高い接続信頼性が得られ、接続箇所が一
方の金属突起が他方の金属突部に食い込んだ形を採って
いるため、接続対象物間の安定した接続が得られるとい
う効果がある。
Therefore, since the alignment accuracy can be relaxed, a high yield can be obtained, and the difference due to thermal expansion can be relaxed, so that a high connection reliability can be obtained, and the metal protrusion at one connection point can be connected to the other metal protrusion at the other. Since it has a shape that digs into the metal protrusion, there is an effect that a stable connection between the objects to be connected can be obtained.

【0041】[0041]

【発明の効果】本発明による半導体装置の製造方法によ
れば、半導体素子と被搭載物とを金属突起を介して接続
する際に、半導体素子の電極パッド上と被搭載物の接続
パッド上に金属突部を設け、そのいずれかの突部を先端
の尖った形状にし他方を頂部が平坦な形状とすることに
より、金属突部同士の位置合わせ精度を緩和することが
できる。また、これらの金属突部は、半導体素子と被搭
載物との熱膨張の差により接続部にずれが生じても、そ
のずれ分を吸収できるだけの許容度を有している。従っ
て、位置合わせ精度の緩和により、高い組立歩留りが得
られ、熱膨張による差を緩和出来るため、高い接続信頼
性が得られる。
According to the method of manufacturing a semiconductor device according to the present invention, when connecting a semiconductor element and an object to be mounted via a metal protrusion, the semiconductor element is mounted on the electrode pad of the semiconductor element and the connection pad of the object to be mounted. By providing the metal protrusions and forming one of the protrusions with a pointed tip and the other with a flat top, the alignment accuracy of the metal protrusions can be eased. Further, these metal protrusions have a tolerance that can absorb the deviation even if the connection portion is deviated due to the difference in thermal expansion between the semiconductor element and the mounted object. Therefore, by relaxing the alignment accuracy, a high assembly yield can be obtained, and the difference due to thermal expansion can be mitigated, so that high connection reliability can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施形態の半導体装置の製造方
法を製造工程順に示す断面図である。
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps.

【図2】本発明の第2の実施形態の半導体装置の製造方
法を製造工程順に示す断面図である。
FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of manufacturing steps.

【図3】本発明の第3の実施形態の半導体装置の製造方
法を製造工程順に示す断面図である。
FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of manufacturing steps.

【図4】従来の半導体装置の製造方法を製造工程順に示
す断面図である。
FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of manufacturing steps.

【符号の説明】[Explanation of symbols]

1、41 第1の半導体素子 2、13、23、32、42、53 金属突部 3、33、43 金属突起 11、51 第2の半導体素子 14、34、54 封止樹脂 21 半導体素子 31 配線基板 35 配線パッド 36 接続プラグ 37 裏面パッド 61 半導体チップ 63、73 含金バンプ 71 チップ被搭載物 1, 41 First semiconductor element 2, 13, 23, 32, 42, 53 Metal protrusion 3, 33, 43 Metal protrusion 11, 51 Second semiconductor element 14, 34, 54 Sealing resin 21 Semiconductor element 31 wiring board 35 wiring pad 36 connection plug 37 Back pad 61 Semiconductor chip 63, 73 Gold bump 71 Chip mounted object

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 第1の導電性凸部を有する第1の基板と
第2の導電性凸部を有する第2の基板とを前記第1及び
第2の導電性凸部を互いに接合させることにより前記第
1及び第2の基板を互いに対向配置させる半導体装置の
製造方法であって、前記第1の導電性凸部は頂上面が平
坦な形状に、前記第2の導電性凸部は先端が突出する形
状にそれぞれ形成され、前記第1及び第2の導電性凸部
の接合が、前記第2の導電性凸部の先端を前記第1の導
電性凸部の平坦な頂上面内に平面的に収まる位置に前記
第1及び第2の基板を配置し、その後、前記第1及び第
2の基板の対向間隔が縮まる方向に前記第1及び第2の
基板のうち少なくとも一方の基板を加圧することにより
行われることを特徴とする半導体装置の製造方法。
1. A first substrate having a first conductive protrusion and a second substrate having a second conductive protrusion are bonded to each other with the first and second conductive protrusions. Is a method for manufacturing a semiconductor device in which the first and second substrates are arranged to face each other, wherein the first conductive protrusion has a flat top surface and the second conductive protrusion has a tip. Are respectively formed in a protruding shape, and the first and second conductive protrusions are joined to each other such that the tips of the second conductive protrusions are located within the flat top surface of the first conductive protrusion. The first and second substrates are arranged in a position that fits in a plane, and then at least one of the first and second substrates is placed in a direction in which the facing distance between the first and second substrates is reduced. A method for manufacturing a semiconductor device, which is performed by applying pressure.
【請求項2】 前記第2の導電性凸部の硬度が、前記第
1の導電性凸部の硬度よりも高い請求項1記載の半導体
装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the hardness of the second conductive protrusion is higher than the hardness of the first conductive protrusion.
【請求項3】 前記第1及び第2の基板のうち、少なく
とも一方の基板は半導体基板である請求項1又は2記載
の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the first and second substrates is a semiconductor substrate.
【請求項4】 前記第1及び第2の導電性凸部の接合の
後に、前記第1の導前記第1及び第2の基板の間に樹脂
を注入し、硬化させることにより前記樹脂が前記第1の
導前記第1及び第2の基板の間を封止する請求項1、2
又は3記載の半導体装置の製造方法。
4. After the first and second conductive convex portions are joined together, a resin is injected between the first conductors and the first and second substrates and cured, so that the resin is cured. The first conductor seals a space between the first and second substrates.
Alternatively, the method for manufacturing a semiconductor device according to the above item 3.
【請求項5】 前記第1及び第2の導電性凸部の接合の
前に、前記第1の導前記第1及び第2の基板のうち、少
なくとも一方の基板の導電性凸部よりも基板の内側に樹
脂が形成され、前記第1及び第2の導電性凸部の接合が
行われることにより前記樹脂が前記第1の導前記第1及
び第2の基板の間を封止する請求項1、2又は3記載の
半導体装置の製造方法。
5. Prior to joining the first and second conductive protrusions, the first conductor is a substrate more than the conductive protrusion of at least one of the first and second substrates. A resin is formed on the inside of the substrate, and the resin seals between the first and second substrates by joining the first and second conductive protrusions. 4. The method for manufacturing a semiconductor device according to 1, 2 or 3.
【請求項6】 前記第1の導電性凸部はメッキ法によ
り、前記第2の導電性凸部はボールボンディング法によ
り、それぞれ形成される請求項1乃至5のいずれか一に
記載の半導体装置の製造方法。
6. The semiconductor device according to claim 1, wherein the first conductive protrusion is formed by a plating method, and the second conductive protrusion is formed by a ball bonding method. Manufacturing method.
【請求項7】 前記第1及び第2の基板のうち少なくと
も一方の基板を加圧する工程が、加熱を伴う加圧である
請求項1乃至6のいずれか一に記載の半導体装置の製造
方法。
7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of pressurizing at least one of the first and second substrates is pressurization accompanied by heating.
【請求項8】 前記第1及び第2の基板のうち少なくと
も一方の基板を加圧する工程が、超音波接続を伴う加圧
である請求項1乃至7のいずれか一に記載の半導体装置
の製造方法。
8. The manufacturing of a semiconductor device according to claim 1, wherein the step of pressurizing at least one of the first and second substrates is pressurization involving ultrasonic connection. Method.
JP2001392400A 2001-12-25 2001-12-25 Method of manufacturing semiconductor device Pending JP2003197672A (en)

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159356A (en) * 2003-11-25 2005-06-16 Ja-Uk Koo Flip chip joining method whose bonding capacity in flip chip packaging process improves, and metal laminate structure of substrate for it
JP2007081417A (en) * 2005-09-13 2007-03-29 Philips Lumileds Lightng Co Llc Interconnection for semiconductor light emitting devices
US7971349B2 (en) 2008-03-26 2011-07-05 Denso Corporation Bump bonding method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159356A (en) * 2003-11-25 2005-06-16 Ja-Uk Koo Flip chip joining method whose bonding capacity in flip chip packaging process improves, and metal laminate structure of substrate for it
JP2007081417A (en) * 2005-09-13 2007-03-29 Philips Lumileds Lightng Co Llc Interconnection for semiconductor light emitting devices
US7971349B2 (en) 2008-03-26 2011-07-05 Denso Corporation Bump bonding method

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