JP3419398B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3419398B2 JP3419398B2 JP2001047868A JP2001047868A JP3419398B2 JP 3419398 B2 JP3419398 B2 JP 3419398B2 JP 2001047868 A JP2001047868 A JP 2001047868A JP 2001047868 A JP2001047868 A JP 2001047868A JP 3419398 B2 JP3419398 B2 JP 3419398B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- semiconductor
- wiring board
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の半導体素子
を配線基板に塔載した半導体装置の製造方法に関するも
のであり、特に、半導体素子どうしの接着性を向上させ
る半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are mounted on a wiring board, and more particularly to a method for manufacturing a semiconductor device for improving the adhesiveness between semiconductor elements. Is.
【０００２】[0002]
【従来の技術】近年、電子機器の小型化の要望から、配
線基板上で半導体素子を積層することによって、配線基
板に対する実装面積を小さくした構造の半導体装置が出
現している。2. Description of the Related Art In recent years, a semiconductor device having a structure in which a mounting area for a wiring board is reduced by stacking semiconductor elements on the wiring board has appeared due to a demand for miniaturization of electronic equipment.
【０００３】以下、従来の半導体装置の製造方法につい
て、図面を用いて説明する。A conventional method of manufacturing a semiconductor device will be described below with reference to the drawings.
【０００４】図３は、従来の半導体装置の製造方法の各
工程を示す断面図である。FIG. 3 is a cross-sectional view showing each step of a conventional semiconductor device manufacturing method.
【０００５】図３（ａ）に示すように、まず、第１の半
導体素子１の電極２に突起状のバンプ３を形成する。As shown in FIG. 3A, first, a bump 3 having a protruding shape is formed on the electrode 2 of the first semiconductor element 1.
【０００６】次に、図３（ｂ）に示すように、バンプ３
が形成された第１の半導体素子１を配線基板４の電極形
成面に対向させ、バンプ３と配線５とを位置合わせした
後、電気的に接続する。そして、第１の半導体素子１と
配線基板４との間に第１の樹脂６を注入する。Next, as shown in FIG.
The first semiconductor element 1 formed with is opposed to the electrode formation surface of the wiring substrate 4, the bump 3 and the wiring 5 are aligned, and then electrically connected. Then, the first resin 6 is injected between the first semiconductor element 1 and the wiring board 4.
【０００７】次に、図３（ｃ）に示すように、第１の樹
脂６を加熱することにより硬化させた後に室温で冷却さ
せると、第１の半導体素子１の熱膨張率と配線基板４の
熱膨張率が異なるために、第１の半導体素子１および配
線基板４は反ってしまう。Next, as shown in FIG. 3C, when the first resin 6 is cured by heating and then cooled at room temperature, the coefficient of thermal expansion of the first semiconductor element 1 and the wiring board 4 are reduced. The first semiconductor element 1 and the wiring board 4 are warped because of different thermal expansion coefficients.
【０００８】次に、図３（ｄ）に示すように、第２の樹
脂８を介して加熱することにより硬化させ、第１の半導
体素子１の上面に対して第２の半導体素子７の裏面を接
着させる。そして、第２の半導体素子７の電極９と配線
基板４の配線１０とを金属細線１１によって電気的に接
続する。Next, as shown in FIG. 3 (d), the second resin 8 is heated and cured so as to be hardened, and the rear surface of the second semiconductor element 7 with respect to the upper surface of the first semiconductor element 1 is cured. To adhere. Then, the electrode 9 of the second semiconductor element 7 and the wiring 10 of the wiring board 4 are electrically connected by the fine metal wire 11.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置の製造方法は、図３（ｃ）に示したように、
第１の半導体素子１と配線基板４とを接着する際に、第
１の半導体素子１と配線基板４との間に注入した第１の
樹脂６を加熱して硬化させた後、室温で冷却する際に、
第１の半導体素子１の熱膨張率と配線基板４の熱膨張率
との相違によって、第１の半導体素子１および配線基板
４が反ってしまう。例えば、厚さ０．６[ｍｍ］の配線
基板４上に、チップサイズ９×９[ｍｍ]、厚さ２５０
[μｍ]の第１の半導体素子１を第１の樹脂６を介して１
７５[℃]で熱硬化させた場合、第１の半導体素子１は４
０[μｍ]反ってしまう。However, as shown in FIG. 3C, the conventional method for manufacturing a semiconductor device is as follows.
When bonding the first semiconductor element 1 and the wiring board 4, the first resin 6 injected between the first semiconductor element 1 and the wiring board 4 is heated and cured, and then cooled at room temperature. When doing
The difference between the coefficient of thermal expansion of the first semiconductor element 1 and the coefficient of thermal expansion of the wiring board 4 causes the first semiconductor element 1 and the wiring board 4 to warp. For example, on a wiring board 4 having a thickness of 0.6 [mm], a chip size of 9 × 9 [mm] and a thickness of 250
1 [μm] of the first semiconductor element 1 with the first resin 6 interposed therebetween.
When heat-cured at 75 [° C.], the first semiconductor element 1 has 4
0 [μm] warps.
【００１０】したがって、図３（ｄ）に示したように、
反った状態の第１の半導体素子１に対して、第２の半導
体素子７を搭載して熱圧着する場合、大きな加圧力を加
えない限り、第１の半導体素子１と第２の半導体素子７
とを全面にわたって均一に接着させることは困難であ
る。ここで、第２の半導体素子７の上面から圧着ツール
で加圧することで、反りを強制的に矯正した場合、第１
の半導体素子１の回路素子および配線基板４の配線を断
線させる等のダメージを与えることになるので、反りを
矯正するための加圧力には限界がある。Therefore, as shown in FIG.
When the second semiconductor element 7 is mounted on the warped first semiconductor element 1 and thermocompression-bonded thereto, the first semiconductor element 1 and the second semiconductor element 7 are provided unless a large pressure is applied.
It is difficult to evenly bond and with each other. Here, when the warp is forcibly corrected by pressing the upper surface of the second semiconductor element 7 with a pressure bonding tool,
Since the circuit element of the semiconductor element 1 and the wiring of the wiring board 4 are damaged, the pressing force for correcting the warp is limited.
【００１１】また、近年の携帯電話等の高機能電子機器
に使用されるメモリーチップ等の半導体素子は、電極数
が５００を超えるような多ピンのものもあり、それに伴
って半導体素子の面積も大型化してきているために、必
然的に反り量も大きくなる。Further, some semiconductor elements such as memory chips used in high-performance electronic equipment such as mobile phones in recent years have a multi-pin structure in which the number of electrodes exceeds 500, so that the area of the semiconductor element also increases. Since the size is increasing, the amount of warpage is inevitably large.
【００１２】このように、第１の半導体素子が反った状
態で第２の半導体素子を第１の半導体素子上に搭載する
と、半導体素子どうしを全面にわたって均一に接着させ
ることが困難となり、間隙が生じたり、樹脂硬化後に半
導体素子間で剥離が生じる。したがって、第２の半導体
素子の電極に金属細線をボンディングする際に、ボンデ
ィング荷重やボンディング周波数等の接合エネルギーが
分散され、安定して金属細線を第２の半導体素子の電極
に接合できない。As described above, when the second semiconductor element is mounted on the first semiconductor element in a state where the first semiconductor element is warped, it becomes difficult to uniformly bond the semiconductor elements to each other over the entire surface, resulting in a gap. Or, peeling occurs between the semiconductor elements after the resin is cured. Therefore, when the metal thin wire is bonded to the electrode of the second semiconductor element, bonding energy such as bonding load and bonding frequency is dispersed, and the metal thin wire cannot be stably bonded to the electrode of the second semiconductor element.
【００１３】さらに、半導体素子間の間隙や亀裂に水分
が浸透して、剥離や亀裂を増大させることになって、実
装信頼性を低下させる要因となる。Further, moisture penetrates into the gaps and cracks between the semiconductor elements to increase peeling and cracks, which causes a decrease in mounting reliability.
【００１４】[0014]
【課題を解決するための手段】前記従来の課題を解決す
るために、本発明の半導体装置の製造方法は、配線基板
上に第１の半導体素子を第１の樹脂を介して第１の温度
を印加して接着する工程と、前記第１の半導体素子上に
対して、第２の半導体素子を第２の樹脂を介して第２の
温度を印加して接着する工程とよりなる複数の半導体素
子を積層する半導体装置の製造方法であって、前記第２
の半導体素子を第１の半導体素子上に接着する工程で
は、前記第１の温度よりも高温の第２の温度を印加し、
前記第１の樹脂を軟化させた状態で接着する。In order to solve the above-mentioned conventional problems, a method of manufacturing a semiconductor device according to the present invention comprises a first semiconductor element on a wiring board at a first temperature via a first resin. A plurality of semiconductors, and a step of applying a second temperature to the first semiconductor element via a second resin to adhere the second semiconductor element to the first semiconductor element. A method of manufacturing a semiconductor device in which elements are stacked, the method comprising:
In the step of adhering the semiconductor element on the first semiconductor element, a second temperature higher than the first temperature is applied,
The first resin is adhered in a softened state.
【００１５】これにより、半導体素子どうしの熱圧着時
に第１の樹脂が軟化して、第１の半導体素子の反りが解
消するので、半導体素子どうしを全面にわたって接着さ
せることができ、金属細線を第２の半導体素子の電極に
安定して接合させることが可能となる。As a result, the first resin is softened at the time of thermocompression bonding between the semiconductor elements and the warpage of the first semiconductor elements is eliminated, so that the semiconductor elements can be adhered to each other over the entire surface, and the thin metal wires can be bonded to each other. The second semiconductor element can be stably bonded to the electrode.
【００１６】また、配線基板上に第１の半導体素子を第
１の樹脂を介して第１の温度を印加して接着する工程で
は、前記配線基板上に前記第１の半導体素子の電極形成
面を接着し、前記配線基板上に形成された配線と前記第
１の半導体素子の電極に形成されたバンプとを電気的に
接続する。In the step of applying the first semiconductor element on the wiring board by applying the first temperature through the first resin to bond the first semiconductor element, the electrode forming surface of the first semiconductor element is formed on the wiring board. Are adhered to electrically connect the wiring formed on the wiring substrate and the bump formed on the electrode of the first semiconductor element.
【００１７】これにより、第１の半導体素子の上面に第
２の半導体素子を熱圧着する時点では、第１の半導体素
子の反りが解消されているので、半導体素子どうしを全
面にわたって接着させることができ、第２の半導体素子
の電極に対して金属細線を安定して接合し、半導体素子
間の亀裂を防止することができる。また、半導体装置を
薄型化することができ、短い配線長により高周波デバイ
スへの応用も可能である。As a result, at the time of thermocompression bonding the second semiconductor element to the upper surface of the first semiconductor element, the warpage of the first semiconductor element is eliminated, so that the semiconductor elements can be bonded to each other over the entire surface. Therefore, the metal thin wire can be stably bonded to the electrode of the second semiconductor element, and cracks between the semiconductor elements can be prevented. Further, the semiconductor device can be thinned, and the short wiring length enables application to a high frequency device.
【００１８】また、配線基板上に第１の半導体素子を第
１の樹脂を介して第１の温度を印加して接着する工程で
は、前記配線基板上に前記第１の半導体素子の裏面を接
着する。In the step of applying the first temperature to the wiring board via the first resin by applying the first temperature, the back surface of the first semiconductor element is bonded to the wiring board. To do.
【００１９】これにより、半導体素子どうしを全面にわ
たり接着させることができ、ワイヤボンディング装置を
用いて半導体素子の電極と配線基板の配線とを金属細線
により安定して電気的に接合することができる。Thus, the semiconductor elements can be adhered to each other over the entire surface, and the electrode of the semiconductor element and the wiring of the wiring board can be stably and electrically connected to each other by the fine metal wire by using the wire bonding apparatus.
【００２０】また、第１の樹脂は熱硬化性樹脂または熱
可塑性樹脂を用いる。A thermosetting resin or a thermoplastic resin is used as the first resin.
【００２１】これにより、特定の樹脂に限定されること
なく、熱硬化性樹脂または熱可塑性樹脂であれば第１の
樹脂として用いることができ、特に、熱可塑性樹脂を用
いた場合は、半導体素子どうしを接着する加熱時に容易
に第１の樹脂が軟化し、第１の半導体素子の反りが解消
する。As a result, the thermosetting resin or the thermoplastic resin can be used as the first resin without being limited to a specific resin. Particularly, when the thermoplastic resin is used, the semiconductor element is The first resin is easily softened at the time of heating to bond the two, and the warpage of the first semiconductor element is eliminated.
【００２２】また、第１の樹脂の軟化温度は第２の樹脂
の硬化温度よりも低い。The softening temperature of the first resin is lower than the hardening temperature of the second resin.
【００２３】これにより、第２の樹脂の加熱時に第１の
樹脂が軟化するので、第１の半導体素子の反りが解消さ
れた状態で半導体素子どうしを全面にわたって熱圧着で
きる。As a result, the first resin is softened when the second resin is heated, so that the semiconductor elements can be thermocompression bonded over the entire surface in a state where the warpage of the first semiconductor element is eliminated.
【００２４】[0024]
【発明の実施の形態】以下、本発明の半導体装置の製造
方法の一実施形態について図面を参照しながら説明す
る。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method of manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.
【００２５】図１および図２は、本実施形態の半導体装
置の製造方法の製造工程を示す断面図である。1 and 2 are sectional views showing the manufacturing steps of the method for manufacturing a semiconductor device of this embodiment.
【００２６】まず、図１（ａ）に示すように、第１の半
導体素子１２の電極１３に突起状のバンプ１４を形成す
る。本実施形態では、ワイヤボンディグ法を用いてＡｕ
バンプを形成したが、めっき法によってバンプを形成し
てもよい。First, as shown in FIG. 1A, bumps 14 having a protruding shape are formed on the electrodes 13 of the first semiconductor element 12. In the present embodiment, Au is formed by using the wire bonding method.
Although the bump is formed, the bump may be formed by a plating method.
【００２７】次に、図１（ｂ）に示すように、バンプ１
４が形成された第１の半導体素子１２の面と配線基板１
５の表面とを対向させ、バンプ１４と配線基板１５の配
線１６とを位置合わせして電気的に接続する。本実施形
態では、配線基板１５はガラスエポキシ系樹脂を用いた
が、耐熱性にすぐれた多層のビルドアップ基板であって
もよい。Next, as shown in FIG. 1B, the bump 1
Surface of the first semiconductor element 12 on which the wiring 4 is formed and the wiring board 1
The bump 14 and the wiring 16 of the wiring board 15 are aligned and electrically connected to each other so that the surface of the wiring board 5 faces the surface of the wiring board 15. In this embodiment, the wiring board 15 is made of glass epoxy resin, but it may be a multilayer build-up board having excellent heat resistance.
【００２８】そして、第１の半導体素子１２と配線基板
１５との間に、硬化温度が１５０〜１８０[℃]の熱硬化
性の第１の樹脂１７を注入し、１６５[℃]に加熱するこ
とにより硬化させる。本実施形態では第１の樹脂とし
て、液状のエポキシ系樹脂を用いたが、あらかじめ、シ
ート状のエポキシ系樹脂または異方性導電膜を第１の半
導体素子１２の電極形成面または配線基板１５の上面に
設置しておいてもよい。Then, a thermosetting first resin 17 having a curing temperature of 150 to 180 [° C.] is injected between the first semiconductor element 12 and the wiring board 15 and heated to 165 [° C.]. To cure. Although the liquid epoxy resin is used as the first resin in the present embodiment, a sheet-shaped epoxy resin or an anisotropic conductive film is previously formed on the electrode formation surface of the first semiconductor element 12 or the wiring substrate 15. It may be installed on the upper surface.
【００２９】次に、図１（ｃ）に示すように、配線基板
１５と第１の半導体素子１２とをそれらの間に注入され
た第１の樹脂１７とともに室温で冷却すると、第１の半
導体素子１２の熱膨張率と配線基板１５の熱膨張率との
相違により、第１の半導体素子１２および配線基板１５
が反ってしまう。そして、反った状態の第１の半導体素
子１２の裏面に対して、硬化温度が１８０〜２００[℃]
のシート状の熱硬化性エポキシ系の第２の樹脂１８を裏
面に設置した第２の半導体素子１９を対向させる。な
お、第２の樹脂１８は液状のエポキシ系樹脂でもよい。Next, as shown in FIG. 1C, when the wiring board 15 and the first semiconductor element 12 are cooled at room temperature together with the first resin 17 injected between them, the first semiconductor is obtained. Due to the difference between the coefficient of thermal expansion of the element 12 and the coefficient of thermal expansion of the wiring board 15, the first semiconductor element 12 and the wiring board 15
Warps. Then, the curing temperature is 180 to 200 [° C.] for the back surface of the warped first semiconductor element 12.
The second semiconductor element 19 having the sheet-shaped thermosetting epoxy-based second resin 18 provided on the back surface thereof is opposed to the second semiconductor element 19. The second resin 18 may be a liquid epoxy resin.
【００３０】次に、図２（ａ）に示すように、第２の半
導体素子１９の電極形成面を圧着ツール２０により１９
０[℃]に加熱しながら加圧する。ここで、圧着ツール２
０を第２の半導体素子１９に接触させることにより第２
の樹脂１８の温度を１９０[℃］に上昇させているが、
この温度は、第１の樹脂を加熱して硬化させる温度の１
７５[℃]よりも高温である。Next, as shown in FIG. 2A, the surface of the second semiconductor element 19 on which the electrodes are formed is bonded to the surface of the second semiconductor element 19 by a pressure bonding tool 20.
Pressurize while heating to 0 [° C]. Where the crimping tool 2
0 by contacting the second semiconductor element 19
Although the temperature of the resin 18 is raised to 190 [° C],
This temperature is one of the temperatures at which the first resin is heated and cured.
The temperature is higher than 75 [° C].
【００３１】ところで、熱硬化性樹脂の特性として、加
熱によりいったん硬化させて冷却しても、再度、硬化温
度よりも高温に加熱することで軟化する性質がある。本
実施形態においても、半導体素子どうしを接着する第２
の樹脂１８の温度を１９０[℃］まで上昇させると、第
１の樹脂１７は軟化するので反りが解消し、半導体どう
しを全面にわたって接着できる。By the way, as a characteristic of the thermosetting resin, even if the thermosetting resin is once hardened by heating and then cooled, it is softened by heating again to a temperature higher than the hardening temperature. Also in the present embodiment, the second bonding of the semiconductor elements is performed.
When the temperature of the resin 18 is raised to 190 [° C.], the first resin 17 is softened so that the warpage is eliminated and the semiconductors can be bonded over the entire surface.
【００３２】また、第１の樹脂１７として熱可塑性樹脂
を用いてもよく、この場合、半導体素子どうしの熱圧着
時に、いったん固化（第１の樹脂として、熱硬化性樹脂
を用いた場合は「硬化」、熱可塑性樹脂を用いた場合は
「固化」という表現を用いている）した第１の樹脂が、
熱硬化性樹脂を用いた場合と比較して容易に軟化し、第
１の半導体素子の反りを解消できるので、半導体素子ど
うしを全面にわたって接着することが可能となる。A thermoplastic resin may be used as the first resin 17. In this case, when the semiconductor elements are thermocompression-bonded, they are once solidified (when a thermosetting resin is used as the first resin, " The first resin that has been “cured” or “solidified” when a thermoplastic resin is used) is
As compared with the case where a thermosetting resin is used, the first semiconductor element can be easily softened and the warpage of the first semiconductor element can be eliminated, so that the semiconductor elements can be bonded over the entire surface.
【００３３】このように、第１の半導体素子の反りが解
消すると、半導体素子どうしを全面にわたって接着する
ことができるので、半導体素子の間の接着面に間隙や亀
裂が生じることがない。したがって、第２の半導体素子
の電極にワイヤボンディングする際に、超音波による振
動や加圧力等の接合エネルギーが分散されることなく、
安定した接合が可能となる。When the warpage of the first semiconductor element is eliminated in this way, the semiconductor elements can be bonded to each other over the entire surface, so that no gaps or cracks are formed on the bonding surface between the semiconductor elements. Therefore, when wire-bonding to the electrode of the second semiconductor element, the bonding energy such as vibration and pressure due to ultrasonic waves is not dispersed,
Stable joining is possible.
【００３４】次に、図２（ｂ）に示すように、第２の半
導体素子１９の電極２１と配線基板１５の配線２２とを
金属細線２３により電気的に接合する。Next, as shown in FIG. 2B, the electrode 21 of the second semiconductor element 19 and the wiring 22 of the wiring board 15 are electrically joined by the fine metal wire 23.
【００３５】次に、図２（ｃ）に示すように、配線基板
１５上で第１の半導体素子１２、第２の半導体素子１９
および金属細線２３を封止樹脂２４によって封止する。Next, as shown in FIG. 2C, the first semiconductor element 12 and the second semiconductor element 19 are formed on the wiring board 15.
And the thin metal wire 23 is sealed with the sealing resin 24.
【００３６】なお、本実施形態では第１の半導体素子の
電極形成面を配線基板の上面に対向させてバンプによっ
てフリップチップ接合する形態を説明したが、第１の半
導体素子の裏面と配線基板の上面とを第１の樹脂によっ
て熱圧着し、第１の半導体素子の電極形成面と第２の半
導体素子の裏面とを第２の樹脂により熱圧着した後、第
１の半導体素子の電極、第２の半導体素子の電極と配線
基板の配線とを金属細線で電気的に接続する場合も、同
様に、第１の樹脂が軟化する温度よりも高い温度で第２
の樹脂を加熱、硬化させることで第１の半導体素子の反
りを解消し、半導体素子どうしを熱圧着できる。In this embodiment, the electrode formation surface of the first semiconductor element is opposed to the upper surface of the wiring board to perform flip-chip bonding by bumps. However, the back surface of the first semiconductor element and the wiring board are The upper surface is thermocompression-bonded with the first resin, and the electrode forming surface of the first semiconductor element and the back surface of the second semiconductor element are thermocompression-bonded with the second resin. Similarly, when electrically connecting the electrode of the second semiconductor element and the wiring of the wiring board with a fine metal wire, the second resin is also heated at a temperature higher than the softening temperature of the first resin.
By heating and curing the resin of (1), the warpage of the first semiconductor element can be eliminated, and the semiconductor elements can be thermocompression bonded.
【００３７】次に、具体的に半導体素子の反り量の解消
と加熱温度との関係について説明する。配線基板と第１
の半導体素子とを、硬化温度が１７５[℃]の第１の樹脂
を用いて加熱、硬化することにより、第１の半導体素子
の全面で４０[μｍ]の反りが発生したが、その後、第２
の半導体素子を第１の半導体素子に熱圧着する際に１８
５[℃]に加熱することで、第１の半導体素子の反りが解
消してほぼ平坦になることを確認した。なお、第１の半
導体素子のサイズは９×９[ｍｍ]、厚みは６００[μ
ｍ]、配線基板の厚みは２５０[μｍ]である。Next, the relationship between the elimination of the warp amount of the semiconductor element and the heating temperature will be specifically described. Wiring board and first
By heating and curing the semiconductor element of No. 1 using the first resin having a curing temperature of 175 [° C.], a warpage of 40 [μm] occurred on the entire surface of the first semiconductor element. Two
When the semiconductor element of 1 is thermocompression-bonded to the first semiconductor element,
It was confirmed that by heating to 5 [° C.], the warpage of the first semiconductor element was eliminated and it became substantially flat. The size of the first semiconductor element is 9 × 9 [mm] and the thickness is 600 [μ
m], and the thickness of the wiring board is 250 [μm].
【００３８】また、それぞれの樹脂の軟化温度および硬
化温度は、それぞれの樹脂の軟化、硬化の状態の境界状
態を決定するものであり、本実施形態の軟化温度および
硬化温度は、樹脂の硬度または接着力が急激に変化す
る、いわゆるガラス転移温度と物性的にほぼ同一である
ことを確認した。Further, the softening temperature and the curing temperature of each resin determine the boundary state of the softening and curing states of the respective resins, and the softening temperature and the curing temperature of this embodiment are the hardness of the resin or the curing temperature. It was confirmed that the adhesive strength is substantially the same as the so-called glass transition temperature at which the adhesive strength changes rapidly.
【００３９】以上、本実施形態の半導体装置の製造方法
は、配線基板と第１の半導体素子とを第１の樹脂を用い
て熱圧着する温度よりも高い温度で半導体素子どうしを
第２の樹脂により熱圧着することにより、第１の樹脂を
軟化させ、第１の半導体素子の反りを解消させた状態で
半導体素子どうしを全面にわたって接着できる。したが
って、ワイヤボンディング時における第２の半導体素子
の電極に対する超音波振動や加圧力等の接合エネルギー
が分散されることなく、安定した金属細線の接合が可能
となる。また、水分の膨張による半導体素子間の間隙や
亀裂の増大が進行することがなく、実装信頼性が向上す
る。As described above, according to the method of manufacturing the semiconductor device of the present embodiment, the semiconductor elements are bonded to the second resin at a temperature higher than the temperature at which the wiring board and the first semiconductor element are thermocompression bonded using the first resin. By thermocompression bonding, the first resin is softened, and the semiconductor elements can be bonded over the entire surface in a state where the warpage of the first semiconductor element is eliminated. Therefore, it is possible to stably bond the fine metal wires without dispersing the bonding energy such as ultrasonic vibration or pressing force to the electrode of the second semiconductor element during wire bonding. Further, the gap between semiconductor elements and the increase of cracks due to the expansion of moisture do not progress, and the mounting reliability is improved.
【００４０】[0040]
【発明の効果】本発明の半導体装置の製造方法は、配線
基板と第１の半導体素子とを接着する第１の樹脂を軟化
させ、第１の半導体素子の反りを解消させた状態で半導
体素子どうしを全面にわたって接着できる。したがっ
て、ワイヤボンディング時の接合エネルギーの分散を防
止して、安定した金属細線の接合を確保できるととも
に、半導体素子どうしの間に形成した第２の樹脂の亀裂
の発生を防止して実装信頼性を向上させることが可能と
なる。According to the method of manufacturing a semiconductor device of the present invention, the first resin for adhering the wiring board and the first semiconductor element is softened to eliminate the warp of the first semiconductor element. Can be glued together over the entire surface. Therefore, it is possible to prevent the dispersion of the bonding energy at the time of wire bonding, to secure the stable bonding of the fine metal wires, and to prevent the second resin formed between the semiconductor elements from cracking to improve the mounting reliability. It is possible to improve.
【図１】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図３】従来の半導体装置の製造方法を示す断面図FIG. 3 is a sectional view showing a conventional method for manufacturing a semiconductor device.
１ 第１の半導体素子 ２ 電極 ３ バンプ ４ 配線基板 ５ 配線 ６ 第１の樹脂 ７ 第２の半導体素子 ８ 第２の樹脂 ９ 電極 １０ 配線 １１ 金属細線 １２ 第１の半導体素子 １３ 電極 １４ バンプ １５ 配線基板 １７ 第１の樹脂 １８ 第２の樹脂 １９ 第２の半導体素子 ２０ 圧着ツール ２１ 電極 ２２ 配線 ２３ 金属細線 1 First semiconductor element 2 electrodes 3 bumps 4 wiring board 5 wiring 6 First resin 7 Second semiconductor element 8 Second resin 9 electrodes 10 wiring 11 thin metal wires 12 First semiconductor element 13 electrodes 14 bumps 15 wiring board 17 First resin 18 Second resin 19 Second semiconductor element 20 Crimping tool 21 electrodes 22 wiring 23 Metal fine wire
Claims (5)
樹脂を介して第１の温度を印加して接着する工程と、前
記第１の半導体素子上に対して、第２の半導体素子を第
２の樹脂を介して第２の温度を印加して接着する工程と
よりなる複数の半導体素子を積層する半導体装置の製造
方法であって、前記第２の半導体素子を第１の半導体素
子上に接着する工程では、前記第１の温度よりも高温の
第２の温度を印加し、前記第１の樹脂を軟化させた状態
で接着することを特徴とする半導体装置の製造方法。1. A step of adhering a first semiconductor element on a wiring board by applying a first temperature through a first resin, and a step of adhering a second semiconductor on the first semiconductor element. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are stacked, which comprises a step of applying a second temperature through a second resin and adhering the elements, wherein the second semiconductor element is a first semiconductor. In the step of adhering on the element, a second temperature higher than the first temperature is applied to adhere the first resin in a softened state.
樹脂を介して第１の温度を印加して接着する工程では、
前記配線基板上に前記第１の半導体素子の電極形成面を
接着し、前記配線基板上に形成された配線と前記第１の
半導体素子の電極に形成されたバンプとを電気的に接続
することを特徴とする請求項１に記載の半導体装置の製
造方法。2. The step of applying a first temperature and adhering a first semiconductor element on a wiring board via a first resin,
Bonding the electrode forming surface of the first semiconductor element on the wiring board, and electrically connecting the wiring formed on the wiring board and the bump formed on the electrode of the first semiconductor element. The method for manufacturing a semiconductor device according to claim 1, further comprising:
樹脂を介して第１の温度を印加して接着する工程では、
前記配線基板上に前記第１の半導体素子の裏面を接着す
ることを特徴とする請求項１に記載の半導体装置の製造
方法。3. A step of adhering a first semiconductor element onto a wiring board by applying a first temperature via a first resin,
The method of manufacturing a semiconductor device according to claim 1, wherein the back surface of the first semiconductor element is bonded onto the wiring board.
性樹脂を用いることを特徴とする請求項１〜請求項３の
いずれかに記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the first resin is a thermosetting resin or a thermoplastic resin.
化温度よりも低いことを特徴とする請求項１〜請求項３
のいずれかに記載の半導体装置の製造方法。5. The softening temperature of the first resin is lower than the curing temperature of the second resin.
A method for manufacturing a semiconductor device according to any one of 1.
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| JP2001047868A JP3419398B2 (en) | 2001-02-23 | 2001-02-23 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001047868A JP3419398B2 (en) | 2001-02-23 | 2001-02-23 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2002252326A JP2002252326A (en) | 2002-09-06 |
| JP3419398B2 true JP3419398B2 (en) | 2003-06-23 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6682955B2 (en) * | 2002-05-08 | 2004-01-27 | Micron Technology, Inc. | Stacked die module and techniques for forming a stacked die module |
| JP4905668B2 (en) * | 2006-09-15 | 2012-03-28 | 信越化学工業株式会社 | Liquid epoxy resin composition for semiconductor encapsulation and semiconductor device |
| JP2008166373A (en) | 2006-12-27 | 2008-07-17 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP2009038347A (en) * | 2007-07-06 | 2009-02-19 | Hitachi Chem Co Ltd | Method of mounting circuit member |
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