JP2004111695A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004111695A
JP2004111695A JP2002273000A JP2002273000A JP2004111695A JP 2004111695 A JP2004111695 A JP 2004111695A JP 2002273000 A JP2002273000 A JP 2002273000A JP 2002273000 A JP2002273000 A JP 2002273000A JP 2004111695 A JP2004111695 A JP 2004111695A
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bump
semiconductor chip
spacer
internal electrode
main surface
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JP3810359B2 (en
Inventor
Takahiro Kumakawa
隈川　隆博
Koichi Nagao
長尾　浩一
Kazuhiko Matsumura
松村　和彦
Katsuki Uchiumi
内海　勝喜
Yukiko Nakaoka
中岡　由紀子
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Abstract

<P>PROBLEM TO BE SOLVED: To finely connect internal electrodes and miniaturize a package by preventing variations in the interval between chips to be connected in a facedown system. <P>SOLUTION: The semiconductor device comprises a first semiconductor chip 10 having a first internal electrode 11 formed on a main surface and a first bump 13 formed on it; a second semiconductor chip 20 having a second internal electrode 21, formed on a main surface and a second bump 24 formed on it; and a spacer-like projection 14 formed at a region, excluding the respective internal electrodes 11, 21 on respective main surfaces of the first and second semiconductor chips 10, 20. The first and second semiconductor chips 10, 20 are stuck, by joining the first and second bumps 13, 24 to each other. The spacer-like projection 14 is in contact with both the first protection film 12, in the first semiconductor chip 10 and a second protection film 23, in the second semiconductor chip 20. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、それぞれがＬＳＩを有する半導体チップを積層し且つ互いに電気的に接続された、いわゆるチップオンチップ構造の半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
近年、ＬＳＩ半導体装置の低コスト化及び小型化を図るために、互いに異なる機能を有するＬＳＩ、又は互いに異なるプロセスにより形成されたＬＳＩを有する複数の半導体チップがフェースダウン方式により固着されてなる半導体装置が提案されている。
【０００３】
以下、従来の半導体装置について図３を参照しながら説明する。
【０００４】
図３に示すように、主面（素子形成面）上に複数の内部電極１１１が形成された第１の半導体チップ１１０と、主面（素子形成面）上に複数の内部電極１２１及び複数のボンディングパッド１２２が形成された第２の半導体チップ１２０とが、内部電極１１１、１２１同士を互いに対向させて貼り合わされている（例えば、特許文献１参照）。
【０００５】
内部電極１１１、１２１同士は半田バンプ１１１を介在させて電気的に接続されており、第１の半導体チップ１１０と第２の半導体チップ１２０との間における半田バンプ１１２を除く領域には、絶縁性樹脂材１２３が充填されている。
【０００６】
第２の半導体チップ１２０は、リードフレーム２０１におけるダイバッド部２０１ａの上に、ダイボンド樹脂材２０２により固着されている。また、ボンディングパッド１２２とリードフレーム２０１におけるリード部２０１ｂとは、ボンディングワイヤ２０３により電気的に接続されている。
【０００７】
また、第１の半導体チップ１１０、第２の半導体チップ１２０、ボンディングワイヤ２０３、リードフレーム２０１のダイパッド２０１ａ及びリード部２０１ｂの内側部分は、封止樹脂材２０４によって封止されてパッケージを形成している。
【０００８】
以下、前記のように構成された半導体装置の製造方法について図４（ａ）〜図４（ｄ）を参照しながら説明する。
【０００９】
まず、図４（ａ）に示すように、電解めっき法により、第１の半導体チップ１１０に設けられた内部電極１１１の上に半田バンプ１１２を選択的に形成する。
【００１０】
次に、図４（ｂ）に示すように、第２の半導体チップ１２０をウエハから個片に分割した後、第２の半導体チップ１２０の上に絶縁性樹脂材１２３を塗布する。続いて、第１の半導体チップ１１０を接続用ツール（コレット）２５０に真空吸着した状態で、第１の半導体チップ１１０に形成した半田バンプ１１２と、第２の半導体チップ１２０の内部電極１２１との互いの位置を合わせる。
【００１１】
次に、図４（ｃ）に示すように、接続用ツール２５０により加圧し且つ加熱しながら、第１の半導体チップ１１０を第２の半導体チップ１２０に圧着する。その後、さらに加熱して、半田バンプ１１２を溶融させて、第１の半導体チップ１１０の内部電極１１１と、第２の半導体チップ１２０の内部電極１２１とを溶融した半田バンプ１１２によって互いに接合する。
【００１２】
次に、第１の半導体チップ１１０が固着された第２の半導体チップ１１０をリードフレーム２０１のダイパッド部２０１ａにダイボンディングし、その後、第２の半導体チップ１２０のボンディングパッド１２２とリードフレーム２０１のリード部２０１ｂとをボンディングワイヤ２０３により接続し、さらに、封止用樹脂材２０４によって封止することにより、図３に示すパッケージを得る。
【００１３】
【特許文献１】
特開２０００−２３２２００号公報（第１図）
【００１４】
【発明が解決しようとする課題】
しかしながら、前記従来の半導体装置は、第１の半導体チップ１１０と第２の半導体チップ１２０との間隙が、接続用ツール２５０による加圧及び加熱の条件、並びに半田バンプ１１２の高さのばらつきによって決定されるため、チップ１１０、１２０同士の間隙のばらつきを調整することが極めて困難であり、従って、以下に示すような問題を有している。
【００１５】
（１）半田バンプ１１２の潰れ量の調節が困難であるため、熱圧着又は溶融により接合する際に、接合された後の半田バンプ１１２のサイズが各内部電極１１１、１２１よりも大きくなり、その結果、各内部電極１１１、１２１の狭ピッチ化に対応することができない。
【００１６】
（２）チップ１１０、１２０同士の間隙の容積が変動するため、両チップ間に絶縁性樹脂材１２３を確実に充填させるには、該絶縁性樹脂材１２３の充填量を必要な量よりも多く見積もらなくてはならない。その結果、絶縁性樹脂材１２３の充填量を多くするとフィレット幅が大きくなるため、複数の半導体チップのうちボンディングパッド１２２を有する半導体チップ、ここでは第２の半導体チップ１２０の外形サイズを大きくしなければならず、パッケージの小型化を困難とする。
【００１７】
本発明は、前記従来の問題を解決し、フェースダウン方式で接続するチップ同士の間隙のばらつきを防止して内部電極同士を微細に接続でき、且つパッケージの小型化を図れるようにすることを目的とする。
【００１８】
【課題を解決するための手段】
前記従来の目的を達成するため、本発明は、チップオンチップ構造を有する半導体チップ同士の対向面であってバンプ形成部分を除く領域に、スペーサとなる部材を設ける構成とする。
【００１９】
具体的に、本発明に係る第１の半導体装置は、主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップと、第１の半導体チップと第２の半導体チップとの互いの対向面における各内部電極を除く領域に形成されたスペーサ状突起部とを備え、第１の半導体チップと第２の半導体チップとは、第１のバンプと第２のバンプとが互いに接合することにより固着されており、スペーサ状突起部は第１の半導体チップ及び第２の半導体チップと接している。
【００２０】
第１の半導体装置によると、第１の半導体チップと第２の半導体チップとの互いの対向面における各内部電極を除く領域に形成されたスペーサ状突起部を備え、スペーサ状突起部は第１の半導体チップ及び第２の半導体チップと接しているため、第１の半導体チップと第２の半導体チップとの間隙が、バンプの高さではなくスペーサ状突起部の高さにより一定に保たれるようになる。
【００２１】
本発明に係る第２の半導体装置は、主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップと、第１の半導体チップの主面における第１の内部電極を除く領域に形成された第１のスペーサ状突起部と、第２の半導体チップの主面における第２の内部電極を除く領域に形成された第２のスペーサ状突起部とを備え、第１の半導体チップと第２の半導体チップとは、第１のバンプと第２のバンプとが互いに接合することにより固着されており、第１のスペーサ状突起部と第２のスペーサ状突起部とは互いに接している。
【００２２】
第２の半導体装置によると、第１の半導体チップの主面における第１の内部電極を除く領域に形成された第１のスペーサ状突起部と、第２の半導体チップの主面における第２の内部電極を除く領域に形成された第２のスペーサ状突起部とを備え、第１のスペーサ状突起部と第２のスペーサ状突起部とは互いに接しているため、第１の半導体チップと第２の半導体チップとの間隙が、バンプの高さではなく第１のスペーサ状突起部及び第２のスペーサ状突起部の高さにより一定に保たれるようになる。
【００２３】
本発明に係る第１の半導体装置の製造方法は、主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップとを用意する第１の工程と、第１の半導体チップの主面における第１の内部電極を除く領域上にスペーサ状突起部を形成する第２の工程と、第１のバンプと第２のバンプとが互いに対向するように、第１の半導体チップと第２の半導体チップとを加熱し且つ加圧しながら固着する第３の工程とを備え、第３の工程は、第１のバンプの頂部と第２のバンプの頂部とが接して、そのうちの少なくとも一方が潰れることにより、第１のバンプと第２のバンプとが電気的に接続する工程と、スペーサ状突起部の端部が第２の半導体チップと接することにより、第１のバンプ又は第２のバンプの潰れを抑制する工程とを含む。
【００２４】
第１の半導体装置の製造方法によると、第１のバンプの頂部と第２のバンプの頂部とが接してそのうちの少なくとも一方が潰れることにより、第１のバンプと第２のバンプとが電気的に接続し、その後、スペーサ状突起部の端部が第２の半導体チップと接することにより、第１のバンプ又は第２のバンプの潰れを抑制する。このように、第１のバンプと第２のバンプとが電気的な接続を十分に行なえる程度にまで押し潰された状態となった後に、第１の半導体チップに形成されたスペーサ状突起部が第２の半導体チップに接触する。このため、バンプに掛かっていた加重がスペーサ状突起部に分散してバンプの潰れ過ぎを抑制できるので、第１の半導体チップと第２の半導体チップとの間隙をバンプの高さではなくスペーサ状突起部の高さによって一定に保つことができる。
【００２５】
第１の半導体装置の製造方法において、スペーサ状突起部は第１のバンプと同一の材料で形成することが好ましい。
【００２６】
このようにすると、スペーサ状突起部をバンプの形成工程と同一の工程で形成することができるため、スペーサ状突起部の形成が容易となると共に、製造コスト及び材料コストを低減することができる。
【００２７】
第１の半導体装置の製造方法において、スペーサ状突起部は第１のバンプと同一の高さで形成することが好ましい。
【００２８】
このようにすると、スペーサ状突起部の高さが、第１のバンプの高さと第２のバンプの高さとの和よりも小さくなるため、スペーサ状突起部は、第１のバンプと第２のバンプとが互いの電気的な接合が十分に行なえるまで押し潰された後に、スペーサとしての機能を確実に果たすことが可能となる。
【００２９】
第１の半導体装置の製造方法において、スペーサ状突起部は有機材料で形成することが好ましい。
【００３０】
このようにすると、スペーサ状突起部が第２の半導体チップと接触した際に、有機材の弾性によりスペーサ状突起部自体が緩衝材となるため、第２の半導体チップのスペーサ状突起部による損傷を防止することができる。
【００３１】
第１の半導体装置の製造方法において、スペーサ状突起部と第２の半導体チップとの接触面積は、第１のバンプと第２のバンプとの接合面積よりも大きいか等しいことが好ましい。
【００３２】
このようにすると、スペーサ状突起部が第２の半導体素子の表面に接触した際に、接合時に第１のバンプ及び第２のバンプに掛かる加重を２分の１以下に低減できるため、バンプの潰れをより確実に抑制することができる。さらに、スペーサ状突起部が第２の半導体チップと接触する際の接触面積を大きくとることができるため、第２の半導体チップに対する衝撃が軽減されるので、第２の半導体チップが有する素子の特性劣化を防止することができる。
【００３３】
本発明に係る第２の半導体装置の製造方法は、主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップとを用意する第１の工程と、第１の半導体チップの主面における第１の内部電極を除く領域上に第１のスペーサ状突起部を形成する第２の工程と、第２の半導体チップの主面における第２の内部電極を除く領域上であって、第１のスペーサ状突起部と対向する位置に第２のスペーサ状突起部を形成する第３の工程と、第１のバンプと第２のバンプとが互いに対向すると共に第１のスペーサ状突起部と第２のスペーサ状突起部とが互いに対向するように、第１の半導体チップと第２の半導体チップとを加熱し且つ加圧しながら固着する第４の工程とを備え、第４の工程は、第１のバンプの頂部と第２のバンプの頂部とが接して、そのうちの少なくとも一方が潰れることにより、第１のバンプと第２のバンプとが電気的に接続する工程と、第１のスペーサ状突起部の端部が第２のスペーサ状突起部と接することにより、第１のバンプ又は第２のバンプの潰れを抑制する工程とを含む。
【００３４】
第２の半導体装置の製造方法によると、第１のバンプの頂部と第２のバンプの頂部とが接してそのうちの少なくとも一方が潰れることにより、第１のバンプと第２のバンプとが電気的に接続し、その後、第１のスペーサ状突起部の端部が第２のスペーサ状突起部と接することにより、第１のバンプ又は第２のバンプの潰れを抑制する。このように、第１のバンプと第２のバンプとが、互いの電気的な接続を十分に行なえる程度にまで押し潰された状態となった後に、第１の半導体チップに形成された第１のスペーサ状突起部と第２の半導体チップに形成された第２のスペーサ状突起部とが互いに接触する。このため、バンプに掛かっていた加重が第１及び第２のスペーサ状突起部に分散してバンプの潰れ過ぎが抑制されるので、第１の半導体チップと第２の半導体チップとの間隙をバンプの高さではなく第１及び第２のスペーサ状突起部の高さによって一定に保つことができる。
【００３５】
第２の半導体装置の製造方法において、第１のスペーサ状突起部は、第１のバンプと同一の材料で形成することが好ましい。
【００３６】
第２の半導体装置の製造方法において、第１のスペーサ状突起部は、第１のバンプと同一の高さで形成し、第２のスペーサ状突起部は、第２のバンプよりも低く形成することが好ましい。
【００３７】
このようにすると、第１のスペーサ状突起部と第２のスペーサ状突起部との高さの和が、第１のバンプの高さと第２のバンプの高さの和よりも小さくなるため、第１のスペーサ状突起部及び第２のスペーサ状突起部は、第１のバンプと第２のバンプとが互いの電気的な接合が十分に行なえるまで押し潰された後に、スペーサとしての機能を確実に果たすことができる。
【００３８】
第２の半導体装置の製造方法において、第１のスペーサ状突起部及び第２のスペーサ状突起部のうち少なくとも一方は有機材料で形成することが好ましい。
【００３９】
第２の半導体装置の製造方法において、第１のスペーサ状突起部と第２のスペーサ状突起部との接触面積は、第１のバンプと第２のバンプとの接合面積よりも大きいか等しいことが好ましい。
【００４０】
【発明の実施の形態】
（第１の実施形態）
本発明の第１の実施形態について図面を参照しながら説明する。ここでは、チップオンチップ構造を有する半導体装置をその製造方法によって説明する。
【００４１】
図１（ａ）〜図１（ｄ）は本発明の第１の実施形態に係る半導体装置の製造方法の工程順の断面構成を示している。
【００４２】
まず、主面に回路素子及び配線（図示せず）、並びに第１の内部電極１１が形成され、該第１の内部電極１１を除く領域に第１の保護（パッシベーション）膜１２が形成された第１の半導体チップ１０を用意する。また、主面に回路素子及び配線（図示せず）、第１の内部電極２１並びにその外側に外部電極２２が形成され、第２の内部電極２１及び外部電極２２を除く領域に第２の保護（パッシベーション）膜２３が形成された第２の半導体チップ２０を用意する。
【００４３】
続いて、第１の半導体チップ１０の第１の内部電極１１の上には、例えば半田材からなる第１のバンプ１３を形成し、第１の保護膜１２の上には、例えば第１のバンプ１３と同様に半田材からなり、互いに間隔をおいた複数のスペーサ状突起部１４を形成する。ここで、第１のバンプ１３及びスペーサ状突起部１４は、電解めっき法又は半田印刷法等により形成する。同様に、第２の半導体チップ２０の第２の内部電極２１の上には、例えば半田材からなる第２のバンプ２４を形成する。なお、第１のバンプ１３、スペーサ状突起部１４及び第２のバンプ２４の材料は、半田材に限られず、金、ニッケル又は銅等を用いてもよい。
【００４４】
次に、図１（ａ）に示すように、第２の半導体チップ２０の主面上における内部電極２１及び外部電極２２を覆わないように、エポキシ、ポリイミド、又はアクリル等からなり熱硬化性を有する絶縁性樹脂材２５を塗布する。続いて、主面上に第１のバンプ１３及びスペーサ状突起部１４が形成された第１の半導体チップ１０における主面の反対側の面をボンディングツール５０により真空吸着し、第１の半導体チップ１０の第１のバンプ１３と、第２の半導体チップ２０の第２のバンプ２４とが互いに対向するように位置合わせする。
【００４５】
次に、図１（ｂ）に示すように、ボンディングツール５０を介して第１の半導体チップ１０を加圧し且つ加熱することにより、第１のバンプ１３と第２のバンプ２１のうち少なくとも一方を潰しながら、該第１のバンプ１３と第２のバンプ２１とを接合する。
【００４６】
次に、図１（ｃ）に示すように、ボンディングツール５０を介して第１の半導体チップ１０をさらに加圧することにより、第１の半導体チップ１０上
に設けられた各スペーサ状突起部１４の頂部を第２の半導体チップ２０の第２の保護膜１０に接触させる。このとき、複数のスペーサ状突起部１４が、第２の半導体チップ２０上の第２の保護膜２３と接触することにより、第１の半導体チップ１０に設けられた第１のバンプ１３と、第２の半導体チップ２０に設けられた第２のバンプ２４とに掛かっている圧力が分散されるため、第１のバンプ１３又は第２のバンプ２４は潰れにくくなる。
【００４７】
ここで、例えば、スペーサ状突起部１４の高さ寸法が第１のバンプ１３とほぼ同一で且つその個数も同数である場合には、スペーサ状突起部１４が第２の半導体チップ２０上の保護膜２３と接触した後の第１のバンプ１３と第２のバンプ２４の潰れ量は、スペーサ状突起部１４を設けなかった場合におけるスペーサ状突起部１４の保護膜２３との仮想の接触点からの各バンプ１３、２４の潰れ量と比べて、約４分の１以下に低減されることを実験により確認している。これにより、スペーサ状突起部１４を設けない場合と比べて、第１及び第２の各バンプ１３、２４の潰れすぎを確実に抑制できるため、第１の半導体チップ１０と第２の半導体チップ２０との間隙のばらつきを防止することができる。
【００４８】
次に、図１（ｄ）に示すように、第１の半導体チップ１０からボンディングツール５０を外し、その後、絶縁性樹脂材２５を加熱して硬化することにより、第１の半導体チップ１０と第２の半導体チップ２０とを互いに固着する。
【００４９】
この後は、図３に示す従来例のように、第１の半導体チップ１０が貼り合わされた第２の半導体チップ２０をリードフレーム上にダイボンディングとワイヤボンディングとを行ない、さらに封止樹脂材により封止してもよい。
【００５０】
ここで、絶縁性樹脂材２５は、第１の半導体チップ１０を第２の半導体チップ２０の主面に貼り合わせるよりも前に、すなわち第１のバンプ１３及び第２のバンプ２４を接合するよりも前に塗布しているが、該バンプ１３、２４同士を接合した後に毛細管現象を利用して、第１の半導体チップ１０と第２の半導体チップ２０との間隙に充填してもよく、また絶縁性樹脂材２５は必ずしも充填しなくてもよい。
【００５１】
このように、第１の実施形態によると、第１の半導体チップ１０と第２の半導体チップ２０との互いの主面同士の間に、各内部電極１１、２１を除く領域に形成されたスペーサ状突起部１４備えており、該スペーサ状突起部１４は第２の半導体チップ２０の第２の保護膜２３と接しているため、第１の半導体チップ１０と第２の半導体チップ２０との間隙が、各バンプ１３、２４の高さではなくスペーサ状突起部１４の高さにより一定に保たれる。これにより、フェースダウン方式で接続される半導体チップ１０、２０同士の間隙のばらつきが防止されるため、内部電極１１、２１同士を微細に接続できるので、パッケージの小型化を図ることができる。
【００５２】
なお、スペーサ状突起部１４の高さは、第１のバンプ１３及び第２のバンプ２４のうち高さが大きい方に合わせるのが好ましい。
【００５３】
また、スペーサ状突起部１４と第２の半導体チップ２０の第２の保護膜２３との接触面積は、第１のバンプ１３と第２のバンプ２４との接合面積よりも大きいか等しいことが好ましい。
【００５４】
また、スペーサ状突起部１４は、第１の半導体チップ１０に設ける代わりに、第２の半導体チップ２０に形成してもよい。
【００５５】
また、スペーサ状突起部１４は必ずしも導電性を有する必要はなく、半導体チップの保護膜として用いられる、例えばポリイミドのような有機材料により形成してもよい。但し、例えば第１の半導体チップ１０に有機材料からなるスペーサ状突起部１４を設ける場合には、該スペーサ状突起部１４は、第１のバンプ１３を形成するよりも前か、第１のバンプ１３を形成した後に設ける。
【００５６】
（第２の実施形態）
以下、本発明の第２の実施形態について図面を参照しながら説明する。ここでも第１の実施形態と同様に、チップオンチップ構造を有する半導体装置についてその製造方法によって説明する。
【００５７】
図２（ａ）〜図２（ｄ）は本発明の第２の実施形態に係る半導体装置の製造方法の工程順の断面構成を示している。
【００５８】
図２において、図１に示す構成部材と同一の構成部材には同一の符号を付すことにより説明を省略し、第１の実施形態との相違点のみを説明する。
【００５９】
図２（ａ）に示すように、第１の半導体チップ１０を第２の半導体チップ２０と貼り合わせるよりも前に、第２の半導体チップ２０における第２の保護膜２３上であって、第１の半導体チップ１０の各第１のバンプ１３と対向する部分に、半田材等の導電性部材又はエポキシ等の絶縁性部材からなる第２のスペーサ状突起部３４を選択的に形成する。なお、第２の実施形態においては、第１の半導体チップ１０の第１の保護膜１２の上に形成したスペーサ状突起部１４を第１のスペーサ状突起部と呼ぶ。
【００６０】
続いて、第２の半導体チップ２０の主面上の内部電極２１及び外部電極２２を覆わないように、エポキシ等からなり熱硬化性を有する絶縁性樹脂材２５を塗布する。続いて、主面上に第１のバンプ１３及び第１のスペーサ状突起部１４が形成された第１の半導体チップ１０における主面の反対側の面をボンディングツール５０により真空吸着し、第１の半導体チップ１０の第１のバンプ１３と、第２の半導体チップ２０の第２のバンプ２４とが互いに対向するように位置合わせする。
【００６１】
次に、図２（ｂ）に示すように、ボンディングツール５０を介して第１の半導体チップ１０を加圧し且つ加熱することにより、第１のバンプ１３及び第２のバンプ２１のうち少なくとも一方を潰しながら、該第１のバンプ１３と第２のバンプ２１とを接合する。
【００６２】
次に、図２（ｃ）に示すように、ボンディングツール５０を介して第１の半導体チップ１０をさらに加圧することにより、第１の半導体チップ１０に設けられた各第１のスペーサ状突起部１４の頂部を、第２の半導体チップ２０上にそれぞれ対向するように設けられた第２のスペーサ状突起部３４の頂部と接触させる。このとき、複数の第１のスペーサ状突起部１４が、第２の半導体チップ２０上の第２のスペーサ状突起部３４の頂部と接触することにより、第１の半導体チップ１０に設けられた第１のバンプ１３と、第２の半導体チップ２０に設けられた第２のバンプ２４とに掛かっている圧力が分散されるため、第１のバンプ１３又は第２のバンプ２４は潰れにくくなる。
【００６３】
ここで、例えば、第１のスペーサ状突起部１４の高さ寸法が第１のバンプ１３とほぼ同一で且つその個数も同数である場合には、第１の実施形態で説明したように、第１のスペーサ状突起部１４が第２の半導体チップ２０に設けた第２のスペーサ状突起部３４と接触した後の第１のバンプ１３と第２のバンプ２４の潰れ量は、第１のスペーサ状突起部１４及び第２のスペーサ状突起部３４を設けない場合と比べて約４分の１以下に低減される。すなわち、第１及び第２の各スペーサ状突起部１４、３４を設けない場合と比べて、第１及び第２の各バンプ１３、２４の潰れすぎが抑制されるため、第１の半導体チップ１０と第２の半導体チップ２０との間隙のばらつきを防止することができる。
【００６４】
次に、図２（ｄ）に示すように、第１の半導体チップ１０からボンディングツール５０を外し、その後、絶縁性樹脂材２５を加熱して硬化することにより、第１の半導体チップ１０と第２の半導体チップ２０とを互いに固着する。
【００６５】
この後は、図３に示す従来例のように、第１の半導体チップ１０が貼り合わされた第２の半導体チップ２０をリードフレーム上にダイボンディングとワイヤボンディングとを行ない、その後、封止樹脂材により封止してもよい。
【００６６】
ここで、絶縁性樹脂材２５は、第１の半導体チップ１０を第２の半導体チップ２０の主面に貼り合わせるよりも前に、すなわち第１のバンプ１３及び第２のバンプ２４を接合するよりも前に塗布しているが、該バンプ１３、２４同士を接合した後に毛細管現象を利用して、第１の半導体チップ１０と第２の半導体チップ２０との間隙に充填してもよく、また絶縁性樹脂材２５は必ずしも充填しなくてもよい。
【００６７】
なお、第２のスペーサ状突起部３４の高さは、第２のバンプ２４の高さよりも小さくすることが好ましい。
【００６８】
また、第１のスペーサ状突起部１４と第２のスペーサ状突起部３４との接触面積は、第１のバンプ１３と第２のバンプ２４との接合面積よりも大きいか等しいことが好ましい。
【００６９】
また、第１のスペーサ状突起部１４は必ずしも導電性を有する必要はなく、半導体チップの保護膜として用いられる、例えばポリイミドのような有機材料により形成してもよい。
【００７０】
【発明の効果】
本発明に係る半導体装置によると、第１の半導体チップと第２の半導体チップとの互いの対向面における各内部電極を除く領域に形成されたスペーサ状突起部を備えているため、第１の半導体チップと第２の半導体チップとの間隙が、バンプの高さではなくスペーサ状突起部の高さにより一定に保たれる。その結果、フェースダウン方式で接続されるチップ同士の間隙のばらつきが防止されるので、内部電極同士を微細に接続でき、且つパッケージの小型化を図ることができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は本発明の第１の実施形態に係る半導体装置及びその製造方法を示す工程順の構成断面図である。
【図２】（ａ）〜（ｄ）は本発明の第２の実施形態に係る半導体装置及びその製造方法を示す工程順の構成断面図である。
【図３】従来の半導体装置を示す構成面図である。
【図４】従来の半導体装置の製造方法を示す工程順の構成断面図である。
【符号の説明】
１０　　　第１の半導体チップ
１１　　　第１の内部電極
１２　　　第１の保護膜
１３　　　第１のバンプ
１４　　　（第１の）スペーサ状突起部
２０　　　第２の半導体チップ
２１　　　第２の内部電極
２２　　　外部電極
２３　　　第２の保護膜
２４　　　第２のバンプ
２５　　　絶縁性樹脂材
５０　　　ボンディングツール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a so-called chip-on-chip structure in which semiconductor chips each having an LSI are stacked and electrically connected to each other, and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in order to reduce the cost and size of an LSI semiconductor device, a semiconductor device in which LSIs having different functions or a plurality of semiconductor chips having LSIs formed by different processes are fixed by a face-down method. Has been proposed.
[0003]
Hereinafter, a conventional semiconductor device will be described with reference to FIG.
[0004]
As shown in FIG. 3, a first semiconductor chip 110 having a plurality of internal electrodes 111 formed on a main surface (element formation surface), a plurality of internal electrodes 121 and a plurality of internal electrodes 121 formed on a main surface (element formation surface). The second semiconductor chip 120 on which the bonding pads 122 are formed is bonded to each other with the internal electrodes 111 and 121 facing each other (for example, see Patent Document 1).
[0005]
The internal electrodes 111 and 121 are electrically connected to each other with the solder bumps 111 interposed therebetween. The region between the first semiconductor chip 110 and the second semiconductor chip 120 except for the solder bumps 112 has an insulating property. The resin material 123 is filled.
[0006]
The second semiconductor chip 120 is fixed on the die pad portion 201 a of the lead frame 201 with a die bond resin material 202. The bonding pad 122 and the lead portion 201b of the lead frame 201 are electrically connected by a bonding wire 203.
[0007]
Further, the first semiconductor chip 110, the second semiconductor chip 120, the bonding wires 203, and the inner portions of the die pad 201a and the lead portion 201b of the lead frame 201 are sealed with a sealing resin material 204 to form a package. I have.
[0008]
Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS. 4 (a) to 4 (d).
[0009]
First, as shown in FIG. 4A, solder bumps 112 are selectively formed on the internal electrodes 111 provided on the first semiconductor chip 110 by electrolytic plating.
[0010]
Next, as shown in FIG. 4B, after the second semiconductor chip 120 is divided into individual pieces from the wafer, an insulating resin material 123 is applied on the second semiconductor chip 120. Subsequently, in a state where the first semiconductor chip 110 is vacuum-sucked to the connection tool (collet) 250, the solder bumps 112 formed on the first semiconductor chip 110 and the internal electrodes 121 of the second semiconductor chip 120 are connected. Align each other.
[0011]
Next, as shown in FIG. 4C, the first semiconductor chip 110 is pressed against the second semiconductor chip 120 while being pressed and heated by the connection tool 250. Thereafter, the solder bumps 112 are further melted, and the internal electrodes 111 of the first semiconductor chip 110 and the internal electrodes 121 of the second semiconductor chip 120 are joined to each other by the melted solder bumps 112.
[0012]
Next, the second semiconductor chip 110 to which the first semiconductor chip 110 is fixed is die-bonded to the die pad portion 201a of the lead frame 201, and thereafter, the bonding pad 122 of the second semiconductor chip 120 and the lead of the lead frame 201 are connected. The package 201 shown in FIG. 3 is obtained by connecting the portion 201b with the bonding wire 203 and further sealing with the sealing resin material 204.
[0013]
[Patent Document 1]
JP 2000-232200 (FIG. 1)
[0014]
[Problems to be solved by the invention]
However, in the conventional semiconductor device, the gap between the first semiconductor chip 110 and the second semiconductor chip 120 is determined by the conditions of pressing and heating by the connection tool 250 and the variation in the height of the solder bumps 112. Therefore, it is extremely difficult to adjust the variation in the gap between the chips 110 and 120, and thus has the following problems.
[0015]
(1) Since it is difficult to adjust the amount of crushing of the solder bump 112, the size of the solder bump 112 after joining becomes larger than the internal electrodes 111 and 121 when joining by thermocompression bonding or melting. As a result, the pitch of the internal electrodes 111 and 121 cannot be reduced.
[0016]
(2) Since the volume of the gap between the chips 110 and 120 fluctuates, in order to reliably fill the insulating resin material 123 between the chips, the filling amount of the insulating resin material 123 is larger than necessary. I have to estimate. As a result, when the filling amount of the insulating resin material 123 is increased, the fillet width is increased. Therefore, the outer size of the semiconductor chip having the bonding pads 122, in this case, the second semiconductor chip 120 must be increased among the plurality of semiconductor chips. This makes it difficult to reduce the size of the package.
[0017]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems, to prevent variations in gaps between chips connected in a face-down manner, to enable fine connection between internal electrodes, and to reduce the size of a package. And
[0018]
[Means for Solving the Problems]
In order to achieve the above-described conventional object, the present invention has a configuration in which a member serving as a spacer is provided in a region excluding a bump forming portion on a surface facing semiconductor chips having a chip-on-chip structure.
[0019]
Specifically, a first semiconductor device according to the present invention includes a first semiconductor having a first internal electrode formed on a main surface and a first bump formed on the first internal electrode. A chip, a second semiconductor chip having a second internal electrode formed on the main surface and a second bump formed on the second internal electrode, a first semiconductor chip and a second semiconductor chip. A spacer-like projection formed in a region excluding each internal electrode on a surface facing each other with the semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are provided with a first bump and a second bump Are fixed by bonding to each other, and the spacer-like projections are in contact with the first semiconductor chip and the second semiconductor chip.
[0020]
According to the first semiconductor device, the first semiconductor device includes the spacer-shaped protrusion formed in a region excluding each internal electrode on the mutually facing surfaces of the first semiconductor chip and the second semiconductor chip. And the second semiconductor chip are in contact with each other, so that the gap between the first semiconductor chip and the second semiconductor chip is kept constant not by the height of the bump but by the height of the spacer-like projection. Become like
[0021]
A second semiconductor device according to the present invention includes a first semiconductor chip having a first internal electrode formed on a main surface and a first bump formed on the first internal electrode; A second semiconductor chip having a second internal electrode formed on the surface and a second bump formed on the second internal electrode; and a first internal portion on a main surface of the first semiconductor chip. A first spacer-like protrusion formed in a region excluding the electrode, and a second spacer-like protrusion formed in a region other than the second internal electrode on the main surface of the second semiconductor chip; The first semiconductor chip and the second semiconductor chip are fixed by bonding the first bump and the second bump to each other, and the first and second spacer-like projections are connected to each other. Are in contact with each other.
[0022]
According to the second semiconductor device, the first spacer-like projection formed in a region other than the first internal electrode on the main surface of the first semiconductor chip, and the second spacer-like protrusion on the main surface of the second semiconductor chip. A second spacer-like projection formed in a region excluding the internal electrode; and the first spacer-like projection and the second spacer-like projection are in contact with each other. The gap with the second semiconductor chip is kept constant by the height of the first spacer-like projection and the second spacer-like projection, not by the height of the bump.
[0023]
A first method of manufacturing a semiconductor device according to the present invention is directed to a first semiconductor chip having a first internal electrode formed on a main surface and a first bump formed on the first internal electrode. A first step of preparing a second semiconductor chip having a second internal electrode formed on the main surface and a second bump formed on the second internal electrode; A second step of forming a spacer-like projection on a region of the main surface of the semiconductor chip other than the first internal electrode, and a first step of forming a first bump and a second bump so as to face each other. A third step of fixing the semiconductor chip and the second semiconductor chip while heating and applying pressure, wherein the third step is such that the top of the first bump and the top of the second bump are in contact with each other, When at least one of them is crushed, the first bump and the second bump are And a step of vapor-connected, by the end of the spacer protrusions is in contact with the second semiconductor chip, and a step of suppressing the collapse of the first bump and the second bump.
[0024]
According to the method of manufacturing the first semiconductor device, the top of the first bump and the top of the second bump come into contact with each other and at least one of them is crushed, so that the first bump and the second bump are electrically connected. Then, the end of the spacer-shaped protrusion contacts the second semiconductor chip, thereby suppressing the crushing of the first bump or the second bump. After the first bumps and the second bumps are crushed to such an extent that electrical connection can be sufficiently made, the spacer-like projections formed on the first semiconductor chip are formed. Contacts the second semiconductor chip. For this reason, the load applied to the bumps is dispersed to the spacer-like protrusions, so that the bumps can be prevented from being crushed too much. The height can be kept constant by the height of the projection.
[0025]
In the first method for manufacturing a semiconductor device, it is preferable that the spacer-like projections be formed of the same material as the first bumps.
[0026]
With this configuration, since the spacer-like protrusions can be formed in the same step as the bump formation step, the formation of the spacer-like protrusions is facilitated, and the manufacturing cost and material cost can be reduced.
[0027]
In the first method for manufacturing a semiconductor device, it is preferable that the spacer-like projections be formed at the same height as the first bumps.
[0028]
In this case, since the height of the spacer-like protrusion is smaller than the sum of the height of the first bump and the height of the second bump, the spacer-like protrusion is formed by the first bump and the second bump. After the bumps are crushed until the electrical connection between them can be sufficiently performed, the function as a spacer can be reliably performed.
[0029]
In the first method for manufacturing a semiconductor device, it is preferable that the spacer-like projections be formed of an organic material.
[0030]
With this configuration, when the spacer-like projection comes into contact with the second semiconductor chip, the spacer-like projection itself becomes a buffering material due to the elasticity of the organic material, so that the spacer-like projection of the second semiconductor chip is damaged. Can be prevented.
[0031]
In the first method for manufacturing a semiconductor device, it is preferable that a contact area between the spacer-shaped protrusion and the second semiconductor chip is larger than or equal to a bonding area between the first bump and the second bump.
[0032]
With this configuration, when the spacer-like projection contacts the surface of the second semiconductor element, the weight applied to the first bump and the second bump at the time of bonding can be reduced to half or less. Collapse can be suppressed more reliably. Furthermore, since the contact area when the spacer-like projection contacts the second semiconductor chip can be increased, the impact on the second semiconductor chip is reduced, and the characteristics of the element of the second semiconductor chip are reduced. Deterioration can be prevented.
[0033]
A second method of manufacturing a semiconductor device according to the present invention is directed to a first semiconductor chip having a first internal electrode formed on a main surface and a first bump formed on the first internal electrode. A first step of preparing a second semiconductor chip having a second internal electrode formed on the main surface and a second bump formed on the second internal electrode; Forming a first spacer-like projection on a region of the main surface of the semiconductor chip excluding the first internal electrode; and forming a region of the main surface of the second semiconductor chip excluding the second internal electrode. A third step of forming a second spacer-like projection at a position facing the first spacer-like projection on the upper side, wherein the first bump and the second bump face each other, and So that the spacer-like projections and the second spacer-like projections face each other. And a fourth step of fixing the semiconductor chip and the second semiconductor chip while heating and applying pressure, wherein the fourth step is such that the top of the first bump is in contact with the top of the second bump. The step of electrically connecting the first bump and the second bump by crushing at least one of them, and the step of bringing the end of the first spacer-like projection into contact with the second spacer-like projection. And suppressing the collapse of the first bump or the second bump.
[0034]
According to the method of manufacturing the second semiconductor device, the top of the first bump and the top of the second bump come into contact with each other and at least one of them is crushed, so that the first bump and the second bump are electrically connected. Then, the end of the first spacer-like projection comes into contact with the second spacer-like projection, thereby suppressing the crushing of the first bump or the second bump. After the first bumps and the second bumps are crushed to such an extent that they can be electrically connected to each other, the first bumps and the second bumps formed on the first semiconductor chip are formed. The first spacer-like protrusion and the second spacer-like protrusion formed on the second semiconductor chip are in contact with each other. For this reason, the weight applied to the bump is dispersed to the first and second spacer-like projections, and the bump is prevented from being excessively crushed. Therefore, the gap between the first semiconductor chip and the second semiconductor chip is reduced. The height can be kept constant by the height of the first and second spacer-shaped protrusions, not by the height of the first protrusion.
[0035]
In the second method for manufacturing a semiconductor device, it is preferable that the first spacer-like projection is formed of the same material as the first bump.
[0036]
In the second method for manufacturing a semiconductor device, the first spacer-like protrusion is formed at the same height as the first bump, and the second spacer-like protrusion is formed lower than the second bump. Is preferred.
[0037]
With this configuration, the sum of the heights of the first spacer-like protrusion and the second spacer-like protrusion is smaller than the sum of the height of the first bump and the height of the second bump. The first spacer-like projections and the second spacer-like projections function as spacers after the first bumps and the second bumps are crushed until electrical connection between them is sufficiently performed. Can be reliably achieved.
[0038]
In the second method for manufacturing a semiconductor device, it is preferable that at least one of the first spacer-like protrusion and the second spacer-like protrusion is formed of an organic material.
[0039]
In the method for manufacturing a second semiconductor device, a contact area between the first spacer-like projection and the second spacer-like projection is larger than or equal to a bonding area between the first bump and the second bump. Is preferred.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A first embodiment of the present invention will be described with reference to the drawings. Here, a semiconductor device having a chip-on-chip structure will be described by its manufacturing method.
[0041]
1A to 1D show cross-sectional configurations in the order of steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
[0042]
First, a circuit element and wiring (not shown) and a first internal electrode 11 were formed on the main surface, and a first protection (passivation) film 12 was formed in a region excluding the first internal electrode 11. A first semiconductor chip 10 is prepared. In addition, a circuit element and wiring (not shown) on the main surface, a first internal electrode 21 and an external electrode 22 are formed outside the first internal electrode 21, and a second protection is provided in a region excluding the second internal electrode 21 and the external electrode 22. (Passivation) The second semiconductor chip 20 on which the film 23 is formed is prepared.
[0043]
Subsequently, a first bump 13 made of, for example, a solder material is formed on the first internal electrode 11 of the first semiconductor chip 10, and a first bump 13 made of, for example, a first material is formed on the first protective film 12. A plurality of spacer-like projections 14 made of a solder material like the bumps 13 and spaced from each other are formed. Here, the first bumps 13 and the spacer-like projections 14 are formed by an electrolytic plating method, a solder printing method, or the like. Similarly, a second bump 24 made of, for example, a solder material is formed on the second internal electrode 21 of the second semiconductor chip 20. The materials of the first bumps 13, the spacer-like protrusions 14, and the second bumps 24 are not limited to solder materials, and gold, nickel, copper, or the like may be used.
[0044]
Next, as shown in FIG. 1A, the thermosetting material is made of epoxy, polyimide, acrylic, or the like so as not to cover the internal electrodes 21 and the external electrodes 22 on the main surface of the second semiconductor chip 20. The insulating resin material 25 is applied. Subsequently, the surface opposite to the main surface of the first semiconductor chip 10 on which the first bumps 13 and the spacer-like projections 14 are formed on the main surface is vacuum-adsorbed by the bonding tool 50, and the first semiconductor chip The 10 first bumps 13 and the second bumps 24 of the second semiconductor chip 20 are aligned so as to face each other.
[0045]
Next, as shown in FIG. 1B, at least one of the first bump 13 and the second bump 21 is pressed by heating and heating the first semiconductor chip 10 via the bonding tool 50. While crushing, the first bump 13 and the second bump 21 are joined.
[0046]
Next, as shown in FIG. 1C, the first semiconductor chip 10 is further pressurized via the bonding tool 50, so that the first semiconductor chip 10
Is brought into contact with the second protective film 10 of the second semiconductor chip 20. At this time, the plurality of spacer-like projections 14 come into contact with the second protective film 23 on the second semiconductor chip 20, and the first bumps 13 provided on the first semiconductor chip 10 Since the pressure applied to the second bump 24 provided on the second semiconductor chip 20 is dispersed, the first bump 13 or the second bump 24 is less likely to be crushed.
[0047]
Here, for example, when the height of the spacer-like protrusions 14 is substantially the same as the number of the first bumps 13 and the number thereof is the same, the spacer-like protrusions 14 are protected on the second semiconductor chip 20. The amount of collapse of the first bump 13 and the second bump 24 after coming into contact with the film 23 is determined from the virtual contact point of the spacer-like protrusion 14 with the protective film 23 when the spacer-like protrusion 14 is not provided. It has been confirmed by experiments that the amount of crushing of each of the bumps 13 and 24 is reduced to about 1/4 or less. As a result, the first and second bumps 13 and 24 can be reliably prevented from being excessively crushed as compared with the case where the spacer-shaped projections 14 are not provided, so that the first semiconductor chip 10 and the second semiconductor chip 20 can be suppressed. Can be prevented from varying.
[0048]
Next, as shown in FIG. 1D, the bonding tool 50 is removed from the first semiconductor chip 10, and then the insulating resin material 25 is heated and hardened, so that the first semiconductor chip 10 and the first semiconductor chip 10 are hardened. The two semiconductor chips 20 are fixed to each other.
[0049]
Thereafter, as in the conventional example shown in FIG. 3, the second semiconductor chip 20 to which the first semiconductor chip 10 has been bonded is die-bonded and wire-bonded on a lead frame, and further sealed with a sealing resin material. It may be sealed.
[0050]
Here, the insulating resin material 25 is used before the first semiconductor chip 10 is bonded to the main surface of the second semiconductor chip 20, that is, before the first bump 13 and the second bump 24 are joined. Is also applied before, but after the bumps 13 and 24 are joined together, the gap between the first semiconductor chip 10 and the second semiconductor chip 20 may be filled by utilizing the capillary phenomenon. The insulating resin material 25 does not necessarily have to be filled.
[0051]
As described above, according to the first embodiment, the spacer formed in the region except for the internal electrodes 11 and 21 between the main surfaces of the first semiconductor chip 10 and the second semiconductor chip 20. Since the spacer-shaped protrusion 14 is in contact with the second protective film 23 of the second semiconductor chip 20, the space between the first semiconductor chip 10 and the second semiconductor chip 20 is provided. However, the height is kept constant not by the height of each of the bumps 13 and 24 but by the height of the spacer-like projections 14. This prevents variations in the gap between the semiconductor chips 10 and 20 that are connected in a face-down manner, so that the internal electrodes 11 and 21 can be finely connected to each other, so that the size of the package can be reduced.
[0052]
It is preferable that the height of the spacer-shaped protrusions 14 be adjusted to the larger one of the first bumps 13 and the second bumps 24.
[0053]
Further, it is preferable that the contact area between the spacer-like projection 14 and the second protective film 23 of the second semiconductor chip 20 is larger than or equal to the bonding area between the first bump 13 and the second bump 24. .
[0054]
Further, the spacer-shaped projections 14 may be formed on the second semiconductor chip 20 instead of being provided on the first semiconductor chip 10.
[0055]
In addition, the spacer-shaped protrusions 14 do not necessarily have to have conductivity, and may be formed of an organic material such as polyimide used as a protective film of a semiconductor chip. However, for example, when the first semiconductor chip 10 is provided with the spacer-like protrusions 14 made of an organic material, the spacer-like protrusions 14 may be provided before the first bumps 13 are formed or the first bumps may be formed. 13 is provided after the formation.
[0056]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Here, similarly to the first embodiment, a semiconductor device having a chip-on-chip structure will be described by its manufacturing method.
[0057]
2A to 2D show cross-sectional configurations in the order of steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
[0058]
In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only differences from the first embodiment will be described.
[0059]
As shown in FIG. 2A, before the first semiconductor chip 10 is bonded to the second semiconductor chip 20, the first semiconductor chip 10 A second spacer-like projection 34 made of a conductive material such as a solder material or an insulating material such as epoxy is selectively formed on a portion of each semiconductor chip 10 facing each first bump 13. In the second embodiment, the spacer-like protrusions 14 formed on the first protective film 12 of the first semiconductor chip 10 are called first spacer-like protrusions.
[0060]
Subsequently, a thermosetting insulating resin material 25 made of epoxy or the like is applied so as not to cover the internal electrodes 21 and the external electrodes 22 on the main surface of the second semiconductor chip 20. Subsequently, the surface opposite to the main surface of the first semiconductor chip 10 on which the first bumps 13 and the first spacer-like protrusions 14 are formed on the main surface is vacuum-adsorbed by the bonding tool 50 to form the first semiconductor chip 10. The first bump 13 of the semiconductor chip 10 and the second bump 24 of the second semiconductor chip 20 are positioned so as to face each other.
[0061]
Next, as shown in FIG. 2B, by pressing and heating the first semiconductor chip 10 via a bonding tool 50, at least one of the first bump 13 and the second bump 21 is formed. While crushing, the first bump 13 and the second bump 21 are joined.
[0062]
Next, as shown in FIG. 2C, the first semiconductor chip 10 is further pressurized via the bonding tool 50, so that each first spacer-like projection provided on the first semiconductor chip 10 is formed. The top of 14 is brought into contact with the top of a second spacer-like projection 34 provided on the second semiconductor chip 20 so as to face each other. At this time, the plurality of first spacer-like protrusions 14 come into contact with the tops of the second spacer-like protrusions 34 on the second semiconductor chip 20, and thus the first spacer-like protrusions 14 provided on the first semiconductor chip 10 are provided. Since the pressure applied to the first bump 13 and the second bump 24 provided on the second semiconductor chip 20 is dispersed, the first bump 13 or the second bump 24 is hardly crushed.
[0063]
Here, for example, when the height dimension of the first spacer-shaped projections 14 is almost the same as the first bumps 13 and the number thereof is the same, as described in the first embodiment, The amount of crushing of the first bumps 13 and the second bumps 24 after the first spacer-like protrusion 14 comes into contact with the second spacer-like protrusion 34 provided on the second semiconductor chip 20 is determined by the first spacer. The height is reduced to about one-fourth or less as compared with the case where the projections 14 and the second spacer projections 34 are not provided. That is, since the first and second bumps 13 and 24 are suppressed from being excessively crushed as compared with the case where the first and second spacer-like projections 14 and 34 are not provided, the first semiconductor chip 10 Of the gap between the semiconductor chip 20 and the second semiconductor chip 20 can be prevented.
[0064]
Next, as shown in FIG. 2D, the bonding tool 50 is removed from the first semiconductor chip 10, and then the insulating resin material 25 is heated and cured, so that the first semiconductor chip 10 and the first semiconductor chip 10 are hardened. The two semiconductor chips 20 are fixed to each other.
[0065]
Thereafter, as in the conventional example shown in FIG. 3, the second semiconductor chip 20 to which the first semiconductor chip 10 is bonded is subjected to die bonding and wire bonding on a lead frame, and thereafter, a sealing resin material is formed. May be used for sealing.
[0066]
Here, the insulating resin material 25 is used before the first semiconductor chip 10 is bonded to the main surface of the second semiconductor chip 20, that is, before the first bump 13 and the second bump 24 are joined. Is also applied before, but after the bumps 13 and 24 are joined together, the gap between the first semiconductor chip 10 and the second semiconductor chip 20 may be filled by utilizing the capillary phenomenon. The insulating resin material 25 does not necessarily have to be filled.
[0067]
It is preferable that the height of the second spacer-like projection 34 be smaller than the height of the second bump 24.
[0068]
It is preferable that the contact area between the first spacer-like projection 14 and the second spacer-like projection 34 is larger than or equal to the junction area between the first bump 13 and the second bump 24.
[0069]
In addition, the first spacer-shaped protrusions 14 do not necessarily have to have conductivity, and may be formed of an organic material such as polyimide used as a protective film of a semiconductor chip.
[0070]
【The invention's effect】
According to the semiconductor device of the present invention, since the first semiconductor chip and the second semiconductor chip are provided with the spacer-like projections formed in the regions except for the internal electrodes on the surfaces facing each other, the first semiconductor chip has the first The gap between the semiconductor chip and the second semiconductor chip is kept constant not by the height of the bump but by the height of the spacer-like projection. As a result, variation in the gap between chips connected in a face-down manner is prevented, so that the internal electrodes can be finely connected and the size of the package can be reduced.
[Brief description of the drawings]
FIGS. 1A to 1D are sectional views in the order of steps showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same.
FIGS. 2A to 2D are sectional views in the order of steps showing a semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same.
FIG. 3 is a structural plan view showing a conventional semiconductor device.
FIG. 4 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device in the order of steps.
[Explanation of symbols]
10 First semiconductor chip
11 First internal electrode
12 First protective film
13 First bump
14 (first) spacer-like protrusions
20 Second semiconductor chip
21 Second internal electrode
22 External electrode
23 Second protective film
24 Second bump
25 Insulating resin material
50 Bonding tool

Claims (12)

主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、
主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップと、
前記第１の半導体チップと前記第２の半導体チップとの互いの対向面における前記各内部電極を除く領域に形成されたスペーサ状突起部とを備え、
前記第１の半導体チップと前記第２の半導体チップとは、前記第１のバンプと前記第２のバンプとが互いに接合することにより固着されており、
前記スペーサ状突起部は、前記第１の半導体チップ及び第２の半導体チップと接していること特徴とする半導体装置。A first semiconductor chip having a first internal electrode formed on the main surface and a first bump formed on the first internal electrode;
A second semiconductor chip having a second internal electrode formed on the main surface and a second bump formed on the second internal electrode;
A spacer-like projection formed in a region excluding each of the internal electrodes on the mutually facing surfaces of the first semiconductor chip and the second semiconductor chip;
The first semiconductor chip and the second semiconductor chip are fixed by bonding the first bump and the second bump to each other,
The semiconductor device, wherein the spacer-shaped protrusion is in contact with the first semiconductor chip and the second semiconductor chip. 主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、
主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップと、
前記第１の半導体チップの主面における前記第１の内部電極を除く領域に形成された第１のスペーサ状突起部と、
前記第２の半導体チップの主面における前記第２の内部電極を除く領域に形成された第２のスペーサ状突起部とを備え、
前記第１の半導体チップと前記第２の半導体チップとは、前記第１のバンプと前記第２のバンプとが互いに接合することにより固着されており、
前記第１のスペーサ状突起部と前記第２のスペーサ状突起部とは互いに接していること特徴とする半導体装置。A first semiconductor chip having a first internal electrode formed on the main surface and a first bump formed on the first internal electrode;
A second semiconductor chip having a second internal electrode formed on the main surface and a second bump formed on the second internal electrode;
A first spacer-like projection formed in a region of the main surface of the first semiconductor chip other than the first internal electrode;
A second spacer-like projection formed in a region of the main surface of the second semiconductor chip other than the second internal electrode,
The first semiconductor chip and the second semiconductor chip are fixed by bonding the first bump and the second bump to each other,
The semiconductor device, wherein the first spacer-like protrusion and the second spacer-like protrusion are in contact with each other. 主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップとを用意する第１の工程と、
前記第１の半導体チップの主面における前記第１の内部電極を除く領域上にスペーサ状突起部を形成する第２の工程と、
前記第１のバンプと前記第２のバンプとが互いに対向するように、前記第１の半導体チップと前記第２の半導体チップとを加熱し且つ加圧しながら固着する第３の工程とを備え、
前記第３の工程は、
前記第１のバンプの頂部と前記第２のバンプの頂部とが接して、そのうちの少なくとも一方が潰れることにより、前記第１のバンプと前記第２のバンプとが電気的に接続する工程と、
前記スペーサ状突起部の端部が前記第２の半導体チップと接することにより、前記第１のバンプ又は第２のバンプの潰れを抑制する工程とを含むことを特徴とする半導体装置の製造方法。A first semiconductor chip having a first internal electrode formed on the main surface and a first bump formed on the first internal electrode, and a second internal electrode formed on the main surface And a second step of preparing a second semiconductor chip having a second bump formed on the second internal electrode; and
A second step of forming a spacer-like projection on a region of the main surface of the first semiconductor chip other than the first internal electrode;
A third step of fixing the first semiconductor chip and the second semiconductor chip while applying heat and pressure so that the first bump and the second bump face each other,
The third step includes:
Contacting the top of the first bump and the top of the second bump and crushing at least one of them, thereby electrically connecting the first bump and the second bump;
A step of preventing the first bump or the second bump from being crushed by bringing an end of the spacer-shaped projection into contact with the second semiconductor chip. 前記スペーサ状突起部は、前記第１のバンプと同一の材料で形成することを特徴とする請求項３に記載の半導体装置の製造方法。4. The method according to claim 3, wherein the spacer-like protrusion is formed of the same material as the first bump. 5. 前記スペーサ状突起部は、前記第１のバンプと同一の高さで形成することを特徴とする請求項３又は４に記載の半導体装置の製造方法。The method according to claim 3, wherein the spacer-shaped protrusion is formed at the same height as the first bump. 前記スペーサ状突起部は、有機材料で形成することを特徴とする請求項３に記載の半導体装置の製造方法。4. The method according to claim 3, wherein the spacer-like protrusion is formed of an organic material. 前記スペーサ状突起部と前記第２の半導体チップとの接触面積は、前記第１のバンプと前記第２のバンプとの接合面積よりも大きいか等しいことを特徴とする請求項３〜６のうちのいずれか１項に記載の半導体装置の製造方法。The contact area between the spacer-shaped protrusion and the second semiconductor chip is larger than or equal to a joint area between the first bump and the second bump. 13. The method for manufacturing a semiconductor device according to claim 1. 主面上に形成された第１の内部電極及び該第１の内部電極の上に形成された第１のバンプを有する第１の半導体チップと、主面上に形成された第２の内部電極及び該第２の内部電極の上に形成された第２のバンプを有する第２の半導体チップとを用意する第１の工程と、
前記第１の半導体チップの主面における前記第１の内部電極を除く領域上に第１のスペーサ状突起部を形成する第２の工程と、
前記第２の半導体チップの主面における前記第２の内部電極を除く領域上であって、前記第１のスペーサ状突起部と対向する位置に第２のスペーサ状突起部を形成する第３の工程と、
前記第１のバンプと前記第２のバンプとが互いに対向すると共に前記第１のスペーサ状突起部と前記第２のスペーサ状突起部とが互いに対向するように、前記第１の半導体チップと前記第２の半導体チップとを加熱し且つ加圧しながら固着する第４の工程とを備え、
前記第４の工程は、
前記第１のバンプの頂部と前記第２のバンプの頂部とが接して、そのうちの少なくとも一方が潰れることにより、前記第１のバンプと前記第２のバンプとが電気的に接続する工程と、
前記第１のスペーサ状突起部の端部が前記第２のスペーサ状突起部と接することにより、前記第１のバンプ又は第２のバンプの潰れを抑制する工程とを含むことを特徴とする半導体装置の製造方法。A first semiconductor chip having a first internal electrode formed on the main surface and a first bump formed on the first internal electrode, and a second internal electrode formed on the main surface And a second step of preparing a second semiconductor chip having a second bump formed on the second internal electrode; and
A second step of forming a first spacer-like projection on a region of the main surface of the first semiconductor chip other than the first internal electrode;
Forming a second spacer-like projection at a position on the main surface of the second semiconductor chip other than the second internal electrode and opposed to the first spacer-like projection; Process and
The first semiconductor chip and the second semiconductor chip are so arranged that the first bumps and the second bumps face each other and the first spacer-like projections and the second spacer-like projections face each other. A fourth step of heating and pressurizing and fixing the second semiconductor chip,
The fourth step includes:
Contacting the top of the first bump and the top of the second bump and crushing at least one of them, thereby electrically connecting the first bump and the second bump;
A step of suppressing the collapse of the first bump or the second bump by bringing an end of the first spacer-like projection into contact with the second spacer-like projection. Device manufacturing method. 前記第１のスペーサ状突起部は、前記第１のバンプと同一の材料で形成することを特徴とする請求項８に記載の半導体装置の製造方法。9. The method according to claim 8, wherein the first spacer-like protrusion is formed of the same material as the first bump. 前記第１のスペーサ状突起部は、前記第１のバンプと同一の高さで形成し、前記第２のスペーサ状突起部は、前記第２のバンプよりも低く形成することを特徴とする請求項８又は９に記載の半導体装置の製造方法。The first spacer-like protrusion is formed at the same height as the first bump, and the second spacer-like protrusion is formed lower than the second bump. Item 10. The method for manufacturing a semiconductor device according to item 8 or 9. 前記第１のスペーサ状突起部及び第２のスペーサ状突起部のうち少なくとも一方は有機材料で形成することを特徴とする請求項８に記載の半導体装置の製造方法。9. The method according to claim 8, wherein at least one of the first spacer-like protrusion and the second spacer-like protrusion is formed of an organic material. 前記第１のスペーサ状突起部と前記第２のスペーサ状突起部との接触面積は、前記第１のバンプと前記第２のバンプとの接合面積よりも大きいか等しいことを特徴とする請求項８〜１１のうちのいずれか１項に記載の半導体装置の製造方法。The contact area between the first spacer-like protrusion and the second spacer-like protrusion is larger than or equal to a joint area between the first bump and the second bump. 12. The method for manufacturing a semiconductor device according to any one of 8 to 11.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332576A (en) * 2005-04-25 2006-12-07 Matsushita Electric Works Ltd Semiconductor device and manufacturing method thereof
JP2008004714A (en) * 2006-06-22 2008-01-10 Nec Corp Chip-laminated semiconductor device
US9570414B2 (en) 2013-11-06 2017-02-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the semiconductor device
US10312197B2 (en) 2013-12-13 2019-06-04 Toshiba Memory Corporation Method of manufacturing semiconductor device and semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332576A (en) * 2005-04-25 2006-12-07 Matsushita Electric Works Ltd Semiconductor device and manufacturing method thereof
JP2008004714A (en) * 2006-06-22 2008-01-10 Nec Corp Chip-laminated semiconductor device
US9570414B2 (en) 2013-11-06 2017-02-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the semiconductor device
US10312197B2 (en) 2013-12-13 2019-06-04 Toshiba Memory Corporation Method of manufacturing semiconductor device and semiconductor device

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