JPH02111059A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02111059A JPH02111059A JP26544588A JP26544588A JPH02111059A JP H02111059 A JPH02111059 A JP H02111059A JP 26544588 A JP26544588 A JP 26544588A JP 26544588 A JP26544588 A JP 26544588A JP H02111059 A JPH02111059 A JP H02111059A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- bonding
- fixing material
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000011368 organic material Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の構造、特に半導体素子とリード
フレームの取付構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a structure for mounting a semiconductor element and a lead frame.
第３図（ａ）は従来の半導体装置の特にダイスパッドに
半導体チップを搭載した状態を示す平面図であり、第３
図（ｂ）は第３図（ａ）のｌＮ−１１１線の断面図を示
す。図において、１は半導体素子、２はリードフレーム
、３は前記半導体素子１を載置するダイスパッド、４は
前記半導体素子１とリードフレーム２を電気的に導通さ
せる結線（金線）、５は前記半導体素子１とダイスパッ
ド３を接合する接合材である。FIG. 3(a) is a plan view showing a state in which a semiconductor chip is mounted on a die pad of a conventional semiconductor device.
FIG. 3(b) shows a sectional view taken along the line 1N-111 in FIG. 3(a). In the figure, 1 is a semiconductor element, 2 is a lead frame, 3 is a die pad on which the semiconductor element 1 is placed, 4 is a connection (gold wire) that electrically connects the semiconductor element 1 and the lead frame 2, and 5 is a gold wire. This is a bonding material for bonding the semiconductor element 1 and the die pad 3 together.
従来の半導体装置は前記半導体素子ｌとダイスパッド３
を接合する際、温度を上げて金属材料又は接着剤等の接
合材５により行っている。さらに金線等による結線４を
やりやすくするために、曲げ加工によりダイスパッド３
部をリードフレーム２より低くして、半導体素子１とリ
ードフレーム２の表面とをほぼ同一面になるように構成
している。A conventional semiconductor device has the semiconductor element 1 and the die pad 3.
When joining, the temperature is raised and a joining material 5 such as a metal material or an adhesive is used. Furthermore, in order to facilitate the connection 4 using gold wire, etc., the die pad 3 is bent.
The semiconductor element 1 and the surface of the lead frame 2 are configured to be substantially flush with each other by making the semiconductor element 1 lower than the lead frame 2.
また、従来の半導体装置では第４図に示す様にリードフ
レーム２の数が増えると、リードフレーム２のばたつき
を防ぐためにリードフレームムタ定用シート７を用いて
リードフレーム２を固定していた。Further, in conventional semiconductor devices, when the number of lead frames 2 increases as shown in FIG. 4, a lead frame fixing sheet 7 is used to fix the lead frames 2 in order to prevent the lead frames 2 from flapping.
従来の半導体装置は以上のように構成されているので、
半導体素子１をダイスパッド３に接合する際、その接合
時の温度変化により半導体素子１とダイスパッド３との
間の熱膨張（収縮）に差が生じ、そのため半導体素子１
に応力がかかり、そりや割れが起こるなどの問題点があ
った。Conventional semiconductor devices are configured as described above, so
When the semiconductor element 1 is bonded to the die pad 3, a difference in thermal expansion (contraction) occurs between the semiconductor element 1 and the die pad 3 due to temperature changes during bonding, and as a result, the semiconductor element 1
There were problems such as stress being applied to the material, causing warping and cracking.
この発明は上記のような問題点を解消するためにな＋ｔ
ｚたもので、半導体素子１にかかる応力やそりを緩和す
ることができる半導体装置を得ろことを目的とする。This invention was created in order to solve the above problems.
An object of the present invention is to obtain a semiconductor device that can alleviate stress and warpage applied to a semiconductor element 1.
この発明に係る半導体装置は、半導体素子の側面とリー
ドフレームとを絶縁性の固定材により固定したものであ
る。In a semiconductor device according to the present invention, a side surface of a semiconductor element and a lead frame are fixed with an insulating fixing material.
この発明における半導体装置は、半導体素子の側面とリ
ードフレームとを絶縁性の固定材を介して接合したので
、温度変化が生じても半導体素子に熱応力が加わらずそ
りや割れの心配がない。また半導体素子とリードフレー
ムのワイヤボンド面をほぼ同一面に構成できるので良好
なワイヤボンドが行える。さらに絶縁性の固定材により
インナーリードのばたつきが防げる。In the semiconductor device according to the present invention, the side surface of the semiconductor element and the lead frame are bonded via an insulating fixing material, so that even if a temperature change occurs, no thermal stress is applied to the semiconductor element, and there is no fear of warping or cracking. Further, since the wire bonding surfaces of the semiconductor element and the lead frame can be configured to be substantially on the same surface, good wire bonding can be achieved. Furthermore, the insulating fixing material prevents the inner lead from flapping.
〔実施例〕
第１図（ａ）はこの発明の一実施例による半導体装置を
示す平面図であり、第１図（ｂ）は第１図（ａ）のＩ−
ＩＭ断面図である。[Embodiment] FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1(b) is a plan view showing a semiconductor device according to an embodiment of the present invention.
It is an IM sectional view.
図において、１は半導体素子、２はリードフレーム、４
は結線（金線）を示す。モして６ａは前記半導体１とリ
ードフレーム２とを固定する絶縁性の固定材である。そ
してこの固定材６ａは半導体素子１の側面（ポンディン
グパッド面に対する側面）とリードフレーム２の先端側
面との間に接合する形で設けられる。In the figure, 1 is a semiconductor element, 2 is a lead frame, and 4 is a semiconductor element.
indicates a connection (gold wire). Furthermore, 6a is an insulating fixing material that fixes the semiconductor 1 and the lead frame 2 together. The fixing member 6a is provided so as to be joined between the side surface of the semiconductor element 1 (the side surface facing the bonding pad surface) and the end side surface of the lead frame 2.
すなわち、上記実施例において、半導体素子１は絶縁性
の固定材６ａによりリードフレーム２の先端に接合され
る。そして固定材６ａとしては、例えば絶縁性の有機材
料が考えられ、特に熱圧着シートを用いた場合には接合
部材なしで熱圧着により接合することができる。また、
接合部が半導体素子１の側面とリードフレーム２先端の
側面との間に存在しているため、接合後の半導体素子１
の変形がなくなる。That is, in the above embodiment, the semiconductor element 1 is bonded to the tip of the lead frame 2 using the insulating fixing material 6a. As the fixing material 6a, for example, an insulating organic material can be considered, and especially when a thermocompression bonding sheet is used, it is possible to join by thermocompression bonding without a bonding member. Also,
Since the bonding portion exists between the side surface of the semiconductor element 1 and the side surface of the tip of the lead frame 2, the semiconductor element 1 after bonding
deformation disappears.
さらに、半導体素子１はリードフレーム２の先端の側面
に接合されているので第３図（ｂ）のようにダイスパッ
ド３をリードフレーム２に対して低い位置に曲げ加工す
る作業なくして良好なワイヤボンドが行える。Furthermore, since the semiconductor element 1 is bonded to the side surface of the tip of the lead frame 2, it is not necessary to bend the die pad 3 to a lower position with respect to the lead frame 2 as shown in FIG. 3(b). Bond can be done.
さらに従来第４図のようにリードフレーム２の数が増え
るとリードフレーム２のばたつきを防ぐためリードフレ
ーム固定シート７を使用しているが、今回の絶縁性固定
材６ａはこれと同等の効果を持つ。Furthermore, as shown in Fig. 4, when the number of lead frames 2 increases, a lead frame fixing sheet 7 is used to prevent the lead frames 2 from fluttering, but this insulating fixing material 6a has the same effect. have
なお上記実施例では、絶縁性固定材８ａが半導体素子１
の側面全周に施されているものを示したが第２図に示す
ようにリードフレーム２の先端の側面部のみに絶縁性固
定材６ｂが施されていても同様の効果が得られる。Note that in the above embodiment, the insulating fixing material 8a is attached to the semiconductor element 1.
2, the same effect can be obtained even if the insulating fixing material 6b is applied only to the side surface of the tip of the lead frame 2, as shown in FIG.
以上のように、この発明によれば半導体素子の側面とリ
ードフレームとの間に絶縁性の固定材を介して接合した
ので、半導体素子にかかる応力が緩和され、そりや割れ
を防止する効果がある。さらに良好なワイヤボンドが得
られ、またリードフレームのばたつきを防止する効果も
ある。As described above, according to the present invention, since the side surface of the semiconductor element and the lead frame are bonded via an insulating fixing material, the stress applied to the semiconductor element is alleviated, and the effect of preventing warping and cracking is achieved. be. Furthermore, a better wire bond can be obtained, and there is also an effect of preventing flapping of the lead frame.
第１図（ａ）はこの発明の一実施例による半導体装置を
示す平面図、第１図（ｂ）は第１図（ｍｌ）のＩ−Ｉ線
断面図、第２図はこの発明の他の実施例を示す半導体装
置の平面図、第３図（ａ）は従来の半導体装置を示す平
面図、第３図（ｂ）は第３図（１） Ｉ −■線断面図
、第４図は従来の半導体装置を示す平面図である。
図において、１は半導体素子、２はリードフレーム、４
は結線、６ｍ、６ｂは絶縁性固定材を示す。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line II in FIG. 1(ml), and FIG. FIG. 3(a) is a plan view of a conventional semiconductor device, FIG. 3(b) is a sectional view taken along the line I-■ of FIG. 3(1), and FIG. 1 is a plan view showing a conventional semiconductor device. In the figure, 1 is a semiconductor element, 2 is a lead frame, and 4 is a semiconductor element.
6m and 6b indicate a wire connection, and 6m and 6b indicate an insulating fixing material. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
を介して接合することを特徴とする半導体装置。A semiconductor device characterized in that a side surface of a semiconductor element and a lead frame are joined via an insulating fixing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26544588A JPH02111059A (en) | 1988-10-20 | 1988-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26544588A JPH02111059A (en) | 1988-10-20 | 1988-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111059A true JPH02111059A (en) | 1990-04-24 |
Family
ID=17417253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26544588A Pending JPH02111059A (en) | 1988-10-20 | 1988-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129871A (en) * | 1989-10-16 | 1991-06-03 | Oki Electric Ind Co Ltd | Resin sealed type semiconductor device |
| JPH06104294A (en) * | 1992-09-17 | 1994-04-15 | Nec Corp | Lead frame |
| JPH0855952A (en) * | 1994-08-16 | 1996-02-27 | Nec Kyushu Ltd | Semiconductor device and manufacture thereof |
-
1988
- 1988-10-20 JP JP26544588A patent/JPH02111059A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129871A (en) * | 1989-10-16 | 1991-06-03 | Oki Electric Ind Co Ltd | Resin sealed type semiconductor device |
| JPH06104294A (en) * | 1992-09-17 | 1994-04-15 | Nec Corp | Lead frame |
| JPH0855952A (en) * | 1994-08-16 | 1996-02-27 | Nec Kyushu Ltd | Semiconductor device and manufacture thereof |
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