JPS63248155A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63248155A JPS63248155A JP62083152A JP8315287A JPS63248155A JP S63248155 A JPS63248155 A JP S63248155A JP 62083152 A JP62083152 A JP 62083152A JP 8315287 A JP8315287 A JP 8315287A JP S63248155 A JPS63248155 A JP S63248155A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- semiconductor chip
- resin
- internal stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 abstract description 9
- 230000035882 stress Effects 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 239000012141 concentrate Substances 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005336 cracking Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に係り、特に樹脂封止型半導体
装置のダイパッド構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a die pad structure of a resin-sealed semiconductor device.
従来のこの種の半導体装置のダイパッド構造としては、
第３図に示すものがあった。The conventional die pad structure of this type of semiconductor device is as follows:
There was one shown in Figure 3.
第３図において、１は半導体チップ、６は前記半導体チ
ップ１を接着する導電板（ダイパッド）である。In FIG. 3, 1 is a semiconductor chip, and 6 is a conductive plate (die pad) to which the semiconductor chip 1 is bonded.
第３図に示すように、従来のダイパッド構造は半導体チ
ップ１が接着する部分において、その形状は平面状にな
っていた。As shown in FIG. 3, in the conventional die pad structure, the portion to which the semiconductor chip 1 is bonded has a planar shape.
したがって、従来のダイパッド構造では、基板実装時の
熱ストレス（はんだリフロ一方式）により、半導体装置
全体が高温にさらされ、この影響で樹脂封止された封止
樹脂とダイパッド材料との線膨張率の違いで封止樹脂内
部に内部応力が生じ、それがダイパッド６のエツジ部に
集中するため、その部分から樹脂クラックが発生すると
いう問題点があった。Therefore, in the conventional die pad structure, the entire semiconductor device is exposed to high temperatures due to thermal stress during board mounting (solder reflow method), and this affects the linear expansion coefficient of the sealing resin and the die pad material. This difference causes internal stress to occur inside the sealing resin, which concentrates on the edge portion of the die pad 6, resulting in the problem that resin cracks occur from that portion.
この発明は、上記のような問題点を解消するためになさ
れたもので、樹脂クラックの防止をはかった半導体装置
を得ることを目的としている。This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor device in which resin cracks are prevented.
（問題点を解決するための手段）
この発明に係る半導体装置は、半導体チップが接着され
るダイパッド形状を波板状に構成したも・のである。(Means for Solving the Problems) A semiconductor device according to the present invention has a die pad to which a semiconductor chip is bonded having a corrugated plate shape.
この発明においては、ダイパッド形状を波板状に構成し
たことから、基板実装時の熱ストレスによる封止樹脂内
部の内部応力はダイパッドエツジに集中しなくなる。In this invention, since the die pad has a corrugated plate shape, internal stress inside the sealing resin due to thermal stress during board mounting is not concentrated on the die pad edge.
（実施例） 以下、この発明の一実施例を図面について説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.
第１図、第２図はこの発明の一実施例を示す図で、第１
図は樹脂封止された半導体装置の上面図、第２図は、第
１図のダイパッドの側面図である。第１図、第２図にお
いて、１は半導体チップ、２は波板状に形成されたダイ
パッドであり、このダイパッド２上に半導体チップ１が
接着剤で固定される。３は接続用ワイヤで、半導体チッ
プ１と外部リード４とを電気的に接続する。５は封止樹
脂を示しており、外部リード４の一部を残して、後はす
べて封止樹脂５で封止される。FIG. 1 and FIG. 2 are diagrams showing one embodiment of the present invention.
The figure is a top view of a resin-sealed semiconductor device, and FIG. 2 is a side view of the die pad of FIG. 1. In FIGS. 1 and 2, 1 is a semiconductor chip, 2 is a die pad formed in the shape of a corrugated plate, and the semiconductor chip 1 is fixed onto this die pad 2 with an adhesive. A connecting wire 3 electrically connects the semiconductor chip 1 and the external leads 4. Reference numeral 5 indicates a sealing resin, and except for a part of the external lead 4, the rest is all sealed with the sealing resin 5.
このように、ダイパッド２を波板状に形成することによ
り、半導体装置の基板実装時の熱ストレスに対する封止
樹脂内部の内部応力を分散させ、ダイパッド２のエツジ
に集中しないような構造とすることができる。In this way, by forming the die pad 2 in a corrugated plate shape, the internal stress inside the sealing resin due to thermal stress during mounting of the semiconductor device on the board is dispersed, and the structure is such that it does not concentrate on the edges of the die pad 2. Can be done.
なお、上記実施例では、デュアルインライン形の半導体
装置を例にとって説明したが、シングルインライン形等
、類似構造の半導体装置すべてに適用可能である。Note that although the above embodiment has been explained by taking a dual in-line type semiconductor device as an example, the present invention is applicable to all semiconductor devices having a similar structure, such as a single in-line type.
〔発明の効果）
以上説明したように、この発明は、半導体チップが接着
されるダイパッド形状を波板状に構成したので、封止樹
脂内部の内部応力を分散させ、ダイパッドエツジに集中
することがさけられる。したがって、樹脂クラックの防
止が可能となり、高品質の半導体装置が得られる効果が
ある。 。[Effects of the Invention] As explained above, in the present invention, the die pad to which the semiconductor chip is bonded has a corrugated plate shape, so that the internal stress inside the sealing resin can be dispersed and concentrated on the die pad edge. I can be yelled at. Therefore, resin cracks can be prevented and a high quality semiconductor device can be obtained. .
第１図はこの発明の一実施例を示す半導体装置の上面図
、第２図は、第１図のダイパッドの側面図、第３図は従
来のダイパッドの側面図である。
図において、１は半導体チップ、２はダイパッド、３は
接続用ワイヤ、４は外部リード、５は封止樹脂である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
第３図FIG. 1 is a top view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a side view of the die pad of FIG. 1, and FIG. 3 is a side view of a conventional die pad. In the figure, 1 is a semiconductor chip, 2 is a die pad, 3 is a connection wire, 4 is an external lead, and 5 is a sealing resin. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3
Claims (1)
半導体装置において、前記ダイパッド形状を波板状に構
成したことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip is bonded to a die pad and sealed with a resin, wherein the die pad has a corrugated plate shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62083152A JPS63248155A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62083152A JPS63248155A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63248155A true JPS63248155A (en) | 1988-10-14 |
Family
ID=13794259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62083152A Pending JPS63248155A (en) | 1987-04-03 | 1987-04-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63248155A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04125458U (en) * | 1991-05-07 | 1992-11-16 | 山口日本電気株式会社 | Lead frame |
| KR20010044948A (en) * | 1999-11-01 | 2001-06-05 | 마이클 디. 오브라이언 | Semiconductor package |
| JP2007053195A (en) * | 2005-08-17 | 2007-03-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
-
1987
- 1987-04-03 JP JP62083152A patent/JPS63248155A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04125458U (en) * | 1991-05-07 | 1992-11-16 | 山口日本電気株式会社 | Lead frame |
| KR20010044948A (en) * | 1999-11-01 | 2001-06-05 | 마이클 디. 오브라이언 | Semiconductor package |
| JP2007053195A (en) * | 2005-08-17 | 2007-03-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP4668729B2 (en) * | 2005-08-17 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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