JPS63128736A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS63128736A JPS63128736A JP61274173A JP27417386A JPS63128736A JP S63128736 A JPS63128736 A JP S63128736A JP 61274173 A JP61274173 A JP 61274173A JP 27417386 A JP27417386 A JP 27417386A JP S63128736 A JPS63128736 A JP S63128736A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip
- substrate
- semiconductor
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000007789 sealing Methods 0.000 abstract description 34
- 239000000758 substrate Substances 0.000 abstract description 32
- 229920005989 resin Polymers 0.000 abstract description 10
- 239000011347 resin Substances 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000011093 chipboard Substances 0.000 abstract 1
- POIUWJQBRNEFGX-XAMSXPGMSA-N cathelicidin Chemical compound C([C@@H](C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CO)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H]([C@@H](C)CC)C(=O)NCC(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)CC)C(=O)N[C@@H](C(C)C)C(=O)N[C@@H](CCC(N)=O)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)CC)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H](CC(N)=O)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](C(C)C)C(=O)N1[C@@H](CCC1)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)O)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CO)C(O)=O)NC(=O)[C@H](CC=1C=CC=CC=1)NC(=O)[C@H](CC(O)=O)NC(=O)CNC(=O)[C@H](CC(C)C)NC(=O)[C@@H](N)CC(C)C)C1=CC=CC=C1 POIUWJQBRNEFGX-XAMSXPGMSA-N 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 206010011224 Cough Diseases 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体チップを搭載基板上に接続固定して
なる、チップオンボード構成の半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element having a chip-on-board configuration in which a semiconductor chip is connected and fixed on a mounting substrate.
従来のチップオンボード(C,O,B)構成の半導体素
子は、第8図^、田)に示すように、セラミックやガラ
ス・エポキシ樹脂などからなる基板21上に、半導体チ
ップ22を直接ダイボンドにより固着し、該半導体チッ
プ22のボンディングバンドと前記基板21上に形成し
た導電パターンとをボンディングワイヤ23で接続した
のち、封止樹脂24あるいはキャップ25で封止を行っ
ている。また基板21上には必要に応じ他のチップ部品
26が搭載されている。A conventional semiconductor device with a chip-on-board (C, O, B) configuration is produced by directly die-bonding a semiconductor chip 22 onto a substrate 21 made of ceramic, glass, epoxy resin, etc., as shown in FIG. After the bonding band of the semiconductor chip 22 and the conductive pattern formed on the substrate 21 are connected with a bonding wire 23, sealing is performed with a sealing resin 24 or a cap 25. Further, other chip components 26 are mounted on the substrate 21 as required.
ところが、従来のチップオンボード構成の半導体素子は
、基板上に半導体チップを1個づつ平面的に配置してい
るため、多数の半導体チップを基板上に搭載する場合は
、半導体チップ数分の面積を必要とし、高実装密度が得
られないという問題点があった。However, in conventional semiconductor devices with a chip-on-board configuration, one semiconductor chip is arranged flat on a substrate, so when mounting a large number of semiconductor chips on a substrate, the area corresponding to the number of semiconductor chips is required. The problem was that high packaging density could not be obtained.
本発明は、従来のチップオンボード構成の半導体素子の
かかる問題点を解決するためなされたもので、高実装密
度を有するチップオンボード構成の半導体素子を提供す
ることを目的とするものである。The present invention has been made to solve the problems of conventional semiconductor devices with a chip-on-board configuration, and it is an object of the present invention to provide a semiconductor device with a chip-on-board configuration that has a high packaging density.
〔問題点を解決するための手段及び作用〕上記問題点を
解決するため、本発明は、搭載基板に第1の半導体チッ
プをダイボンドにより固着し、該第1の半導体チップ上
に第2の半導体チップを立体的に配置して、各半導体チ
ップをそれぞれ搭載基板上の導電パターンに接続すると
共に、各半導体チップを封止して半導体素子を構成する
ものである。[Means and effects for solving the problems] In order to solve the above problems, the present invention fixes a first semiconductor chip to a mounting substrate by die bonding, and attaches a second semiconductor chip onto the first semiconductor chip. Chips are arranged three-dimensionally, each semiconductor chip is connected to a conductive pattern on a mounting substrate, and each semiconductor chip is sealed to form a semiconductor element.
このように構成することにより、2個の半導体チップを
立体的に実装され、1チツプ当たりの実装面積の縮小化
が計れ、高密度実装が可能となる。With this configuration, two semiconductor chips can be mounted three-dimensionally, the mounting area per chip can be reduced, and high-density mounting can be achieved.
以下実施例について説明する。第1図は、本発明に係る
半導体素子の第1実施例を示す断面図である。この実施
例は、セラミックやガラス・エポキシ樹脂等からなる搭
載基板1に第1の半導体チップ2をダイボンドにより固
着し、該チップ2のボンディングバンドと前記搭載基板
1上に形成した導電パターンをボンディングワイヤ3を
用いて接続したのちセラミック、ガラスエポキシ樹脂な
どからなるキャップ4を被せて基板lに接着し、封止を
行う。Examples will be described below. FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting substrate 1 made of ceramic, glass, epoxy resin, etc. by die bonding, and a bonding band of the chip 2 and a conductive pattern formed on the mounting substrate 1 are connected using bonding wires. 3, and then a cap 4 made of ceramic, glass epoxy resin, etc. is placed on the cap 4 and bonded to the substrate 1 for sealing.
次いで前記キャップ4上に第2の半導体チップ5をダイ
ボンドにより固着し、該第2半導体チフブ5のポンディ
ングパッドと基板1上の導電パターンとをボンディング
ワイヤ6で接続し、最後にエポキシ、ポリイミド、シリ
コン系などの封止樹脂を、第1半導体チップ2を封止し
たキャップ4及びその上に載置した第2半導体チップ5
の全体を封止するようにボッティングして封止部7を形
成し、チップオンボード構成の半導体素子を構成する。Next, the second semiconductor chip 5 is fixed on the cap 4 by die bonding, the bonding pad of the second semiconductor chip 5 and the conductive pattern on the substrate 1 are connected with a bonding wire 6, and finally, epoxy, polyimide, A cap 4 sealing the first semiconductor chip 2 with a sealing resin such as silicone and a second semiconductor chip 5 placed thereon.
A sealing portion 7 is formed by botting so as to seal the entire portion, thereby configuring a semiconductor element having a chip-on-board configuration.
8は基板l上に接続固定した他のチップ部品である。8 is another chip component connected and fixed on the substrate l.
このように構成することにより、1個の半導体チップ取
付面積に対して2個の半導体チップを搭載することがで
き、高実装密度が得られる。With this configuration, two semiconductor chips can be mounted on one semiconductor chip mounting area, resulting in high packaging density.
第2図は、本発明の第2実施例を示す断面図である。こ
の実施例は、第1図に示した実施例における封止樹脂の
ボッティングにより形成した封止部7で第2半導体チッ
プを封止する代わりに、キャンプを用いて封止したもの
である。すなわち、図示のように、第1半導体チフブ2
を封止したキャンプ4と、該キャップ4上にグイボンデ
ィングして載置した第2半導体チップ5とに第2のキャ
ンプ9を被せて基板lに接着し、これらを一体的に封止
するものである。FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, instead of sealing the second semiconductor chip with the sealing portion 7 formed by botting the sealing resin in the embodiment shown in FIG. 1, the second semiconductor chip is sealed using a camp. That is, as shown in the figure, the first semiconductor chip 2
A second camp 9 is placed over the sealed camp 4 and the second semiconductor chip 5 placed on the cap 4 by bonding and bonded to the substrate l, and these are integrally sealed. It is.
第3図は、本発明の第3実施例を示す断面図である。こ
の実施例は搭載基板1に第1の半導体チップ2をダイボ
ンドで固着し、該チップ2のポンディングパッドと搭載
基板l上に形成した導電パターンとをボンディングワイ
ヤ3で接続したのち、封止樹脂をボッティングして封止
部lOを形成する。FIG. 3 is a sectional view showing a third embodiment of the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting substrate 1 by die bonding, a bonding pad of the chip 2 and a conductive pattern formed on the mounting substrate 1 are connected with a bonding wire 3, and then a sealing resin is A sealing portion IO is formed by botting.
なお、このボッティングによる封止部10を形成する際
、上面がほぼ平面状になるように形成する。In addition, when forming the sealing part 10 by this botting, it is formed so that the upper surface is substantially planar.
次いでボッティング封止部lOの上面に第2半導体チッ
プ5をダイボンドにより固着したのち、該チップ5のポ
ンディングパッドと基板1の導電パターンとをボンディ
ングワイヤ6で接続し、更に第1半導体チップ2に施し
た封止部10と、前記第2半導体チップ5とを一体的に
封止するように、封止樹脂をボッティングして封止部1
1を形成し、半導体素子を構成するものである。Next, after fixing the second semiconductor chip 5 to the upper surface of the botting sealing part 10 by die bonding, the bonding pad of the chip 5 and the conductive pattern of the substrate 1 are connected with the bonding wire 6, and then the first semiconductor chip 2 The sealing resin is potted to integrally seal the sealing portion 10 applied to the sealing portion 1 and the second semiconductor chip 5.
1 and constitutes a semiconductor element.
第4図は、本発明の第4実施例を示す断面図である。こ
の実施例は、上記各実施例と同様に、搭載基板1に第1
半導体チップ2をダイボンドにより固着し、該チップ2
のボンディングバンドと基板1の導電パターンとをボン
ディングワイヤ3で接続したのち、このボンディングワ
イヤ3を含めた第1半導体チンブ2より若干大きい内側
面積を有し、且つ第1半導体チフブ2より若干高さを大
に形成した四角形状の枠を、第1半導体チVブ2を囲む
ように基板1上に載置して接着する。FIG. 4 is a sectional view showing a fourth embodiment of the present invention. In this embodiment, similarly to each of the above embodiments, a first
The semiconductor chip 2 is fixed by die bonding, and the chip 2 is
After connecting the bonding band and the conductive pattern of the substrate 1 with the bonding wire 3, the bonding band has a slightly larger inner area than the first semiconductor chip 2 including the bonding wire 3, and has a slightly higher height than the first semiconductor chip 2. A rectangular frame having a large size is placed on the substrate 1 so as to surround the first semiconductor chip 2 and bonded.
次いで該枠12上に第2半導体チップ5をダイボンドに
より接着し、該チップ5と基板1とをボンディングワイ
ヤ6で接続したのち、前記枠12及び第2半導体チフプ
5を含めて封止するように封止樹脂をポツティングして
封止部13を形成する。Next, the second semiconductor chip 5 is bonded onto the frame 12 by die bonding, and the chip 5 and the substrate 1 are connected with bonding wires 6, and then the frame 12 and the second semiconductor chip 5 are sealed together. A sealing portion 13 is formed by potting a sealing resin.
この実施例では封止工程が一回で済むという利点がある
。This embodiment has the advantage that only one sealing step is required.
第5図は、本発明の第5実施例を示す断面図である。こ
の実施例では搭載基板1に第1半導体チップ2をダイボ
ンドにより固着して、該チップ2と基板1の導電パター
ンとをボンディングワイヤ3で接続したのち、第1半導
体チップ2の上面に、ボンディングワイヤ3に接触しな
いように、チ、2プ載置幅広面14′を有する絶縁性台
板14を接合し、咳台板14の幅広面14′に第2半導
体チップ5をダイボンドにより接合し、第2半導体チッ
プ5と基板1とをボンディングワイヤ6により接続した
のち、第1半導体チンプ2及び第2半導体チップ5を共
通に封止するように封止樹脂をポツティングして封止部
15を形成する。このように構成した場合も一回の封止
工程により封止部を形成することができる。FIG. 5 is a sectional view showing a fifth embodiment of the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting board 1 by die bonding, and the chip 2 and the conductive pattern of the board 1 are connected with a bonding wire 3. An insulating base plate 14 having a wide chip mounting surface 14' is bonded so as not to contact the chips 3, and a second semiconductor chip 5 is bonded to the wide surface 14' of the cough base plate 14 by die bonding. After the two semiconductor chips 5 and the substrate 1 are connected by bonding wires 6, a sealing resin is potted to commonly seal the first semiconductor chip 2 and the second semiconductor chip 5 to form a sealing part 15. . Even with this configuration, the sealing portion can be formed by a single sealing process.
第6図は、本発明の第6実施例を示す断面図である。こ
の実施例は、第1図に示した実施例と同様に第1半導体
チップ2に封止用キャンプ4を被せたのち、該キャンプ
4上に該キャップ4とほぼ同一の外形を有するワイヤシ
ョート防止用枠16を接着する0次いで該封止用キャン
プ4の上面に第゛ 2半導体チフブ5をダイボンドで接
着したのち、該チップ5のポンディングパッドと基板l
の電極パターンとをボンディングワイヤ6で接続する。FIG. 6 is a sectional view showing a sixth embodiment of the present invention. In this embodiment, similarly to the embodiment shown in FIG. 1, a sealing camp 4 is placed over the first semiconductor chip 2, and then a wire short-circuit preventive device is placed on the camp 4 to prevent wire short-circuiting. Next, the second semiconductor chip 5 is bonded to the upper surface of the sealing camp 4 by die bonding, and then the bonding pad of the chip 5 and the substrate l are bonded.
are connected to the electrode pattern using bonding wires 6.
この際ボンディングワイヤ6はワイヤショート防止用枠
16で支持されるように配設される0次いでキャンプ4
及び第2半導体チフプ5及び枠16の全体を封止するよ
うに封止用樹脂をポツティングして封止部17を形成す
る。At this time, the bonding wire 6 is supported by the wire short-circuit prevention frame 16.
Then, a sealing resin is potted to seal the entire second semiconductor chip 5 and frame 16, thereby forming a sealing portion 17.
一般に2つの半導体チップを立体的に配置した場合高さ
が高くなり、したがって第2チツプのポンディングパッ
ドと基板の導電パターンとを接続するボンディングワイ
ヤの長、さが長くなり、該ワイヤとチンプエッジ間のシ
ョートが発生しやすくなるが、この実施例では、第2半
導体チップ5のポンディングパッドへ接続されるボンデ
ィングワイヤ6は、ワイヤショート防止用枠16で保持
されているため、上記ワイヤショートの発生を有効に防
止することができる。Generally, when two semiconductor chips are arranged three-dimensionally, the height becomes high, and therefore the length of the bonding wire that connects the bonding pad of the second chip and the conductive pattern of the substrate becomes long, and the distance between the wire and the chimp edge increases. However, in this embodiment, since the bonding wire 6 connected to the bonding pad of the second semiconductor chip 5 is held by the wire short prevention frame 16, the occurrence of the wire short is likely to occur. can be effectively prevented.
第7図は、本発明の第7実施例を示す断面図である。こ
の実施例は、第3図に示した第3実施例のように、搭載
基板1に第1半導体チップ2をダイボンドにより固着し
、該チップ2のポンディングパッドと基板1上に形成さ
れた導電パターンとをボンディングワイヤ3で接続した
のち、封止樹脂をポツティングして封止部10を形成す
る。FIG. 7 is a sectional view showing a seventh embodiment of the present invention. In this embodiment, as in the third embodiment shown in FIG. After connecting the pattern with the bonding wire 3, a sealing resin is potted to form a sealing portion 10.
次に、この封止部lOの2倍以上の高さを有し、上板1
8’の内面の一部から側板18′の内面を通り、該側板
18#の外面下端部に到る所定の導電パターン19を形
成したキャップ18の上板18′の内面に第2半導体チ
ップ5をダイボンドにより接着し、該チップ5のポンデ
ィングパッドとキャップ18の内面に形成した導電パタ
ーン19とをボンディングワイヤ6で接続する0次にこ
のように構成したキャップ18を、前記第1半導体チッ
プ2を封止した封止部10上に被せて基板1に接着する
と共に、キャップ18の側板18“の外面底部に形成さ
れている導電パターン19と基板1に形成されている導
電パターンとをハンダ20等により接続し、半導体素子
を構成するものである。Next, the upper plate 1 has a height more than twice that of this sealing part lO.
A second semiconductor chip 5 is disposed on the inner surface of the upper plate 18' of the cap 18, on which a predetermined conductive pattern 19 is formed from a part of the inner surface of the cap 18, passing through the inner surface of the side plate 18' and reaching the lower end of the outer surface of the side plate 18#. The bonding pad of the chip 5 and the conductive pattern 19 formed on the inner surface of the cap 18 are connected by a bonding wire 6. The conductive pattern 19 formed on the bottom of the outer surface of the side plate 18'' of the cap 18 and the conductive pattern formed on the substrate 1 are bonded together using solder 20. etc., to form a semiconductor element.
本発明は、上記各実施例に示したものに限らず、例えば
上記各実施例に示した第1半導体チップ及び第2半導体
チップに対する封止手段あるいはそれら支持手段等は適
宜組み合わせることができる。The present invention is not limited to what is shown in each of the above embodiments, and for example, the sealing means for the first semiconductor chip and the second semiconductor chip or their supporting means shown in each of the above embodiments can be combined as appropriate.
以上実施例に基づいて説明したように、本発明によれば
、複数個の半導体チップを搭載基板上に立体的に配設し
たので、1チツプ当たりの所要面積を減少させ、高実装
密度のチップオンボード構成の半導体素子を得ることが
できる。As described above based on the embodiments, according to the present invention, a plurality of semiconductor chips are arranged three-dimensionally on a mounting board, which reduces the required area per chip and allows for high packaging density. A semiconductor device with an on-board configuration can be obtained.
第1図乃至第7図は、それぞれ本発明の第1乃至第7実
施例を示す断面図、第8図は^、 (B)は、従来のチ
ップオンボード構成の半導体素子の構成例を示す断面図
である。
図において、lは搭載基板、2は第1半導体チップ、3
.6はボンディングワイヤ、4.9はキャップ、5は第
2半導体チップ、7.10.11.13゜15、17は
封止部、8はチップ部品、12は枠、14は合板、16
はワイヤショート防止用枠、18はキャップ、19は導
電パターン、20はハンダを示す。
特許出願人 オリンパス光学工業株式会社代理人弁理士
最 上 健 治7215、第1図
第2図
第3図
第4図
第5図
第6図1 to 7 are cross-sectional views showing the first to seventh embodiments of the present invention, respectively, and FIG. 8 is a cross-sectional view showing an example of the structure of a semiconductor element having a conventional chip-on-board structure. FIG. In the figure, l is a mounting board, 2 is a first semiconductor chip, and 3 is a mounting board.
.. 6 is a bonding wire, 4.9 is a cap, 5 is a second semiconductor chip, 7.10.11.13° 15, 17 is a sealing part, 8 is a chip component, 12 is a frame, 14 is a plywood board, 16
18 indicates a wire short prevention frame, 18 a cap, 19 a conductive pattern, and 20 a solder. Patent applicant Olympus Optical Industry Co., Ltd. Patent attorney Kenji Mogami 7215, Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
着し、該第1の半導体チップ上に第2の半導体チップを
立体的に配置して、各半導体チップをそれぞれ搭載基板
上の導電パターンに接続すると共に、各半導体チップを
封止したことを特徴とする半導体素子。A first semiconductor chip is fixed to a mounting board by die bonding, a second semiconductor chip is three-dimensionally arranged on the first semiconductor chip, and each semiconductor chip is connected to a conductive pattern on the mounting board, respectively. , a semiconductor element characterized in that each semiconductor chip is sealed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61274173A JPS63128736A (en) | 1986-11-19 | 1986-11-19 | Semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61274173A JPS63128736A (en) | 1986-11-19 | 1986-11-19 | Semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63128736A true JPS63128736A (en) | 1988-06-01 |
Family
ID=17538052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61274173A Pending JPS63128736A (en) | 1986-11-19 | 1986-11-19 | Semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63128736A (en) |
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