JP2007053195A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2007053195A
JP2007053195A JP2005236591A JP2005236591A JP2007053195A JP 2007053195 A JP2007053195 A JP 2007053195A JP 2005236591 A JP2005236591 A JP 2005236591A JP 2005236591 A JP2005236591 A JP 2005236591A JP 2007053195 A JP2007053195 A JP 2007053195A
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Japan
Prior art keywords
tab
semiconductor chip
semiconductor device
frame
formed
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JP2005236591A
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Japanese (ja)
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JP4668729B2 (en
JP2007053195A5 (en
Inventor
Mayumi Ikeda
Koichi Kanemoto
Yoichi Kawada
Toshihiro Shiotsuki
敏弘 塩月
真由美 池田
洋一 河田
光一 金本
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Renesas Technology Corp
株式会社ルネサステクノロジ
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of effectively utilizing a semiconductor chip with a die attach film attached to a general lead frame product. Specifically, the present invention provides a technique capable of suppressing warpage and resin cracks in a semiconductor device in which a semiconductor chip having a die attach film attached is mounted on a tab and then sealed with a resin.
A semiconductor chip 4 is mounted on a frame-shaped frame tab 2 cut through the inside. The frame tab 2 and the semiconductor chip 4 are connected using a die attach film 6 attached to the entire back surface of the semiconductor chip 4. Then, the semiconductor chip 4 is sealed with a resin 8. At this time, the die attach film 6 formed on the back surface of the semiconductor chip 4 and the resin 8 are brought into direct contact.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device using a lead frame.

  Japanese Patent Application Laid-Open No. 10-214850 (Patent Document 1) discloses a technique for providing an electronic component mounting substrate for manufacturing an electronic component device such as a semiconductor package having no package cracks and excellent reliability. Yes. Specifically, a film-like organic die bonding material is placed on a support substrate having a hole. At this time, the film is affixed on the support substrate at a temperature, pressure, and time that satisfy the condition that the film does not fall down from the hole. Next, the semiconductor chip is placed on the film and bonded. Also at this time, the semiconductor device is manufactured by bonding the semiconductor chip at a temperature, pressure, and time that satisfy the condition that the film does not protrude and fall down.

Japanese Patent Laid-Open No. 6-268146 (Patent Document 2) discloses a technique for improving the crack resistance of a package during solder reflow. Specifically, a hole is formed at the center of the die pad. Then, a semiconductor element is mounted on this die pad. The front surface and the back surface of the semiconductor element are covered with a highly adhesive material such as polyimide, for example. Although a part of the back surface of the semiconductor element is exposed, a high adhesion material is formed on the exposed part, so that the adhesion between the semiconductor element and the sealing resin is improved. Note that the die bonding material is formed only between the back surface of the semiconductor element and the die pad.
JP-A-10-214850 JP-A-6-268146

  When a semiconductor chip is mounted on a tab in a lead frame, a liquid conductive paste material has been used. However, in recent years, with the thinning of semiconductor wafers, an adhesive die attach film (Die Attach Film) has been applied in advance to the back surface of the semiconductor wafer. The first reason is to improve the strength of the thinned semiconductor wafer. Since the strength (bending strength) of the thinned semiconductor wafer is reduced, the semiconductor wafer is easily cracked during conveyance to the manufacturing process after the thinning step (BG step) of the semiconductor wafer. Therefore, after thinning the semiconductor wafer, by attaching a die attach film to the back side of the semiconductor wafer, the strength of the semiconductor wafer can be improved and cracking during transportation can be suppressed. The second is performed in order to simplify the die bonding process for mounting the semiconductor chip on the tab and to improve the adhesion between the semiconductor chip and the tab.

  In the case of mounting a semiconductor chip using a liquid conductive paste material, a coating process is required to mount the semiconductor chip after applying the conductive paste material on the main surface of the tab. However, when a die attach film is used, since it is attached after the BG process, in the die bonding process, it is possible to fix the semiconductor chip on the tab only by mounting the semiconductor chip. In addition, the liquid conductive paste material is applied by a multi-point application method using a plurality of paste nozzles, but there may be variations in the applied paste material or unfilled locations. On the other hand, in the die attach film, since a uniform adhesive layer is formed on the substrate, no gap is generated between the tab and the semiconductor chip as compared with the liquid conductive paste material.

  For example, the thickness of the semiconductor wafer forming the nonvolatile memory is about 220 μm or less, and a die attach film is attached to the back surface of the semiconductor wafer. This semiconductor wafer is diced in a state where a die attach film is attached, and is singulated into individual semiconductor chips. At this time, the die attach film is still attached to each semiconductor chip.

  In general product applications, packages such as TSOP (thin small outline package) and QFP (quad flat package) are used. In these packages, a lead frame is used, and a semiconductor chip is mounted on a tab in the lead frame. Here, there is a so-called large tab structure in which the outer size (dimension) of the tab is formed larger than the outer size (dimension, outer size of the back surface of the semiconductor chip) of the semiconductor chip. The lead frame is formed of a conductive material whose main component is, for example, Cu (copper) or Cu alloy.

  In the large tab structure, as shown in FIG. As a result, the amount of Cu used in the tab 101 also increases, so that the expansion and contraction of the tab 101 due to heat treatment increase, and there is a problem that warpage is likely to occur. Furthermore, since the adhesiveness between the tab 101 made of Cu and the resin (resin) 102 to be sealed is low, there is a problem that a crack (resin crack) occurs in the resin 102. This resin crack occurs, for example, as shown below. First, the die attach film 103 attached to the back surface of the semiconductor chip 100 absorbs moisture. Next, when solder reflow is performed, moisture in the die attach film 103 is evaporated, and the semiconductor chip 100 and the tab 101 are peeled off. Since the adhesiveness between the tab 101 and the resin 102 is low, the evaporated water further expands, a resin crack is generated in the resin 102, and the water is released to the outside. As described above, when the tab 101 having the large tab structure is used for mounting the semiconductor chip 100 to which the hygroscopic die attach film 103 is attached, since the adhesion between the tab 101 and the resin 102 is low, a resin crack is generated. There is a problem that is easy to do. Further, even on the back surface side opposite to the surface on which the die attach film 103 is formed in the tab 101, peeling occurs because the adhesiveness between the tab 101 and the resin 102 is low. The above-mentioned Patent Document 1 also discloses a large tab structure, but with such a configuration, it is difficult to suppress the problem of resin cracks.

  In order to solve the problem of the large tab, a so-called small tab structure, which is smaller than the outer size of the semiconductor chip, has recently been proposed. Since the amount of Cu to be used can be reduced with the small tab structure, the problem of lead frame warpage can be suppressed. Further, the back surface of the semiconductor chip can be exposed from the tab. Since the adhesive force between the semiconductor chip and the resin is higher than the adhesive force between the tab and the resin, the semiconductor chip can be held even if peeling occurs at the interface between the semiconductor chip and the tab.

  However, when a semiconductor chip with a die attach film attached is mounted on a tab having a small tab structure, the following inconvenience occurs. That is, a semiconductor chip with a die attach film attached is mounted on a tab having a small tab structure. However, as shown in FIG. 24, the semiconductor chip 100 is placed on the heater stage 105 when wire bonding is performed. Will be.

  Since the connection strength between the bonding pad (electrode pad) and the wire on the semiconductor chip 100 can be improved by applying heat, the heater stage 105 is provided with a tab so that the heat of the heater stage 105 is efficiently transmitted to the bonding pad. The mounting area of 106 is recessed, and the semiconductor chip 100 is in close contact with the heater stage 105. However, an adhesive die attach film 103 is attached to the back surface of the semiconductor chip 100, and this die attach film 103 is attached to the heater stage 105. Therefore, after wire bonding, the semiconductor chip is removed from the heater stage 105. 100 will not peel off. Further, the surface of the heater stage 105 is contaminated, and the heater stage 105 needs to be frequently cleaned.

  From the above, there is a problem in applying a semiconductor chip with a die attach film applied to a lead frame product having a large tab structure or a small tab structure.

  An object of the present invention is to provide a technique capable of effectively utilizing a semiconductor chip with a die attach film attached to a lead frame product.

  Specifically, in a semiconductor device in which a semiconductor chip with a die attach film attached is mounted on a tab and then sealed with a resin, a technique capable of suppressing warpage and resin cracking of the semiconductor device is provided. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention includes (a) a semiconductor chip having a die attach film attached to one surface thereof, (b) a tab on which the semiconductor chip is mounted via the die attach film, and (c) the tab. And (d) a plurality of wires connecting the plurality of leads and the semiconductor chip, and (e) a resin for sealing the semiconductor chip, and the tab has a frame shape It is characterized by doing.

  The method for manufacturing a semiconductor device according to the present invention includes (a) a step of preparing a lead frame having a frame-shaped tab, and (b) a step of mounting a semiconductor chip on which a die attach film is attached on the tab. And (c) a step of connecting a plurality of leads arranged around the tab and the semiconductor chip with a plurality of wires, and (d) a step of sealing the semiconductor chip. It is.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the shape of the tab on which the semiconductor chip to which the die attach film is affixed is formed into a frame shape, warpage of the semiconductor device and resin cracks can be suppressed. For this reason, the semiconductor chip to which the die attach film is attached can be effectively used for the lead frame product.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a diagram showing a part of the semiconductor device 1 according to the first embodiment. In FIG. 1, the package form of the semiconductor device 1 according to the first embodiment is TSOP (the height from the mounting surface of the package is 1.2 mm or less). In this TSOP, a tab is used for mounting a semiconductor chip. At the center of the semiconductor device 1, a frame tab 2 having a frame shape with the inside hollowed out is formed. That is, a frame tab 2 having a hollow portion 2a formed therein is formed in the central portion of the semiconductor device 1. The frame tab 2 is for mounting a semiconductor chip and has a rectangular frame shape. A plurality of leads 3 are formed around the frame tab 2.

  FIG. 2 is a diagram illustrating a state in which the semiconductor chip 4 is mounted on the frame tab 2. As shown in FIG. 2, the semiconductor chip 4 is mounted on the frame tab 2, a plurality of leads 3 arranged around the frame tab 2, and a bonding pad arranged on one side of the semiconductor chip 4. (Not shown) is electrically connected by a wire 5. The dimensions of the outer shape (region sealed with resin) of the TSOP in Embodiment 1 are about 20 mm on the long side and about 12 mm on the short side. The semiconductor chip 4 sealed with resin is, for example, a non-volatile memory (flash memory), and the planar shape intersecting with the thickness direction is, for example, a rectangular shape. About 12 mm and the short side are about 10.5 mm. As described above, the package used for the nonvolatile memory is characterized in that the ratio of the semiconductor chip 4 to the sealing area increases.

3 is a cross-sectional view showing a cross section taken along line AA of FIG. In FIG. 3, frame tab 2
A semiconductor chip 4 is mounted on the top. An adhesive die attach film 6 is attached to the entire back surface of the semiconductor chip 4, and the frame tab 2 and the semiconductor chip 4 are bonded by the die attach film 6. A plurality of bonding pads 7 are formed on the surface of the semiconductor chip 4, and the bonding pads 7 and the leads 3 are electrically connected by wires 5. Then, a part of the leads from the semiconductor chip 4 is sealed with resin to form a TSOP package.

  One feature of the first embodiment is that a frame-shaped frame tab 2 is used as a tab on which the semiconductor chip 4 is mounted. Conventionally, a tab having a solid tab material and a larger area than the semiconductor chip 4 has been used as a tab for mounting the semiconductor chip 4. However, when a large tab is used, since the tab material made of metal is formed in a solid shape, the tab tends to expand due to heat treatment during resin sealing. For this reason, when the temperature is returned to room temperature, the tab contracts, and the package is likely to warp. Further, in the first embodiment, it is assumed that the semiconductor chip 4 with the die attach film 6 attached is mounted on the tab. For example, a semiconductor wafer on which a non-volatile memory is formed is becoming thinner. Therefore, in order to improve the strength of the semiconductor wafer as described above and to facilitate the subsequent die bonding process, it is preferable to attach a die attach film to the back surface of the semiconductor wafer in advance.

  However, as a package form of a semiconductor device used for general purposes, there is a type using a lead frame such as TSOP and QFP. In these packages, a semiconductor chip is mounted on the tab. However, when a die attach film is used to connect the tab and the semiconductor chip, the above-described disadvantages occur. For example, since the die attach film is hygroscopic, the moisture stored in the die attach film is vaporized by reflow processing when the package is mounted on the mounting substrate, and bubbles are formed between the die attach film and the tab. appear. Although this bubble expands, since the adhesion between the tab and the sealing resin is low, the bubble further expands and finally a resin crack is generated. In particular, when a large tab is used, the contact area between the resin and the tab increases, and therefore resin cracks are likely to occur.

  For this reason, in the first embodiment, a frame tab 2 having a frame shape is used instead of using a large tab formed as a solid tab. According to the frame tab 2, since the inside (portion in contact with the vicinity of the center of the back surface of the semiconductor chip 4) is hollowed out, the use area of the tab material is smaller than that of the large tab. The thermal expansion of the tab becomes more prominent as the use area of the tab material is larger. Therefore, the thermal expansion and contraction can be reduced in the frame tab 2 having a smaller use area of the tab material than the large tab. Therefore, an effect of suppressing package warpage can be obtained. Furthermore, by using the frame tab 2, as shown in FIG. 3, the contact area between the tab material and the resin 8 can be reduced. In other words, the contact area between the semiconductor chip 4 to which the die attach film 6 is attached and the resin 8 can be increased. That is, since no tab material is formed inside the frame tab 2, the contact area between the frame tab 2 and the resin 8 is reduced, and the die attach film 6 and the resin 8 attached to the semiconductor chip 4 are directly connected. Come into contact. Since the adhesiveness between the die attach film 6 and the resin 8 is better than the adhesiveness between the tab material and the resin 8, an effect of suppressing resin cracks can be obtained. For example, the die attach film 6 is formed from an acrylic resin or a polyimide resin.

  In particular, in the nonvolatile memory, as described above, the area occupied by the semiconductor chip 4 with respect to the sealing area is large. Therefore, the area occupied by the tab on which the semiconductor chip 4 is mounted is also increased. For this reason, if a large tab formed on a solid is used, package warpage and resin cracking are likely to occur. From this, it can be seen that it is particularly preferable to use the frame tab 2 in the TSOP used for the nonvolatile memory.

  The object of the first embodiment is to effectively utilize the semiconductor chip 4 with the die attach film 6 attached to a lead frame product. Therefore, it is assumed that the semiconductor chip 4 with the die attach film 6 attached to the entire back surface is mounted on the tab. Here, Japanese Patent Laid-Open No. 6-268146 discloses a technique in which a semiconductor chip is mounted on a tab in which a hole is formed. However, in this technique, a die bonding material is formed only on the contact surface between the tab and the semiconductor chip, and a highly adhesive material is formed in other regions. For this reason, there is no technical idea of effectively using the die attach film 6 attached to the entire back surface of the semiconductor chip 4. That is, if this technique is used, a part of the die attach film 6 is attached to the entire back surface of the semiconductor chip 4 and a part of the die attach film 6 is removed, and a highly adhesive material is formed on the removed part. However, this process is complicated and does not effectively utilize the semiconductor chip 4 having the die attach film 6 attached to the entire back surface. Furthermore, a process for removing the die attach film 6 and a process for forming a highly adhesive material are required, which increases the number of processes. From this, it can be seen that the first embodiment is different from the technique described above.

  As in the first embodiment, when the frame tab 2 having a hollowed inside is used, the warpage of the package and the occurrence of resin cracks after the resin sealing body is formed can be suppressed, but the area of the tab material is reduced. In the process up to the sealing step, the adhesion between the frame tab 2 and the semiconductor chip 4 is considered to be a problem. In the case where the semiconductor chip 4 is fixed to the tab via the liquid conductive paste material, just because the area is large like a large tab, it does not necessarily improve the adhesive strength. That is, even if the contact area is increased, the adhesive force cannot be improved unless there is a uniform adhesive force between the large tab and the semiconductor chip 4. Further, since it is liquid, the fluidity is high, and if the conductive paste material is not cured, the semiconductor chip 4 moves and the bonding itself becomes unstable. On the other hand, when the semiconductor chip 4 is fixed to the tab via the die attach film 6, the semiconductor chip 4 has a so-called solid uniform adhesive layer having a higher viscosity than the liquid conductive paste material. Therefore, even if the frame tab 2 as in the first embodiment is used, the contact area is reduced, but the variation in the adhesive force is suppressed. Therefore, even if the frame tab 2 is used, the adhesive force does not become extremely weak. Furthermore, the adhesiveness between the frame tab 2 and the semiconductor chip 4 is not a problem. This is because the frame tab 2 and the semiconductor chip 4 are finally sealed with the resin 8 and thus fixed with the resin 8. That is, since the die attach film 6 has a solid adhesive layer with high viscosity, the semiconductor chip 4 is not displaced from the frame tab 2 until it is sealed with resin. For example, when wire bonding is performed, it is sufficient that the semiconductor chip 4 is firmly fixed to the frame tab 2. The frame tab 2 is sufficient to obtain such an adhesive strength. For this reason, it can be seen that there is no problem in adhesion between the frame tab 2 and the semiconductor chip 4 even if the frame tab 2 is used. Further, when using a conductive paste material made of liquid, heat treatment is required for semi-curing the semiconductor chip 4 so as not to cause displacement in the wire bonding process, but when using the die attach film 6. Since it can be held simply by mounting the semiconductor chip 4 on the frame tab 2, the number of steps can be reduced.

  As shown in FIG. 3, in the first embodiment, a semiconductor chip 4 is mounted on the frame tab 2, and a bonding pad 7 is formed on the semiconductor chip 4. The bonding pad 7 is formed at the outer edge of the semiconductor chip 4 and is formed immediately above the frame tab 2. The reason why the frame tab 2 is arranged immediately below the bonding pad 7 is as follows. That is, the bonding pad 7 and the lead 3 are bonded by the wire 5. At this time, the bonding pad 7 is heated. The bonding pad 7 is heated by heat from the heater stage. By arranging the bonding pad 7 on the frame tab 2, heat is conducted from the heater stage to the frame tab 2 that is in direct contact with the frame tab 2. This is because heat is efficiently transmitted from 2 to the bonding pad 7 immediately above. Therefore, even if the frame tab 2 is used, the wire 5 can be reliably connected to the bonding pad 7. As described above, according to the first embodiment, the use of the frame tab 2 positioned immediately below the bonding pad 7 suppresses the warping of the package and the resin crack without deteriorating the connection characteristics of the bonding pad 7. be able to. That is, by adopting the frame tab 2, the semiconductor chip 4 having the die attach film 6 attached to the entire back surface can be effectively used for a lead frame product.

  Next, although it is the tab material which comprises the frame tab 2, 50 alloys can be used, for example. 50 alloy is an alloy of iron (Fe) and nickel (Ni), and the ratio of iron and nickel is 50% respectively. The frame tab 2 may be made of a material mainly composed of 42 alloy or copper (Cu) in addition to 50 alloy.

FIG. 4 shows the evaluation results when 42 alloy, 50 alloy or copper is used for the tab material. 42 alloy is an alloy of iron and nickel, and is an alloy having a ratio of iron of 58% and a ratio of nickel of 42%. As can be seen from FIG. 4, the thermal expansion coefficient of 42 alloy is 4 × 10 −6 (ppm / ° C.), and the thermal expansion coefficient of 50 alloy is 10 × 10 −6 (ppm / ° C.). Moreover, the thermal expansion coefficient of copper is 17 × 10 −6 (ppm / ° C.). From this, the thermal expansion coefficient of 42 alloy is the lowest and is the closest to the thermal expansion coefficient of the resin. Therefore, it can be seen that when 42 alloy is used for the tab material, the warpage and reflow characteristics (generation of resin cracks) are not so problematic in both the large tab and the frame tab. Next, in the case of 50 alloy, since the thermal expansion coefficient is larger than that of 42 alloy, warpage becomes a problem when a large tab is used. On the other hand, since the coefficient of thermal expansion is the highest in the case of copper, both warpage and reflow characteristics become a problem when a large tab is used. From the above, it can be seen that it is desirable to use a frame tab in the case of 50 alloy, and it is essential to use a frame tab when copper is used. That is, when copper is used for a frame tab, it turns out that there exists an effect especially.

  Next, FIG. 5 is a diagram showing a modification of the first embodiment. The first embodiment is characterized in that a frame tab structure is employed in order to effectively utilize a semiconductor chip having a die attach film attached to the entire back surface for a lead frame product. However, when the frame tab 2 as shown in FIG. 3 is used, the thickness of the frame tab 2 is reduced in the cavity 2 (through hole, near the center of the back surface of the semiconductor chip 4) 2a of the frame tab 2 on which the semiconductor chip 4 is mounted. There will be a difference in level. If there is such a step, when the resin is allowed to flow into the entire surface of the semiconductor chip in the resin sealing step, bubbles are likely to remain in the cavity (the lower surface of the semiconductor chip 4) 2a of the frame tab 2 where the step is generated. If this bubble is left as it is, there is a possibility that a resin crack will occur due to reflow during packaging. Therefore, in the modification of the first embodiment, as shown in FIG. 5, the groove 9 is provided on the main surface (the side on which the semiconductor chip 4 is mounted) of the frame tab 2. By providing the groove 9, even if bubbles remain in the cavity 2 a of the frame tab 2 where the step is generated, it can be discharged from the groove 9 to the outside when the resin flows. That is, the grooves 9 formed in the frame tab 2 can prevent bubbles from remaining in the cavity 2a of the frame tab 2, and can prevent the occurrence of resin cracks in the package. The groove 9 can be formed by, for example, half-etching the frame of the frame tab 2 or can be formed by pressing.

  The frame tab 2 has, for example, a rectangular frame shape, and the groove 9 is formed on the long side of the frame, for example. This is because the resin flows in from the one long side in the frame of the frame tab 2 toward the other long side, so that bubbles are formed along this inflow direction. That is, if the groove 9 is not formed on the long side of the frame tab 2, bubbles are formed in the cavity 2 a of the frame tab 2. In this case, since the bubbles flow along the inflow direction, the bubbles are discharged to the outside by the groove 9 provided on the long side.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. First, as shown in FIG. 6, a semiconductor wafer 10 is prepared. For example, transistor elements and wirings are formed on the semiconductor wafer 10 by using a normal process technique. As an example, when a nonvolatile memory is formed on the semiconductor wafer 10, the thickness of the semiconductor wafer 10 is reduced to, for example, 220 μm or less.

  Next, as shown in FIG. 7, a semiconductor wafer 10 having an adhesive die attach film 13 attached in advance to the back surface is mounted (fixed) on a concentric jig 11 attached with a dicing tape 12.

  Subsequently, as shown in FIG. 8, the jig 11 on which the semiconductor wafer 10 is mounted is disposed on the suction stage 14. Then, the semiconductor wafer 10 is cut into individual semiconductor chips 10 a using the blade 15. At this time, cutting by the blade 15 is performed on the semiconductor wafer 10 and the die attach film 13 attached to the back surface thereof, and the dicing tape 12 formed under the die attach film 13 is not cut.

  Thereafter, as shown in FIG. 9, the semiconductor chip 10 a cut using the push-up piece 16 is lifted. Then, the lifted semiconductor chip 10 a is vacuum-sucked by the collet 17.

  Next, as shown in FIG. 10, a lead frame having leads 19 and frame tabs 20 is arranged on the heater stage 18. The frame tab 20 has a rectangular frame shape, and a plurality of grooves are formed on the long side. These grooves are formed by etching, for example. Then, the semiconductor chip 10 a is pressed against the frame tab 20 using the collet 17. Thereby, as shown in FIG. 11, the semiconductor chip 10 a is mounted on the frame tab 20. At this time, the semiconductor chip 10 a and the frame tab 20 are bonded by the die attach film 13. In the first embodiment, the frame tab 20 is formed on the heater stage 18, and the semiconductor chip 10 a is mounted on the frame tab 20. For this reason, the die attach film 13 is separated from the heater stage 18 by the thickness of the frame tab 20, and the die attach film 13 does not directly adhere to the heater stage 18.

  Here, after die bonding for mounting the semiconductor chip 10a on the frame tab 20, heat treatment for curing the die attach film 13 is not performed. This is because the die attach film 13 is not in a semi-dry state, so that the semiconductor chip 10a can be firmly fixed without being cured. Furthermore, if an extra heat treatment is applied, the semiconductor chip 10a is warped, and there is a risk that poor wire connection may occur in the subsequent wire bonding step. On the other hand, when the semiconductor chip 10a is bonded with a liquid paste, a heat treatment for curing the liquid paste is required to firmly fix the semiconductor chip 10a. In the first embodiment, since the semiconductor chip 10a and the frame tab 20 are adhered by the die attach film 13, a heat treatment process for curing can be omitted. Therefore, the manufacturing process can be simplified.

  Subsequently, as shown in FIG. 12, the bonding pad 21 formed on the semiconductor chip 10 a and the lead 19 are electrically connected by the wire 22 while the semiconductor chip 10 a is heated by the heater stage 18. The wire 22 is formed of, for example, a gold wire. An enlarged view of FIG. 12 is shown in FIG. As shown in FIG. 13, the bonding pad 21 is formed on the outer edge portion of the semiconductor chip 10 a and is formed immediately above the frame tab 20. In other words, the frame tab 20 is formed immediately below the bonding pad 21. Thus, by forming the frame tab 20 directly below the bonding pad 21, the heat generated in the heater stage 18 is transferred to the frame tab 20, and the heat transferred to the frame tab 20 is disposed immediately above. Communicate efficiently. Thereby, the wire 22 can be connected in a state where the bonding pad 21 is sufficiently heated. Therefore, the wire 22 can be reliably connected. Although the frame tab 20 is formed immediately below the bonding pad 21, the frame tab 20 is further formed from the position immediately below the bonding pad 21 to the inside by about 100 μm in consideration of misalignment and the like.

  Next, the semiconductor chip 10a is sealed with resin. To seal the semiconductor chip 10a with resin, as shown in FIG. 14, a gate is provided on the long side of the semiconductor chip 10a, and resin is introduced from the long side of the rectangular semiconductor chip 10a. At this time, a plurality of grooves 23 are formed on the long side of the frame tab 20 below the semiconductor chip 10a. 15 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 15, when the frame tab 20 is used, a step is generated in the cavity 20 a of the frame tab 20 on which the semiconductor chip 10 a is mounted by the thickness of the frame tab 20. If there is such a step, when the resin 25 is caused to flow into the entire surface of the semiconductor chip 10a in the resin sealing step, the bubbles 24 are formed at the corners of the cavity portion 20 (the lower surface of the semiconductor chip 10a) 20a where the step is generated. It tends to remain. However, in the first embodiment, since the groove 23 is provided on the main surface on the long side of the frame tab 20, the bubbles 24 are discharged from the groove 23 to the outside. Therefore, according to this Embodiment 1, peeling of the die attach film 13 and the resin 25 by the bubble 24 can be prevented, and a resin crack can be suppressed.

  And after forming the resin sealing body by sealing the semiconductor chip 10a with the resin 25 as shown in FIG. 16, the outer lead 26 exposed from the sealed resin 25 is cut and formed as shown in FIG. Thus, the semiconductor device according to the first embodiment is manufactured.

  Further, as shown in FIG. 18, the semiconductor device according to the first embodiment is mounted on the mounting substrate 27. Mounting on the mounting board 27 is performed as follows, for example. The solder 29 is printed on the terminals 28 formed on the mounting substrate 27 using a screen printing method or the like. Then, after mounting the semiconductor device according to the first embodiment on the solder 29, the semiconductor device is bonded to the mounting substrate 27 by reflowing.

  Here, lead-containing solder (Sn—Pb-based) is used for solder joints, and has many advantages of excellent workability because the joint has high reliability and low melting point. ing. For this reason, solder containing lead is often used for assembling electrical and electronic equipment. However, electrical and electronic products are increasingly discarded due to the end of their useful lives and the appearance of new products. And since this waste is nonflammable, it is currently left as it is or crushed and buried in the ground. For this reason, lead-containing solder used in discarded electrical and electronic equipment is eluted and mixed into groundwater or flows into rivers. Then, some form of lead is taken up by humans and its toxicity is regarded as a problem.

  In recent years, environmental problems have been highlighted all over the world, and there is a movement to regulate toxic lead contained in solder. For this reason, solder that does not contain lead is used instead of solder that contains lead. Examples of the solder containing no lead include tin (Sn), silver (Ag), copper (Cu) alloy, tin, copper Sn—Cu alloy, tin, silver Sn—Ag alloy, or Sn— There are Bi-based alloys. These lead-free solders are environmentally friendly because they do not contain lead, but have a higher melting point than lead-containing solders. Therefore, when the solder 29 is used for mounting the mounting substrate 27, there is a problem that the reflow temperature becomes high. As the reflow temperature increases, the stress applied to the resin 25 increases, so that resin cracks are also likely to occur. However, since the frame tab 20 is used in the first embodiment, resin cracks at the time of reflow can be suppressed even if a solder not containing lead is used as the solder 29. That is, when a normal large tab is used, resin cracks are likely to occur when the reflow temperature is increased by using solder that does not contain lead, but the frame tab 20 is used as in the first embodiment. In this case, even if the reflow temperature is increased, the amount of tab material (metal such as Cu) to be used can be reduced, and the contact area between the semiconductor chip 10a to which the die attach film 13 is attached and the resin 25 is increased. Therefore, the occurrence of resin cracks can be suppressed. For this reason, the structure using the frame tab 20 has a remarkable effect when the semiconductor device is mounted on the mounting board using the lead-free solder.

(Embodiment 2)
In the first embodiment, the example in which the bonding pad is provided on the outer edge portion of the semiconductor chip has been described. In the second embodiment, an example in which the bonding pad is provided in the center portion of the semiconductor chip will be described.

  FIG. 19 is a diagram showing a tab structure of the semiconductor device 30 according to the second embodiment. As shown in FIG. 19, the tab structure of the semiconductor device 30 according to the second embodiment is a frame tab 31, and a tab member 32 is formed at the center. A plurality of leads 33 are formed around the frame tab 31. FIG. 20 is a diagram illustrating a state in which the semiconductor chip 34 is mounted on the frame tab 31. As shown in FIG. 20, a bonding pad 35 is formed at the center of the semiconductor chip 34, and the bonding pad 35 is electrically connected to the lead 33 by a wire 36.

  If the frame tab shown in the first embodiment is used when the bonding pad 35 is in the center of the semiconductor chip 34 as in the second embodiment, the tab material is not provided directly under the bonding pad 35. It becomes. This structure has the following disadvantages. That is, heating is performed by the heater stage during wire bonding, but this heat is transmitted to the frame tab that is in direct contact with the heater stage, and is transmitted from the frame tab to the semiconductor chip. However, if a tab material is not provided directly below the bonding pad 35 formed in the center of the semiconductor chip 34, heat cannot be efficiently transmitted to the bonding pad 35 via the tab material. If wire bonding is not performed in a state where the bonding pad 35 is sufficiently heated, wire connection failure is likely to occur. Therefore, in the second embodiment, the tab structure is the frame tab 31, and the tab material 32 is further provided at the center. As a result, the tab material 32 is provided immediately below the bonding pad 35 formed at the center of the semiconductor chip 34, so that heat generated in the heater stage can be efficiently transmitted to the bonding pad 35 during wire bonding. The wire 36 can be connected while the bonding pad 35 is sufficiently heated.

  Since the tab material 32 only needs to be formed at least directly below the bonding pad 35, the tab material 32 may be provided without forming the frame tab 31. Also in this case, since the area of the tab can be reduced, warpage of the semiconductor device and resin cracks can be suppressed. Further, as described in the first embodiment, the frame tab 31 may be provided with a plurality of grooves.

  According to the second embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Although the package form of the first embodiment is TSOP, the third embodiment will be described in the case where the package form is QFP.

  FIG. 21 shows a tab structure of the semiconductor device 40 according to the third embodiment. As shown in FIG. 21, a frame tab 41 is formed at the center of the semiconductor device 40 by tab suspension leads provided on a diagonal line. Bubble removal grooves 42 are provided on four sides of the frame tab 41. A plurality of leads 43 are provided around the frame tab 41. FIG. 22 is a diagram illustrating a state in which the semiconductor chip 44 is mounted on the frame tab 41. As shown in FIG. 22, a semiconductor chip 44 is mounted on the frame tab 41, and the semiconductor chip 44 and the lead 43 are electrically connected by a wire 45.

  The difference between the third embodiment and the first embodiment is that a groove is provided only on the long side of the frame tab in the first embodiment, whereas the frame tab 41 is different in the third embodiment. The groove 42 is formed on all four sides. In the first embodiment, the resin is caused to flow from the long side of the frame tab. However, in the third embodiment, the resin is introduced from the corner of the frame tab 41, that is, from the diagonal line of the frame tab 41. This is to make it flow. That is, in the first embodiment, since the resin is caused to flow from the long side of the frame tab, it is easy for bubbles to remain below the long side of the frame tab. For this reason, providing a groove on the long side of the frame tab was sufficient to remove bubbles. On the other hand, in this Embodiment 3, since resin flows in from the diagonal of the frame tab 41, air bubbles tend to remain below the four sides of the frame tab. For this reason, in the third embodiment, the grooves 42 are provided on all four sides of the frame tab 41. Thereby, it is possible to sufficiently remove bubbles that are likely to be generated when the resin flows. The groove 42 can be formed by etching or the like as in the first embodiment. According to the third embodiment, the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, TSOP and QFP have been described. However, the present invention is not limited to this, and can be widely applied to lead frame products having tabs.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the figure which showed a part of semiconductor device in Embodiment 1 of this invention. It is a figure which shows a mode that the semiconductor chip was mounted on the frame tab. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. It is the figure which showed the evaluation result at the time of using 42 alloy, 50 alloy, or copper for a tab material. FIG. 6 is a diagram showing a modification of the first embodiment. FIG. 10 is a side view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a side view illustrating a manufacturing step of the semiconductor device following that of FIG. 11; It is an enlarged view of FIG. FIG. 13 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 12; It is sectional drawing cut | disconnected by the AA line of FIG. FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 17 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a side view showing a manufacturing step of the semiconductor device following that of FIG. 17; 6 is a diagram showing a tab structure of a semiconductor device in a second embodiment. It is a figure which shows a mode that the semiconductor chip was mounted on the frame tab. FIG. 10 illustrates a tab structure of a semiconductor device in a third embodiment. It is a figure which shows a mode that the semiconductor chip was mounted on the frame tab. It is sectional drawing which shows the cross section which mounted the semiconductor chip on the large tab and was resin-sealed. It is sectional drawing which shows the cross section which mounted the semiconductor chip on the small tab and wire-bonded on the heater stage.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Frame tab 2a Hollow part 3 Lead 4 Semiconductor chip 5 Wire 6 Die attach film 7 Bonding pad 8 Resin 9 Groove 10 Semiconductor wafer 10a Semiconductor chip 11 Jig 12 Dicing tape 13 Die attach film 14 Adsorption stage 15 Blade 16 Push up Frame 17 Collet 18 Heater stage 19 Lead 20 Frame tab 20a Cavity 21 Bonding pad 22 Wire 23 Groove 24 Bubble 25 Resin 26 Outer lead 27 Mounting substrate 28 Terminal 29 Solder 30 Semiconductor device 31 Frame tab 32 Tab material 33 Lead 34 Semiconductor chip 35 Bonding pad 36 Wire 40 Semiconductor device 41 Frame tab 42 Groove 43 Lead 44 Semiconductor chip 45 Wire 100 Semiconductor chip 101 Tab 102 Resin 10 Die attach film 105 heater stage 106 tab

Claims (15)

  1. (A) a semiconductor chip having a die attach film attached to one surface;
    (B) a tab for mounting the semiconductor chip via the die attach film;
    (C) a plurality of leads disposed around the tab;
    (D) a plurality of wires connecting the plurality of leads and the semiconductor chip;
    (E) a resin for sealing the semiconductor chip;
    2. The semiconductor device according to claim 1, wherein the tab has a frame shape.
  2.   The semiconductor device according to claim 1, wherein a groove is formed in a main surface of the tab.
  3.   The semiconductor device according to claim 2, wherein the groove is formed by etching.
  4.   The semiconductor device according to claim 2, wherein the tab has a rectangular frame shape, and the groove is formed on a long side of the tab.
  5.   3. The semiconductor device according to claim 2, wherein the groove is formed on four sides of the tab having a frame shape.
  6.   2. The semiconductor device according to claim 1, wherein the tab is formed at least immediately below a bonding pad formed on the semiconductor chip.
  7.   2. The semiconductor device according to claim 1, wherein the plurality of leads and the tab are made of a material mainly composed of copper.
  8. (A) preparing a lead frame having a frame-shaped tab;
    (B) mounting a semiconductor chip with a die attach film on the tab;
    (C) connecting a plurality of leads arranged around the tab and the semiconductor chip with a plurality of wires;
    (D) A method for manufacturing a semiconductor device, comprising: sealing the semiconductor chip.
  9.   9. The method of manufacturing a semiconductor device according to claim 8, wherein a groove is formed on a main surface of the tab.
  10.   The method of manufacturing a semiconductor device according to claim 9, wherein the groove is formed by etching.
  11.   The method for manufacturing a semiconductor device according to claim 9, wherein the tab has a rectangular frame shape, and the groove is formed on a long side of the tab.
  12.   12. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (d), resin is introduced from a long side of the tab.
  13.   20. The method of manufacturing a semiconductor device according to claim 19, wherein the groove is formed on four sides of the tab having a frame shape.
  14.   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (d), a resin is introduced from a corner portion of the tab.
  15. further,
    9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device formed by sealing the semiconductor chip is mounted on a mounting substrate via solder not containing lead.
JP2005236591A 2005-08-17 2005-08-17 Manufacturing method of semiconductor device Expired - Fee Related JP4668729B2 (en)

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215844A (en) * 1985-07-15 1987-01-24 Hitachi Ltd Semiconductor lead frame
JPS63248155A (en) * 1987-04-03 1988-10-14 Mitsubishi Electric Corp Semiconductor device
JPH0697354A (en) * 1992-07-27 1994-04-08 Motorola Inc Semiconductor device provided with flag having opening part
JPH06236899A (en) * 1992-09-29 1994-08-23 Toshiba Corp Resin sealed type semiconductor device
JPH06268146A (en) * 1993-03-15 1994-09-22 Toshiba Corp Semiconductor device
JPH10303352A (en) * 1997-04-22 1998-11-13 Anam Ind Co Ltd Semiconductor device and manufacture of semiconductor device
JP2000104040A (en) * 1998-09-30 2000-04-11 Hitachi Chem Co Ltd Adhesive for die bonding and preparation of semiconductor device
JP2000252403A (en) * 1999-02-26 2000-09-14 Mitsui High Tec Inc Semiconductor device
JP2002261187A (en) * 2000-12-28 2002-09-13 Hitachi Hokkai Semiconductor Ltd Semiconductor device
JP2003332522A (en) * 2002-05-17 2003-11-21 Mitsubishi Electric Corp Semiconductor device
JP2005203401A (en) * 2004-01-13 2005-07-28 Sumitomo Bakelite Co Ltd Semiconductor device and manufacturing method thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215844A (en) * 1985-07-15 1987-01-24 Hitachi Ltd Semiconductor lead frame
JPS63248155A (en) * 1987-04-03 1988-10-14 Mitsubishi Electric Corp Semiconductor device
JPH0697354A (en) * 1992-07-27 1994-04-08 Motorola Inc Semiconductor device provided with flag having opening part
JPH06236899A (en) * 1992-09-29 1994-08-23 Toshiba Corp Resin sealed type semiconductor device
JPH06268146A (en) * 1993-03-15 1994-09-22 Toshiba Corp Semiconductor device
JPH10303352A (en) * 1997-04-22 1998-11-13 Anam Ind Co Ltd Semiconductor device and manufacture of semiconductor device
JP2000104040A (en) * 1998-09-30 2000-04-11 Hitachi Chem Co Ltd Adhesive for die bonding and preparation of semiconductor device
JP2000252403A (en) * 1999-02-26 2000-09-14 Mitsui High Tec Inc Semiconductor device
JP2002261187A (en) * 2000-12-28 2002-09-13 Hitachi Hokkai Semiconductor Ltd Semiconductor device
JP2003332522A (en) * 2002-05-17 2003-11-21 Mitsubishi Electric Corp Semiconductor device
JP2005203401A (en) * 2004-01-13 2005-07-28 Sumitomo Bakelite Co Ltd Semiconductor device and manufacturing method thereof

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