JPH01257361A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH01257361A
JPH01257361A JP8640988A JP8640988A JPH01257361A JP H01257361 A JPH01257361 A JP H01257361A JP 8640988 A JP8640988 A JP 8640988A JP 8640988 A JP8640988 A JP 8640988A JP H01257361 A JPH01257361 A JP H01257361A
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
assembly
lead frame
setup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8640988A
Other languages
Japanese (ja)
Inventor
Nobuyuki Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8640988A priority Critical patent/JPH01257361A/en
Publication of JPH01257361A publication Critical patent/JPH01257361A/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE: To enhance the mounting density of a semiconductor device by a method wherein opposite faces of two lead frames where semiconductor elements are mounted are bonded to each other and this assembly is resin-sealed.
CONSTITUTION: A semiconductor element 4 is mounted on a main face of a lead frame 1; the semiconductor element 4 is connected electrically to the lead frame 1 by using a bonding wire 3; by this setup, a first assembly is formed. A semiconductor element 4' is mounted on a main face of a lead frame 1'; it is connected electrically to the lead frame 1' by using a bonding wire 3'; by this setup, a second assembly is formed. An insulating layer 5 is situated between opposite faces of these two lead frames 1 and 2; both opposite faces are bonded to each other; after that, this assembly is sealed by using a resin 2. By this setup, a semiconductor device having two functions can be formed in one package; the mounting density of the semiconductor device can be enhanced sharply.
COPYRIGHT: (C)1989,JPO&Japio
JP8640988A 1988-04-07 1988-04-07 Resin-sealed semiconductor device Granted JPH01257361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8640988A JPH01257361A (en) 1988-04-07 1988-04-07 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8640988A JPH01257361A (en) 1988-04-07 1988-04-07 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH01257361A true JPH01257361A (en) 1989-10-13

Family

ID=13886068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8640988A Granted JPH01257361A (en) 1988-04-07 1988-04-07 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH01257361A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
US5543658A (en) * 1993-06-14 1996-08-06 Kabushiki Kaisha Toshiba Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device
US6157050A (en) * 1997-09-25 2000-12-05 Sumitomo Electric Industries, Ltd. Optical module and lead frame for optical module
JP2021034661A (en) * 2019-08-28 2021-03-01 Ｎｅｃプラットフォームズ株式会社 Semiconductor device, electronic device, and manufacturing method of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
US5543658A (en) * 1993-06-14 1996-08-06 Kabushiki Kaisha Toshiba Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device
US5614441A (en) * 1993-06-14 1997-03-25 Kabushiki Kaisha Toshiba Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package
US6157050A (en) * 1997-09-25 2000-12-05 Sumitomo Electric Industries, Ltd. Optical module and lead frame for optical module
JP2021034661A (en) * 2019-08-28 2021-03-01 Ｎｅｃプラットフォームズ株式会社 Semiconductor device, electronic device, and manufacturing method of semiconductor device

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