KR20010044948A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR20010044948A KR20010044948A KR1019990048009A KR19990048009A KR20010044948A KR 20010044948 A KR20010044948 A KR 20010044948A KR 1019990048009 A KR1019990048009 A KR 1019990048009A KR 19990048009 A KR19990048009 A KR 19990048009A KR 20010044948 A KR20010044948 A KR 20010044948A
- Authority
- KR
- South Korea
- Prior art keywords
- mounting plate
- chip mounting
- chip
- resin
- semiconductor package
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 좀 더 상세하게는 칩탑재판 노출형 패키지(Exposed Paddle Package)의 칩탑재판 상면에 다수의 홈을 형성하고, 그 저면 테두리 하단에 단차부를 형성하여, 패키지내로 수분의 침투를 방지하고 칩탑재판과 수지와의 결합력을 증대시킬 수 있도록 한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to form a plurality of grooves in an upper surface of a chip mounting plate of an exposed paddle package, and to form a step portion at a lower edge of a bottom of the chip mounting plate. The present invention relates to a semiconductor package capable of preventing the penetration of moisture and increasing the bonding force between the chip mounting plate and the resin.
일반적으로 반도체 패키지는 칩탑재판과 상기 칩탑재판 상면에 접착수단에 의해 실장되는 칩과 상기 칩과 리드프레임의 리드를 연결하는 와이어로 이루어지며, 상기 칩과 와이어와 리드 및 탑재판을 외부로부터 보호하기 위하여 수지로 몰딩된다.In general, the semiconductor package is composed of a chip mounted on the chip mounting plate and the upper surface of the chip mounting plate and a wire connecting the chip and the lead of the lead frame with the chip. Molded with resin to protect.
또한, 최근에는 반도체 패키지에 사용되는 칩이 고집적화 되면서 칩에서 많은 열을 방출하게 되어서 칩탑재판 하면이 외부로 노출된 칩탑재판 노출형 패키지(Exposed Paddle Package)가 개발되었다.In addition, recently, as the chips used in semiconductor packages have been highly integrated, a lot of heat is emitted from the chips, so that an exposed paddle package having an exposed bottom surface of the chip mounting plate is exposed.
첨부한 도 1은 종래의 칩탑재판의 일면이 외부로 노출된 반도체 패키지를 나타내는 단면도로써, 칩(22)이 접착수단(30)에 의해 칩탑재판(10) 상부에 실장되고, 칩(22)의 본딩패드와 각 리드(28)간에는 와이어(26)에 의해 본딩되어 상기 칩(22)과 각 리드(28) 사이에서 전기적 신호를 전달할 수 있게 되어 있으며, 또한 칩탑재판(10) 상면에 실장되어지는 칩(22)과 와이어(26)와 리드(28) 및 칩탑재판(10) 상면부는 수지(24)에 의해 몰딩되어 반도체 패키지가 완성된다.1 is a cross-sectional view illustrating a semiconductor package in which one surface of a conventional chip mounting plate is exposed to the outside, and the chip 22 is mounted on the chip mounting plate 10 by the bonding means 30, and the chip 22. Is bonded by a wire 26 between the bonding pads and the leads 28 to transfer electrical signals between the chips 22 and the leads 28, and also on the upper surface of the chip mounting plate 10. The upper surface portions of the chip 22, the wire 26, the lead 28, and the chip mounting plate 10 to be mounted are molded by the resin 24 to complete the semiconductor package.
상기와 같은 구조로 이루어진 칩탑재판 노출형 패키지의 가장 큰 특징은 칩탑재판(10)의 저면이 몰딩수지(24)의 외곽라인과 평행을 이루며 외부에 노출되어 칩(22)에서 발생되는 열을 외부로 보다 효율적으로 방출할 수 있는 점에 있다.The biggest feature of the chip mounting plate exposed package having the structure as described above is that the bottom surface of the chip mounting plate 10 is parallel to the outer line of the molding resin 24 and exposed to the outside to generate heat from the chip 22. It is in that it can discharge | emit more efficiently to the outside.
그러나, 상기와 같이 이루어진 반도체 패키지는 칩탑재판(10)의 저면이 외부로 노출되어 있는 바, 수분이 칩탑재판(10)과 수지(24)의 경계라인 틈새로 침투하여 칩탑재판(10)과 수지(24) 사이가 박리되는 디라미네이션(delamination) 현상이 발생하고, 칩탑재판 (10)과 칩(22) 사이의 접착수단(30)이 칩(22)에서 발생하는 열에 의해 녹아서 칩(22) 상부까지 타고 올라가서 칩탑재판(10)과 수지(24)와의 결합력이 약화되는 문제점이 있었다.However, in the semiconductor package made as described above, the bottom surface of the chip mounting plate 10 is exposed to the outside, and moisture penetrates into the gap between the chip mounting plate 10 and the boundary line between the resin 24 and the chip mounting plate 10. ) And delamination between the resin 24 occurs, and the adhesive means 30 between the chip mounting plate 10 and the chip 22 is melted by the heat generated in the chip 22 and the chip (22) There was a problem in that the bonding force between the chip mounting plate 10 and the resin 24 was weakened up to the upper portion.
본 발명은 상기와 같은 문제점을 감안하여 안출한 것으로, 칩탑재판 노출형 패키지(Exposed Paddle Package)의 칩탑재판 상면의 칩탑재 영역 밖으로 다수의 홈을 형성하고, 그 저면 테두리 하단에 단차부를 형성하여, 패키지내로 수분의 침투를 방지하고 접착수단이 외부로 빠져나가는 것을 차단하여 칩탑재판과 수지와의 결합력을 증대할 수 있도록 한 반도체 패키지를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and forms a plurality of grooves outside the chip mounting area of the upper surface of the chip mounting plate of an exposed paddle package, and forms a stepped portion at the bottom of the bottom edge thereof. Accordingly, an object of the present invention is to provide a semiconductor package which prevents the penetration of moisture into the package and prevents the adhesion means from escaping to the outside to increase the bonding force between the chip mounting plate and the resin.
도 1은 종래의 칩탑재판의 일면이 외부로 노출된 반도체 패키지를 나타내는 단면도,1 is a cross-sectional view showing a semiconductor package in which one surface of a conventional chip mounting plate is exposed to the outside;
도 2은 본 발명에 따른 칩탑재판의 일면이 외부로 노출된 반도체 패키지를 나타내는 단면도,2 is a cross-sectional view showing a semiconductor package in which one surface of the chip mounting plate according to the present invention is exposed to the outside;
도 3는 본 발명에 따른 반도체 패키지의 칩탑재판을 나타내는 요부 평면도.Figure 3 is a plan view of the main portion showing a chip mounting plate of the semiconductor package according to the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10 : 칩탑재판 12 : 단차부10: chip mounting plate 12: stepped portion
14 : 홈 22 : 칩14: groove 22: chip
24 : 수지 26 : 와이어24: Resin 26: Wire
28 : 리드 30 : 접착수단28: lead 30: bonding means
이하, 첨부도면을 참조하여 본 발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 반도체 패키지는 반도체 칩(22)이 부착된 칩탑재판(10)과, 상기 반도체 칩(22)의 본딩패드와 리드프레임의 리드(28)간에 연결된 와이어(26)와, 칩탑재판(10)의 상면을 몰딩하고 있는 수지(24)로 이루어지되, 상기 칩탑재판(10)의 저면이 외부로 노출되게 제조된 반도체 패키지에 있어서, 상기 칩탑재판(10)의 칩탑재영역 밖의 영역에 칩탑재판(10)과 수지(28)의 결합력을 증대시킬 수 있도록 다수의 홈(14)을 형성하면서 된 것을 특징으로 한다.The semiconductor package according to the present invention includes a chip mounting plate 10 having a semiconductor chip 22 attached thereto, a wire 26 connected between a bonding pad of the semiconductor chip 22 and a lead 28 of a lead frame, and a chip mounting member. In the semiconductor package made of a resin 24 molding the upper surface of the plate 10, the bottom surface of the chip mounting plate 10 is exposed to the outside, the chip mounting area of the chip mounting plate 10 It is characterized in that a plurality of grooves 14 are formed to increase the bonding force between the chip mounting plate 10 and the resin 28 in the outer region.
특히, 상기 칩탑재판(10)의 저면 테두리는 칩탑재판(10)과 수지(24) 사이로 수분이 침투하는 것을 방지하기 위하여 수분의 침투경로를 길게 할 수 있는 단차부(12)가 형성된 것을 특징으로 한다.In particular, the bottom edge of the chip mounting plate 10 is formed with a stepped portion 12 which can lengthen the penetration path of water in order to prevent the penetration of moisture between the chip mounting plate 10 and the resin 24. It features.
본 발명을 좀 더 상세하게 설명하면 다음과 같다.The present invention will be described in more detail as follows.
도 2은 본 발명에 따른 칩탑재판의 일면이 외부로 노출된 반도체 패키지를 나타내는 단면도이고, 도 3는 본 발명에 따른 반도체 패키지의 칩탑재판을 나타내는 요부 평면도로써, 칩(22)이 접착수단(30)에 의해 칩탑재판(10) 상부에 실장되어 있고, 상기 칩(22)은 각 리드(28)와 와이어(26)에 의해 본딩되어 칩(22)과 각 리드(28) 사이에서 전기적 신호를 전달할 수 있다.2 is a cross-sectional view illustrating a semiconductor package in which one surface of the chip mounting plate according to the present invention is exposed to the outside, and FIG. 3 is a plan view of a main portion of the chip mounting plate of the semiconductor package according to the present invention, in which the chip 22 is a bonding means. 30 mounted on the chip mounting plate 10, and the chips 22 are bonded by the leads 28 and the wires 26 to electrically connect between the chips 22 and the leads 28, respectively. Can carry a signal.
또한, 상기 칩탑재판(10) 상면에 실장되는 칩(22)과 와이어(26)와 리드(28) 및 칩탑재판(10) 상면은 수지(24)에 의해 몰딩되는 동시에, 칩탑재판(10)의 저면이 외부에 노출되어 칩(22)에서 발생되는 열을 외부로 보다 효율적으로 방출할 수 있는 것이다.In addition, the chip 22, the wire 26, the lead 28, and the chip mounting plate 10, which are mounted on the chip mounting plate 10, may be molded by the resin 24, and at the same time, the chip mounting plate ( The bottom surface of 10) is exposed to the outside so that the heat generated from the chip 22 can be more efficiently discharged to the outside.
여기에서, 상기 칩탑재판(10)의 상부에는 칩(22)에서 발생하는 열에 의해 칩탑재판(10)과 칩(22) 사이의 접착수단(30)이 녹아서 칩(22) 상부로 올라가는 것을 방지하기 위하여 상기 칩(22)이 실장되는 테두리를 따라 2열 내지 3열로 다수개의 홈(14)이 등간격으로 형성된다.Here, the adhesive means 30 between the chip mounting plate 10 and the chip 22 is melted by the heat generated from the chip 22 on the upper part of the chip mounting plate 10 to rise to the upper part of the chip 22. In order to prevent the plurality of grooves 14 are formed at equal intervals in two to three rows along the edge where the chip 22 is mounted.
따라서, 상기 다수의 홈(14)은 칩(22)에서 발생하는 열에 의해 접착수단(30)이 녹아 칩(22) 상부로 올라가는 것을 방지하는 저항 역할을 하며, 이와 동시에 수지(24)와 칩탑재판(10)의 접촉면적을 증가시켜 결합력을 강화하는 역할을 한다.Therefore, the plurality of grooves 14 serve as a resistance to prevent the adhesive means 30 from melting and rising to the upper portion of the chip 22 by the heat generated from the chip 22, and at the same time, the resin 24 and the chip mounting material. Increasing the contact area of the plate 10 serves to strengthen the bonding force.
또한, 상기 칩탑재판 테두리 저면에는 코이닝(coining) 또는 하프에칭(half etching)에 의해 단차부(12)를 형성하여 수분이 침투되는 경로를 길게 함으로써, 수분의 침투를 방지하여 수지(24)와 칩탑재판(10) 사이가 박리되는 디라미네이션 현상을 방지할 수 있는 것이다.In addition, the stepped portion 12 is formed on the bottom of the edge of the chip mounting plate by coining or half etching to lengthen a path through which moisture penetrates, thereby preventing moisture from penetrating into the resin 24. And it can prevent the delamination phenomenon is peeled off between the chip mounting plate 10.
이상 서술한 바와 같이, 본 발명에 따른 반도체 패키지의 칩탑재판에 의하면 칩탑재판 상면에 다수의 홈을 형성하고 그 저면 테두리에 단차부를 형성하여, 칩에서 발생하는 열에 의해 접착수단이 외부로 빠져나가는 것을 방지하여 칩탑재판과 수지와의 결합력을 증대할 수 있고 수분의 침투를 방지할 수 있는 효과가 있다.As described above, according to the chip mounting plate of the semiconductor package according to the present invention, a plurality of grooves are formed on the upper surface of the chip mounting plate, and a step portion is formed on the bottom edge thereof, so that the adhesive means falls out due to heat generated from the chip. It is possible to prevent the outgoing to increase the bonding strength of the chip mounting plate and the resin and has the effect of preventing the penetration of moisture.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990048009A KR20010044948A (en) | 1999-11-01 | 1999-11-01 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990048009A KR20010044948A (en) | 1999-11-01 | 1999-11-01 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010044948A true KR20010044948A (en) | 2001-06-05 |
Family
ID=19618060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990048009A KR20010044948A (en) | 1999-11-01 | 1999-11-01 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010044948A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708039B1 (en) * | 2001-07-28 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | Substrate for semiconductor package |
| KR100859700B1 (en) * | 2001-11-15 | 2008-09-23 | 페어차일드코리아반도체 주식회사 | Pad exposed type semiconductor package for good heat radiation |
| WO2022188071A1 (en) * | 2021-03-10 | 2022-09-15 | Innoscience (suzhou) Semiconductor Co., Ltd. | Iii-nitride-based semiconductor packaged structure and method for manufacturing thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188964A (en) * | 1987-01-31 | 1988-08-04 | Dainippon Printing Co Ltd | Integrated circuit package |
| JPS63248155A (en) * | 1987-04-03 | 1988-10-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPH05145002A (en) * | 1991-11-25 | 1993-06-11 | Toshiba Corp | Semiconductor device |
| KR19990032516U (en) * | 1997-12-31 | 1999-07-26 | 유무성 | Semiconductor leadframe |
-
1999
- 1999-11-01 KR KR1019990048009A patent/KR20010044948A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188964A (en) * | 1987-01-31 | 1988-08-04 | Dainippon Printing Co Ltd | Integrated circuit package |
| JPS63248155A (en) * | 1987-04-03 | 1988-10-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPH05145002A (en) * | 1991-11-25 | 1993-06-11 | Toshiba Corp | Semiconductor device |
| KR19990032516U (en) * | 1997-12-31 | 1999-07-26 | 유무성 | Semiconductor leadframe |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708039B1 (en) * | 2001-07-28 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | Substrate for semiconductor package |
| KR100859700B1 (en) * | 2001-11-15 | 2008-09-23 | 페어차일드코리아반도체 주식회사 | Pad exposed type semiconductor package for good heat radiation |
| WO2022188071A1 (en) * | 2021-03-10 | 2022-09-15 | Innoscience (suzhou) Semiconductor Co., Ltd. | Iii-nitride-based semiconductor packaged structure and method for manufacturing thereof |
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