KR0185571B1 - Leadframe and semiconductor chip package - Google Patents
Leadframe and semiconductor chip package Download PDFInfo
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- KR0185571B1 KR0185571B1 KR1019960028598A KR19960028598A KR0185571B1 KR 0185571 B1 KR0185571 B1 KR 0185571B1 KR 1019960028598 A KR1019960028598 A KR 1019960028598A KR 19960028598 A KR19960028598 A KR 19960028598A KR 0185571 B1 KR0185571 B1 KR 0185571B1
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- leads
- package
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 칩 온 리드용 리드프레임 및 그를 이용한 반도체 칩 패키지에 관한 것으로, 내부리드의 말단부의 하부면은 평평하고, 상부면은 하향 단차지게 형성함으로써, 종래의 평면적인 접착에서 입체적인 접착이 가능하기 때문에 칩과 내부리드들간의 결합력이 증가되며 동시에 칩과 내부리드들 사이의 보이드 발생이 억제될 수 있으며, 칩이 내부리드의 단차부에 접착되기 때문에 종래 보다 칩의 본딩패드들과 내부리드들의 와이어 본딩의 높이가 낮아져서 와이어 본딩의 신뢰성을 확보할 수 있으며, 칩이 내부리드의 단차부의 높이 만큼이 하향 접착되기 때문에 종래의 패키지보다 박형화를 이룰수 있는 장점이 있다.The present invention relates to a lead frame for a chip-on-lead and a semiconductor chip package using the same, wherein the lower surface of the distal end portion of the inner lead is flat and the upper surface is stepped downward, thereby allowing three-dimensional bonding in conventional planar bonding. Therefore, the bonding force between the chip and the inner leads is increased, and at the same time, the generation of voids between the chip and the inner leads can be suppressed, and since the chip is attached to the stepped portion of the inner lead, the bonding pads of the chip and the wires of the inner leads are more conventional. As the height of the bonding is lowered, the reliability of wire bonding can be ensured, and since the chip is adhered downward by the height of the stepped portion of the inner lead, there is an advantage that the thickness of the conventional package can be achieved.
Description
본 발명은 리드프레임 및 그를 이용한 반도체 칩 패키지에 관한 것으로, 더욱 상세하게는 내부리드 말단에 칩접착 단차부가 형성된 리드프레임 및 그를 이용한 반도체 칩 패키지에 관한 것이다.The present invention relates to a lead frame and a semiconductor chip package using the same, and more particularly, to a lead frame having a chip adhesion stepped portion at an inner lead end and a semiconductor chip package using the same.
통상의 반도체 칩 패키지는 그 패키지 크기에 비하여 칩 크기에 대한 제약이 많았다.Conventional semiconductor chip packages have more restrictions on chip size than their package sizes.
이는 패키지 구조상 다이패드를 기본적으로 배치하여야 하고, 또한 다이패드와 리드들 간의 공간은 최소한 리드프레임의 두께만큼은 확보되어야 하므로 실제 실장 가능한 칩의 크기는 패키지의 폭에 약 70%가 일반적인 한계이었다.In the package structure, the die pad should be basically disposed, and since the space between the die pad and the leads should be secured at least as much as the thickness of the lead frame, the actual mountable chip size was about 70% of the package width.
상기한 단점을 보완하기 위해서, 제시된 방안이 칩의 탑재부를 다이패드 대신에 내부리드를 칩 탑재부로 사용하는 것이다.In order to make up for the above disadvantages, the proposed solution is to use the inner lead as the chip mount instead of the die pad.
내부리드를 칩 탑재부로 사용하여 제조된 반도체 칩 패키지는 리드 온 칩(lead on chip) 패키지와 칩 온 리드(chip on lead) 패키지가 있다.The semiconductor chip package manufactured using the internal lead as a chip mounting part includes a lead on chip package and a chip on lead package.
도 1은 종래 기술에 의한 칩 온 리드 패키지의 단면도이다.1 is a cross-sectional view of a chip on lead package according to the prior art.
도 1을 참조하면, 종래 기술에 의한 칩 온 리드 패키지(100)는 상부면에 복수개의 본딩패드(12)를 갖는 칩(10)과, 그 칩(10)의 하부면이 접착제(60)에 의해 내부리드들(30) 상부면에 접착되어 있으며, 상기 내부리드들(30)과 일체형으로 형성된 외부리드들(20)을 갖는 리드프레임과, 상기 본딩패드들(12)과 각기 대응된 상기 내부리드들(30)이 와이어(40)에 의해 전기적으로 연결되어 있으며, 상기 칩(10)과 내부리드들(30) 및 와이어(40)를 보호하기 위해 성형수지(50)에 의해 내재·봉지된 구조(100)를 갖는다.Referring to FIG. 1, in the chip on lead package 100 according to the related art, a chip 10 having a plurality of bonding pads 12 on an upper surface thereof, and a lower surface of the chip 10 may be attached to an adhesive 60. A lead frame having an outer lead 20 bonded to an upper surface of the inner leads 30 and integrally formed with the inner leads 30, and corresponding to the bonding pads 12, respectively. Leads 30 are electrically connected by wire 40, and are embedded and encapsulated by molding resin 50 to protect the chip 10, the inner leads 30, and the wire 40. Has a structure 100.
여기서, 상기 칩(10)과 내부리드들(30)을 접착하는 상기 접착제(60)로 전도성 재질과 비전도성 재질의 접착제 및 폴리이미드 테이프가 사용된다.Here, as the adhesive 60 for adhering the chip 10 and the inner leads 30, an adhesive and a polyimide tape made of a conductive material and a non-conductive material are used.
이와 같은 구조를 갖는 칩 온 리드 패키지는 내부리드와 칩이 평면 접촉에 의해서 접착되기 때문에 내부리드와 접착제, 접착제와 칩사이에 보이드(void)가 발생하는 문제점이 있다.The chip on lead package having such a structure has a problem in that voids are generated between the inner lead and the adhesive, the adhesive, and the chip because the inner lead and the chip are adhered by the planar contact.
그리고, 내부리드 상부면에 칩이 접착되기 때문에 칩의 본딩패드와 내부리드와의 높이 차이가 크기 때문에 와이어 본딩의 신뢰성에 문제점이 발생된다.In addition, since the chip is bonded to the upper surface of the inner lead, there is a problem in the reliability of wire bonding because the height difference between the bonding pad and the inner lead of the chip is large.
상기 문제점을 해결하기 위해 상기 내부리드들을 하향 절곡하여 와이어 본딩성을 좋게 할 수 있지만, 절곡에 따른 공정이 추가 되어야 하기 때문에 비용이 많이 드는 문제점이 있다.In order to solve the problem, the inner leads may be bent downward to improve wire bonding property, but there is a problem in that the process is expensive because the process according to the bending should be added.
따라서 본 발명의 목적은 칩과 내부리드들 사이의 보이드 발생을 억제할 수 있으며, 와이어 본딩의 신뢰성을 확보할 수 있으며, 박형화를 이룰 수 있는 내부리드 말단에 칩접착 단차부가 형성된 칩 온 리드용 리드프레임 및 그를 이용한 반도체 칩 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to suppress the generation of voids between the chip and the inner lead, to ensure the reliability of wire bonding, chip lead leads for chip-on lead formed on the inner lead end that can be thinned The present invention provides a frame and a semiconductor chip package using the same.
도 1은 종래 기술에 의한 칩 온 리드 패키지의 단면도,1 is a cross-sectional view of a chip on lead package according to the prior art,
도 2는 본 발명에 의한 내부리드 말단의 단차부에 칩이 접착된 상태를 나타내는 부분 절개도.2 is a partial cutaway view showing a state in which a chip is bonded to the stepped portion of the inner lead end according to the present invention.
도 3은 A-A'선 단면도.3 is a cross-sectional view taken along the line A-A '.
도 4는 제 3도의 B부분의 확대 단면도.4 is an enlarged cross-sectional view of a portion B of FIG.
*도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
10,110 : 칩 20,120 : 외부리드10,110: chip 20,120: external lead
30,130 : 내부리드 40,140 : 와이어30,130: Internal lead 40,140: Wire
50,150 : 성형수지 60,160 : 접착제50,150: Molding resin 60,160: Adhesive
135 : 단차부135: stepped portion
상기 목적을 달성하기 위하여, 칩 하부면이 말단에 접착되어 있으며, 그 칩의 본딩패드들과 각기 대응되어 전기적으로 연결된 내부리드들과; 상기 내부리드들과 일체형으로 형성된 외부리드들을 갖는 칩 온 리드용 리드프레임에 있어서,In order to achieve the above object, the lower surface of the chip is adhered to the end, the inner leads are electrically connected to each of the bonding pads of the chip; In the lead frame for a chip on lead having an outer lead formed integrally with the inner leads,
상기 내부리드 말단의 하부면은 평평하고, 상부면에 칩이 접착될 수 있는 하향 단차진 단차부가 형성된 것을 특징으로 하는 내부리드 말단에 칩접착 단차부가 형성된 칩 온 리드용 리드프레임을 제공한다.The lower surface of the inner lead end is flat, and provides a chip-on lead lead frame formed with a chip adhesive step on the inner lead end, characterized in that the lower stepped stepped portion is formed on the upper surface can be bonded to the chip.
상기 다른 목적을 달성하기 위하여, 복수개의 본딩패드를 갖는 칩과; 상기 칩 하부면이 말단에 접착되어 있으며, 상기 본딩패드들과 각기 대응되어 전기적으로 연결된 내부리드들과, 상기 내부리드들과 일체형으로 형성된 외부리드들을 갖는 칩 온 리드용 리드프레임과; 상기 칩과 내부리드들을 보호하기 위해 내재·봉지하는 성형수지;를 포함하는 반도체 칩 패키지에 있어서,In order to achieve the above another object, a chip having a plurality of bonding pads; A lead frame for chip-on leads, wherein the chip bottom surface is bonded to an end and has inner leads electrically connected to the bonding pads, respectively, and the outer leads integrally formed with the inner leads; A semiconductor chip package comprising: a molding resin that is internally encapsulated to protect the chip and internal leads.
상기 내부리드 말단의 하부면은 평평하고, 상부면에 하향 단차가 형성되어 있으며, 상기 말단의 단차부에 칩이 접착된 것을 특징으로 하는 내부리드 말단에 칩접착 단차부가 형성된 칩 온 리드용 리드프레임을 이용한 반도체 칩 패키지를 제공한다.The lower surface of the inner lead end is flat, the lower step is formed on the upper surface, the chip-on lead lead frame having a chip adhesive step on the inner lead end, characterized in that the chip is bonded to the stepped portion of the end It provides a semiconductor chip package using.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 2는 본 발명에 의한 내부리드 말단의 단차부에 칩이 접착된 상태를 나타내는 부분 절개도이고, 도 3은 A-A'선 단면도이고, 도 4는 제 3도의 B부분의 확대 단면도이다.FIG. 2 is a partial cutaway view showing a state in which a chip is bonded to a stepped portion of an inner lead end according to the present invention, FIG. 3 is a cross-sectional view taken along line AA ′, and FIG. 4 is an enlarged cross-sectional view of part B of FIG.
도 2, 도 3 및 도 4를 참조하면, 본 발명에 의한 칩 온 리드 패키지(200)는 칩(110)의 내부리드(130) 말단에 상기 칩(110)이 접착될 수 있는 단차부(135)가 형성되어 있으며, 나머지는 종래 기술에 의한 구조와 동일하다.(도 1 참조)2, 3, and 4, the chip on lead package 200 according to the present invention may have a stepped portion 135 to which the chip 110 may be adhered to an end of an inner lead 130 of the chip 110. ), And the rest is the same as the structure according to the prior art (see Fig. 1).
좀더 상세히 언급하면, 상기 내부리드(130) 말단부분의 하부면은 평평하고, 상부면은 하향 단차진 상기 단차부(135)를 갖는다.In more detail, the lower surface of the distal end of the inner lead 130 is flat, and the upper surface has the stepped portion 135 stepped downward.
그리고, 상기 칩(110)이 상기 단차부(135)에 접착될 때, 그 단차부(135)의 측면과 상부면에 그 칩(110)의 측면과 하부면이 각기 대응되어 접착된다.When the chip 110 is bonded to the stepped part 135, the side and bottom surfaces of the chip 110 correspond to the side and top surfaces of the stepped part 135, respectively.
또한, 상기 칩(110)이 종래 보다 하향되어 접착되기 때문에 그 칩(110)의 본딩패드들(112)과 각기 대응된 상기 내부리드들(130)과의 와이어 본딩이 용이하다.In addition, since the chip 110 is adhered downward than the conventional one, wire bonding between the bonding pads 112 of the chip 110 and the inner leads 130 corresponding to the chip 110 is easy.
따라서, 종래의 평면적인 접착에서 입체적인 접착이 가능하기 때문에 칩과 내부리드들간의 결합력이 증가되어 칩과 내부리드들 사이의 보이드 발생이 억제될 수 있다.Therefore, since the three-dimensional bonding is possible in the conventional planar bonding, the bonding force between the chip and the inner leads is increased, and the generation of voids between the chips and the inner leads can be suppressed.
그리고, 칩이 내부리드의 단차부에 접착되기 때문에 종래 보다 칩의 본딩패드들과 내부리드들의 와이어 본딩의 높이가 낮아져서 와이어 본딩의 신뢰성을 확보할 수 있다.In addition, since the chip is adhered to the stepped portion of the inner lead, the height of the wire bonding of the bonding pads and the inner leads of the chip is lower than that of the prior art, thereby ensuring the reliability of wire bonding.
또한, 칩이 내부리드의 단차부의 높이 만큼이 하향 접착되기 때문에 종래의 패키지보다 박형화를 이룰수 있는 이점(利點)이 있다.In addition, since the chip is adhered downward by the height of the stepped portion of the inner lead, there is an advantage that can be made thinner than the conventional package.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960028598A KR0185571B1 (en) | 1996-07-15 | 1996-07-15 | Leadframe and semiconductor chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960028598A KR0185571B1 (en) | 1996-07-15 | 1996-07-15 | Leadframe and semiconductor chip package |
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| Publication Number | Publication Date |
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| KR980012325A KR980012325A (en) | 1998-04-30 |
| KR0185571B1 true KR0185571B1 (en) | 1999-03-20 |
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|---|---|---|---|
| KR1019960028598A KR0185571B1 (en) | 1996-07-15 | 1996-07-15 | Leadframe and semiconductor chip package |
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| KR (1) | KR0185571B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030025481A (en) * | 2001-09-21 | 2003-03-29 | 주식회사 칩팩코리아 | flip-chip semiconductor package and method of manufacturing thereof |
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| KR980012325A (en) | 1998-04-30 |
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