KR960005965A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
KR960005965A
KR960005965A KR1019950021276A KR19950021276A KR960005965A KR 960005965 A KR960005965 A KR 960005965A KR 1019950021276 A KR1019950021276 A KR 1019950021276A KR 19950021276 A KR19950021276 A KR 19950021276A KR 960005965 A KR960005965 A KR 960005965A
Authority
KR
South Korea
Prior art keywords
wiring board
semiconductor chip
resin
electrode
semiconductor device
Prior art date
Application number
KR1019950021276A
Other languages
Korean (ko)
Inventor
아끼오 스미야
이찌로 안죠
마사찌까 마스다
히로미찌 스즈끼
료 하루따
쥰이찌 아리따
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 가나이 쯔또무
Publication of KR960005965A publication Critical patent/KR960005965A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

범프전극을 거쳐서 실장기판에 실장하는 패키지, 특히 수지봉지형의 볼그리드어레이에 관한 것으로써, 유리 에폭시재를 포함하는 배선기판, 배선기판상에 탑재된 반도체칩, 반도체칩의 여러개의 외부단자와 배선기판상의 여러개의 전극을 접속하는 본딩와이어, 배선기판의 한쪽의 면에만 형성되고 반도체칩과 본딩와이어를 봉하여 막는 수지봉지체 및 배선기판의 다른쪽의 면사에 어레이형상으로 형성된 여러개의 범프전극을 갖고, 수지봉지체는 반도체칩의 중앙영역에 있어서 주변영역보다 얇은 구조를 하고 있다.A package mounted on a mounting substrate via a bump electrode, particularly a resin encapsulated ball grid array, comprising a wiring board containing a glass epoxy material, a semiconductor chip mounted on a wiring board, and a plurality of external terminals and wirings of the semiconductor chip. Bonding wires for connecting several electrodes on a substrate, a resin encapsulation body formed only on one surface of the wiring board and sealing the semiconductor chip and the bonding wire and a plurality of bump electrodes formed in an array shape on the other side yarns of the wiring board. The resin encapsulating member has a structure thinner than the peripheral region in the central region of the semiconductor chip.

이러한 장치에 의해 패키지형성시 수지의 경화수축에 의해서 배선기판이 휘어지지만 얇은 수지부분은 얇으므로 배선기판을 휘어지게 하는 부재로 되기 어려워 휘어짐이 작아진다.With such a device, the wiring board is bent due to curing shrinkage of the resin during package formation, but since the thin resin part is thin, it is difficult to be a member that causes the wiring board to bend, and thus the bending becomes small.

Description

반도체 장치Semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예인 반도체 장치(BallGrid Array : BGA)를 도시한 주요부 단면도이다.1 is a cross-sectional view of an essential part of a semiconductor device (BallGrid Array: BGA) as a first embodiment of the present invention.

제2도는 상기 제1실시예의 BGA의 모식적 단면도이다.2 is a schematic cross-sectional view of the BGA of the first embodiment.

제3도는 상기 제1실시예의 BGA의 평면도이다.3 is a plan view of the BGA of the first embodiment.

제4도는 상기 제1실시예의 BGA의 배선기판구조의 주요부를 도시한 단면도이다.FIG. 4 is a sectional view showing the principal part of the wiring board structure of the BGA of the first embodiment.

Claims (5)

⒜ 상면과 상기 상면과 대향하는 하면을 갖고, 상기 상면상에 형성된 제1의 전극과 상기 하면상에 형성된 제2의 전극을 갖는 배선기판, ⒝ 상기 배선기판의 상면상에 탑재되고, 주면을 가지면, 그의 주변부상에 형성된 패드전극을 갖는 반도체 칩, ⒞ 상기 제1의 전극에 상기 패드전극을 전기적으로 접속하는 본딩와이어, ⒟ 상기 반도체칩과 상기 본딩와이어를 봉하여 막기 위해 상기 배선기판의 사이기 상면상에 형성된 수지봉지체 및 ⒠ 상기 배선기판의 상기 하면상에 형성되고, 상기 제2의 전극에 전기적으로 접속된 범프전극을 포함하며, 상기 수지봉지체의 중앙영역의 두께는 주변영역의 두께보다 얇은 반도체장치.(B) a wiring board having an upper surface and a lower surface opposing the upper surface and having a first electrode formed on the upper surface and a second electrode formed on the lower surface; (iv) mounted on an upper surface of the wiring substrate and having a main surface. A semiconductor chip having a pad electrode formed on its periphery, a bonding wire for electrically connecting the pad electrode to the first electrode, and a separator of the wiring board to seal and block the semiconductor chip and the bonding wire. A resin encapsulation member formed on an upper surface and a bump electrode formed on the lower surface of the wiring board and electrically connected to the second electrode, wherein the thickness of the central region of the resin encapsulation body is the thickness of the peripheral region. Thinner semiconductor device. 제1항에 있어서, 상기 주지봉지체는 상기 중앙영역에 있어서 오목부를 갖는 반도체 장치.The semiconductor device according to claim 1, wherein the main sealing body has a recess in the central region. 제1항에 있어서, 상기 수지봉지체는 트랜스퍼몰드에 의해 형성되는 반도체 장치.The semiconductor device according to claim 1, wherein the resin encapsulation member is formed by a transfer mold. 제1항에 있어서, 상기 배선기판은 유리에폭시기판이고, 사이기 수지봉지체는 에폭시수지인 반도체장치.The semiconductor device according to claim 1, wherein the wiring board is a glass epoxy board, and the sigi resin encapsulation member is an epoxy resin. 제1항에 있어서, 상기 패드전극은 상기 반도체칩의 상기 주며의 주변부에 배치되고, 사이기 제1의 전극은 상기 반도체칩의 주위의 상기 배선기판의 상기 상면상에 배치되며, 상기 수지봉지체의 중앙영역은 상기 패드전극과 본딩와이어보다 안쪽의 영역인 반도체장치.The resin encapsulation body according to claim 1, wherein the pad electrode is disposed at the periphery of the column of the semiconductor chip, and the first phase electrode is disposed on the upper surface of the wiring board around the semiconductor chip. The central region of the semiconductor device is an inner region of the pad electrode and the bonding wire. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950021276A 1994-07-27 1995-07-20 Semiconductor devices KR960005965A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-175606 1994-07-27
JP6175606A JPH0846091A (en) 1994-07-27 1994-07-27 Ball grid array semiconductor device

Publications (1)

Publication Number Publication Date
KR960005965A true KR960005965A (en) 1996-02-23

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ID=15999040

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950021276A KR960005965A (en) 1994-07-27 1995-07-20 Semiconductor devices

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JP (1) JPH0846091A (en)
KR (1) KR960005965A (en)
TW (1) TW296473B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237142A (en) * 2000-02-22 2001-08-31 Shizuki Electric Co Inc Film capacitor and resin molded part
JP5213736B2 (en) * 2009-01-29 2013-06-19 パナソニック株式会社 Semiconductor device
JP2010050488A (en) * 2009-11-30 2010-03-04 Panasonic Corp Semiconductor device and manufacturing method thereof
CN102668042B (en) * 2009-12-24 2015-06-24 株式会社村田制作所 Electronic component manufacturing method

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JPH0846091A (en) 1996-02-16
TW296473B (en) 1997-01-21

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