KR960004090B1 - Semiconductor package - Google Patents

Abstract

The semiconductor package comprises leads equipped with a rear surface of a first semiconductor chip, wires for the connection of bonding pads of the chip and leads, an anisotropic electroconductive layer bonded to the lower of the leads, a second semiconductor chip equipped with a front surface on the lower of the electroconductive layer, and a package body for the protection of the chips and the wires. The electroconductive layer is blended with an insulating material i.e. rubber and a metal powder, and the package body is molded with an epoxy molding compound. The semiconductor package increases a memory capacity.

Description

Semiconductor package

1 is a perspective view including a partial cross section of a general resin-encapsulated semiconductor package.

2 is a cross-sectional view of an embodiment of a conventional stacked semiconductor package.

3 is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

4 is a cross-sectional view showing another embodiment of a semiconductor package according to the present invention.

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which two semiconductor chips are stacked in one package using an anisotropic conductive layer to simplify a manufacturing process and to easily expand memory capacity.

The importance of semiconductor packages is increasing with the recent trend of increasing integration of semiconductor devices, increasing memory capacity, increasing signal processing speed and power consumption, demand for multifunctionalization, and high density mounting.

As the number of input / output terminals increases due to the higher integration of the semiconductor device and the increase in memory capacity, the number of leads, which are input / output terminals for connection to the outside of the semiconductor device, increases, so that the leads are fine pitched to design the leads. Is getting harder.

As the signal processing speed and power consumption of the semiconductor device are increased, a large amount of heat is generated in the semiconductor device, and in order to dissipate the heat, a heat sink for separate heat dissipation of the semiconductor package is installed or a high thermal conductivity is generated. Form the package body from the material. In addition, as the semiconductor devices become more versatile, semiconductor packages having various functions are required.

In general, a semiconductor chip such as an IC or LSI is sealed in a semiconductor package and mounted on a printed circuit board. As shown in FIG. 1, the basic type of the semiconductor package 10 is mounted on the die pad 12, which is a heat dissipating metal plate, by an adhesive such as Ag epoxy or a thermocompression method. Leads 14 are formed at predetermined intervals around the die pad 12. The bonding pad 13, which is an electrode terminal of the semiconductor chip 11, and the lead 14 for connecting an external circuit are formed by the bonding wire 13. The package body 15, which is connected and resin-sealed with an epoxy molding compound (hereinafter referred to as EMC), is formed to surround and protect the semiconductor chip 11 and the wire 13.

Such a resin-encapsulated semiconductor package has a dual in line package (shown in FIG. 1) in which the leads protrude vertically downward from both sides of the package body, and the leads have four sides of the package. The quad flat package protruding into the mainstream is the mainstream. Since the QFP can form a relatively larger number of leads than the DIP, the QFP is suitable for a high density memory device.

For mounting density of such semiconductor chips, a method of directly mounting a semiconductor chip on a printed circuit board and stacking a semiconductor chip or a semiconductor package has been studied.

In particular, in the case of a memory semiconductor chip, there is a method of increasing memory capacity by connecting leads, which are input / output terminals, in parallel. For this purpose, at least two leads of the same semiconductor package are stacked or two semiconductor chips are stacked and then one package is used. And resin encapsulation in a body.

2 shows a stacked package of a semiconductor chip according to the prior art, in which the first and second substrates 18 and 17 are mounted on the upper surface of the first and second semiconductor chips 16 and 17. 19 are mutually insulated and bonded to the back of each other, and the leads 20 are formed at regular intervals therebetween.

The first and second substrates 18 and 19 are formed of an insulating material such as glass or epoxy, and land patterns are formed on the surfaces thereof. The second semiconductor chip 17 is a Miller chip in which a circuit and a bonding pad are formed to be symmetrical with the first semiconductor chip 16, and the first and second semiconductor chips 16 and 17 are made of Ag epoxy or the like. It is mounted by adhesive or thermocompression method.

Bonding pads of the first and second semiconductor chips 16 and 17 and land patterns on the first and second substrates 18 and 19 and wires 21 are connected to each other. It is connected to the lead 20 and the wire 21 again. This two-time wire bonding is intended to prevent the wire from being shortened due to its long length.

In addition, the package body 21 surrounding and protecting the first and second semiconductor chips 16 and 17, the first and second substrates 18 and 19, the leads 20, and the wires 21 are provided. It is formed by molding with molding members such as EMC.

Such semiconductor packages are widely used because they can obtain the same memory capacity by using half the semiconductor packages in a predetermined area such as a memory module or a memory card.

However, the above-described conventional semiconductor package uses two semiconductor chips in one semiconductor package by using a Miller chip which is formed so that the positions of the semiconductor chip and the bonding pad face each other in addition to the semiconductor chip in order to increase memory capacity. As a method, a separate Miller chip must be manufactured and wire bonding must be performed twice, thereby increasing the time and cost required for manufacturing and producing a semiconductor package.

Accordingly, an object of the present invention is to provide a semiconductor package that can easily increase the memory capacity without using the Miller chip of the semiconductor chip, thereby reducing the time and cost required for manufacturing and production.

In order to achieve the above object, the present invention is a semiconductor package that accommodates two semiconductor chips in one package body, the leads are formed at a predetermined interval and the back surface of the first semiconductor chip is mounted on the upper side of one side Wires connecting the bonding pads and the lead of the first semiconductor chip to each other, an anisotropic conductive layer bonded to the lower portions of the leads on which the first semiconductor chip is mounted and electrically conducting only in the vertical direction; And a second semiconductor chip formed to correspond to the first semiconductor chip and mounted below the anisotropic conductive layer, and a package body surrounding and protecting the first and second semiconductor chips and wires. It is done.

Hereinafter, a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view according to an embodiment of the semiconductor package 30 according to the present invention, in which leads 33 formed of an inner lead connected to the semiconductor chip and an outer lead connected to the outside are formed at predetermined intervals. The insulating tape 32 having the first semiconductor chip 31 mounted thereon is adhered to one side of the leads 33 and supported by the leads 33. Bonding pads (not shown) of the leads 33 and the first semiconductor chip 31 are connected by wires 34, and the insulating tape 32 is adhered to both surfaces by an insulating material such as polyimide. Have sex.

An anisotropic conductive layer 35 that is electrically conductive only in an up and down direction is attached to one lower side of the leads 33, and a second semiconductor chip 36 is mounted below the anisotropic conductive layer 35. The package body 37 is formed by molding a molding member such as EMC to surround and protect the first and second semiconductor chips 31, 36, and the wire 34.

In this case, the second semiconductor chip 36 is the same chip as the first semiconductor chip 31, and bonding pads of portions corresponding to each other are connected to the same lead 33, so that the memory capacity is doubled. For example, two semiconductor chips of 8M DRAM can be packaged to have a memory capacity of 16M DRAM.

The anisotropic conductive layer 35 is a mixture of metal powders such as silver (Ag) and the like evenly distributed in the main material of the elastic insulating material, such as rubber, etc., the predetermined pressure at the time of mounting the second semiconductor chip 36 When applied, the anisotropic conductive layer 35 on the bonding pad of the second semiconductor chip 36 is compressed by about 10% of the thickness, and the metal powders of the portions are compressed to be electrically connected only in the vertical direction.

An embodiment in which the anisotropic conductive layer is formed by a method other than the structure in which the metal powder is blended with the main material of the elastic material is shown in FIG. The conductive layer 40 has a through hole formed in a portion of the insulating thin film, such as rubber having elasticity, that corresponds to the bonding pad of the second semiconductor chip 36. The conductive layer 40 conducts the conductive hole 40 in the vertical direction. The pillar 41 is formed, and the 2nd semiconductor chip 36 in which the bump 42 is formed on the bonding pad is crimp-mounted on the said conductive pillar 41. In this case, the conductive pillar 41 is formed by coating a conductive material such as gold (Au) on the surface of a pillar made of elastic material such as rubber, and the bump 42 is a bonding pad of the second semiconductor chip 36. Is to prevent the breakage.

As described above, in the semiconductor package in which two identical memory semiconductor chips are mounted on one package body, the first and second semiconductor chips are disposed on upper and lower sides of the lead using a lead frame without a die pad. Mounted. That is, the first semiconductor chip is mounted on one side of the lead and connected to the lead by wire bonding, and the second semiconductor chip is mounted on the lead and connected to the lead by an anisotropic conductive layer which is electrically conductive only in the vertical direction. Then, the package body was formed of a molding member to surround and protect the first and second semiconductor chips, wires, and the like.

Therefore, the present invention mounts the same two memory semiconductor chips in one semiconductor package, so that no separate Miller chip is required, thereby reducing the time and cost required for the research and production of the multilayer package, and easily increasing the memory capacity. There is an advantage to this.

Claims (6)

A semiconductor package accommodating two semiconductor chips in one package body, comprising: leads formed at a predetermined interval and having a rear surface of a first semiconductor chip mounted on an upper side thereof, bonding pads of the first semiconductor chip; Wires connecting the leads, anisotropic conductive layers that are electrically connected to the lower portions of the leads on which the first semiconductor chip is mounted, and are electrically connected only in the vertical direction, and are formed so as to correspond to the first semiconductor chips. And a package body for protecting the first and second semiconductor chips and the wire, the second semiconductor chip having a front surface mounted on a lower portion thereof. The semiconductor package of claim 1, wherein the first semiconductor chip is mounted on an insulating tape made of a material such as polyimide to be mounted on one side of the leads. The semiconductor package according to claim 1, wherein the anisotropic conductive layer is formed of a layer in which an elastic main material and a powder of a conductive material are blended and evenly distributed. The method of claim 1, wherein the anisotropic conductive layer is an insulating thin film having a through hole is formed in a portion corresponding to the bonding pad of the second semiconductor chip and a conductive pillar formed to be conducted in the vertical direction inside and outside the through hole. The semiconductor package is provided. The semiconductor package according to claim 4, wherein the conductive pillar is coated with a conductive layer on an outer surface of the elastic pillar. The semiconductor package according to claim 1, wherein the package body is formed by resin molding with an epoxy molding compound.