JPH04144269A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04144269A JPH04144269A JP2268963A JP26896390A JPH04144269A JP H04144269 A JPH04144269 A JP H04144269A JP 2268963 A JP2268963 A JP 2268963A JP 26896390 A JP26896390 A JP 26896390A JP H04144269 A JPH04144269 A JP H04144269A
- Authority
- JP
- Japan
- Prior art keywords
- sealed
- resin
- board
- wiring board
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 238000001721 transfer moulding Methods 0.000 claims abstract 2
- 239000004020 conductor Substances 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は゛混成集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a hybrid integrated circuit device.
従来から混成集積回路装置として、モノシックＩＣと同
じリードフレーム上に絶縁エリアを設け、その上に能動
素子および受動素子をベアチップ状態にて搭載し、これ
をワイヤボンディング法により回路接続し、トランスフ
ァモールド封止した構造をもつトランスファモールド型
のハイブリッドＩＣ（以下、ＣＯＭＰＡＣＴと呼称する
）がある。Conventionally, as a hybrid integrated circuit device, an insulating area is provided on the same lead frame as the monolithic IC, active elements and passive elements are mounted on it in the form of bare chips, circuits are connected using wire bonding, and transfer mold sealing is performed. There is a transfer mold type hybrid IC (hereinafter referred to as COMPACT) that has a fixed structure.
これらについては例えば、「最新ハイブリッドテクノロ
ジーｊｐｐ２１５〜ｐｐ２１９；工業調査会、電子材料
編集部、ｒ１９８５ハイブリッドテクノロジー」月刊セ
ミコンダクタワールド（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ
Ｗｏｒｌｄ） 臨時増刊号、ｐｐ１８４〜ｐｐ
１８７・；ブレジャーナル、「モールド型のハイブリッ
ジＩＣＪ第１凹マイクロエレクロニクスシンポジウム論
文集。Regarding these, for example, "Latest Hybrid Technology jppp215-pp219; Industrial Research Group, Electronic Materials Editorial Department, r1985 Hybrid Technology" Monthly Semiconductor World (Semiconductor World)
World) Special issue, pp184-pp
187.; Brejournal, ``Molded High Bridge ICJ 1st Concave Microelectronics Symposium Proceedings.
ＩＳＨＭ ＪＡＰＡＮ）などに述べられている。ISHM JAPAN) etc.
この従来のハイブリッドＩＣ（ＣＯＭＰＡＣＴ＞では、
絶縁エリア上に搭載できるベアチップの寸法およびベア
チップの数量は、絶縁エリアの面積に当然制限を受ける
。In this conventional hybrid IC (COMPACT),
The dimensions and quantity of bare chips that can be mounted on the insulating area are naturally limited by the area of the insulating area.
近年、集積回路装置の高集積化、大規模化にＣい、ベア
チップ寸法も拡大化しており、１０へ１５ｍｍ角のベア
チップが登場してきている。In recent years, as integrated circuit devices have become more highly integrated and larger, the size of bare chips has also increased, and bare chips of 10 mm to 15 mm square have appeared.
所定の絶縁エリア上に寸法の大きなベアチップを複数個
搭載しようとしても絶縁エリア面積の＄限で搭載できな
い場合が多い。また、絶縁エリアの面積は、ＩＣの外形
サイズが決まっている為、大きくもできないという欠点
があった。Even if it is attempted to mount a plurality of large bare chips on a predetermined insulating area, it is often impossible to mount them due to the $ limit of the insulating area area. Another disadvantage is that the area of the insulating area cannot be increased because the external size of the IC is fixed.
本発明の混成集積回路装置は、リードフレーム上に少な
くとも一つの開口部を有する配線基梯と、前記開口部内
に樹脂封止されたベアチップと、前記開口部の樹脂封止
部の表面に少くとも１つのベアチップとを具備し、前記
リードフレーＬの外部端子を除く全体をトランスファモ
ールドＣ：より樹脂封止して構成されている。The hybrid integrated circuit device of the present invention includes a wiring board having at least one opening on a lead frame, a bare chip sealed with resin in the opening, and at least a surface of the resin-sealed portion of the opening. The lead frame L, except for the external terminals, is entirely sealed with a resin using a transfer mold C.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。混成集
積回路装置は、リードフレーム１のアイランド２上に、
開口部３を有するプリント配線基盤４を接着剤等にて貼
付け、開口部３の内のアイランド２上にベアチップ５を
ダイボンディングし、ベアチップ５の所定の電極と開口
部３内に設けた導体部６とを金線７にてワイヤボンディ
ングした後、樹脂８にて封止する。FIG. 1 is a sectional view of a first embodiment of the invention. The hybrid integrated circuit device has on the island 2 of the lead frame 1,
A printed wiring board 4 having an opening 3 is pasted with adhesive or the like, a bare chip 5 is die-bonded onto the island 2 in the opening 3, and a predetermined electrode of the bare chip 5 and a conductor part provided in the opening 3 are bonded. 6 are wire-bonded with a gold wire 7, and then sealed with a resin 8.
さらに、封止された樹脂ｓ上に他のベアチップ９のダイ
ボンディングし、プリント配線基板４上の所定の導体パ
ッド１０とベアチップ９の所定の電極とを金線１１にて
ワイヤボンディングし、さらに、プリント配線基板４上
の所定の導体パッドと外部リード１２とを金線１３にて
ワイヤボンディングし、樹脂１４にて風刺している。Furthermore, another bare chip 9 is die-bonded onto the sealed resin s, and predetermined conductor pads 10 on the printed wiring board 4 and predetermined electrodes of the bare chip 9 are wire-bonded with gold wires 11, and further, Predetermined conductor pads on the printed wiring board 4 and external leads 12 are wire-bonded with gold wires 13 and bonded with resin 14.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
本実施例の混成集積回路装置は、第１図で説明したと同
様に、ベアチップ５を樹脂８にて封止した後、プリント
配線基板４上の所定の導体パッド１０ａにチップコンデ
ンサ１５を例えば銀ペーストにて取り付け、さらに、金
線１３にて、プリント配線基板４の所定の導体パッドと
外部リード１２とをワイヤボンディングし、樹脂１４に
て封止している。In the hybrid integrated circuit device of this embodiment, after a bare chip 5 is sealed with resin 8, chip capacitors 15 are attached to predetermined conductor pads 10a on a printed wiring board 4, for example, as described in FIG. They are attached using paste, and further, predetermined conductor pads of the printed wiring board 4 and external leads 12 are wire-bonded with gold wires 13, and sealed with resin 14.
以上説明したように本発明は、リードフレームのアイラ
ンド上に設けた絶縁エリア内で、従来プリント配線基板
上にベアチップを搭載していただけのものを、プリント
配線基板内と、さらにプリント配線基板上にもベアチッ
プを搭載可能となるため、非常に高密度実装が可能とな
るといろ効果を有する。As explained above, the present invention allows bare chips to be mounted inside the printed wiring board and further on the printed wiring board, instead of mounting bare chips on the printed wiring board within the insulation area provided on the island of the lead frame. Since it is also possible to mount bare chips, it has the advantage of enabling extremely high-density packaging.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は従来の混成集積回
路装置の一例の断面図である。
１・・・リードフレーム、２・・・アイランド、３・・
・開口部、４．４ａ・・・プリント配線基板、３，９゜
１６・・・ベアチップ、６・・・導体部、７，１１゜１
１ａ、１Ｂ・・・金線、８．１４・・・樹脂部、１ｏ、
ａ ・・
導体パッド、
２・・・外部リード、
５・・・
チップコンデンサ。FIG. 1 is a sectional view of a first embodiment of the invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of an example of a conventional hybrid integrated circuit device. 1...Lead frame, 2...Island, 3...
・Opening part, 4.4a...Printed wiring board, 3,9゜16...Bare chip, 6...Conductor part, 7,11゜1
1a, 1B...Gold wire, 8.14...Resin part, 1o,
a... Conductor pad, 2... External lead, 5... Chip capacitor.
Claims (1)
線基板と、前記開口部内に樹脂封止されたベアチップと
、前記開口部の樹脂封止部の表面に少くとも１つのベア
チップとを具備し、前記リードフレームの外部端子を除
く全体をトランスファモールドにより樹脂封止したこと
を特徴とする混成集積回路装置。A wiring board having at least one opening on a lead frame, a bare chip sealed with resin in the opening, and at least one bare chip on a surface of the resin-sealed part of the opening, A hybrid integrated circuit device characterized in that the entire frame except external terminals is sealed with resin by transfer molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268963A JPH04144269A (en) | 1990-10-05 | 1990-10-05 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268963A JPH04144269A (en) | 1990-10-05 | 1990-10-05 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04144269A true JPH04144269A (en) | 1992-05-18 |
Family
ID=17465735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2268963A Pending JPH04144269A (en) | 1990-10-05 | 1990-10-05 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04144269A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414381B1 (en) | 1999-03-15 | 2002-07-02 | Fujitsu Media Devices Limited | Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board |
| JP2006278401A (en) * | 2005-03-28 | 2006-10-12 | Denso Corp | Semiconductor device |
| JP2007116015A (en) * | 2005-10-24 | 2007-05-10 | Mitsubishi Electric Corp | Electronic device |
| JP2007221139A (en) * | 2006-02-17 | 2007-08-30 | Stats Chippac Ltd | Integrated circuit package system having die on base package |
| JP2008091418A (en) * | 2006-09-29 | 2008-04-17 | Elpida Memory Inc | Semiconductor device, and its manufacturing method |
| JP2009239005A (en) * | 2008-03-27 | 2009-10-15 | Toshiba Memory Systems Co Ltd | Semiconductor device and composite lead frame used therefor |
-
1990
- 1990-10-05 JP JP2268963A patent/JPH04144269A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414381B1 (en) | 1999-03-15 | 2002-07-02 | Fujitsu Media Devices Limited | Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board |
| JP2006278401A (en) * | 2005-03-28 | 2006-10-12 | Denso Corp | Semiconductor device |
| JP4556732B2 (en) * | 2005-03-28 | 2010-10-06 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP2007116015A (en) * | 2005-10-24 | 2007-05-10 | Mitsubishi Electric Corp | Electronic device |
| JP2007221139A (en) * | 2006-02-17 | 2007-08-30 | Stats Chippac Ltd | Integrated circuit package system having die on base package |
| JP2008091418A (en) * | 2006-09-29 | 2008-04-17 | Elpida Memory Inc | Semiconductor device, and its manufacturing method |
| JP2009239005A (en) * | 2008-03-27 | 2009-10-15 | Toshiba Memory Systems Co Ltd | Semiconductor device and composite lead frame used therefor |
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