JP2913858B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2913858B2 JP2913858B2 JP2581791A JP2581791A JP2913858B2 JP 2913858 B2 JP2913858 B2 JP 2913858B2 JP 2581791 A JP2581791 A JP 2581791A JP 2581791 A JP2581791 A JP 2581791A JP 2913858 B2 JP2913858 B2 JP 2913858B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- chip
- island
- silicon
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路に関する。This invention relates to hybrid integrated circuits.
【０００２】[0002]
【従来の技術】従来の混成集積回路は、図３に示すよう
に、配線パターンが形成されたセラミック基板５やプリ
ント基板上に、半導体チップとして２つ以上の能動素子
１及び受動素子３をダイボンディング法やフェイスボン
ディング法等により搭載し、更にワイヤー４にて素子と
配線パターンと外部リード７との電気的接続を行なった
のち、モールド樹脂８にて封止する構造となっていた。2. Description of the Related Art As shown in FIG. 3, a conventional hybrid integrated circuit includes two or more active elements 1 and passive elements 3 as semiconductor chips on a ceramic substrate 5 or a printed circuit board on which a wiring pattern is formed. The device is mounted by a bonding method, a face bonding method, or the like, and furthermore, after electrically connecting the element, the wiring pattern, and the external lead 7 with the wire 4, the structure is sealed with a mold resin 8.
【０００３】[0003]
【発明が解決しようとする課題】この従来の混成集積回
路では、所定の電気回路を実現させるためにセラミック
基板又はプリント基板上に所定の導体配線パターンを形
成しており、配線密度はこの配線基板のパターン形成上
の精度によって決定される。通常、配線基板上の最小パ
ターン幅及び間隔は、各々例えば１００μｍ程度となっ
ていた。これはシリコン基板上に形成される配線パター
ンと比較すると、配線密度が小さいため、従来の混成集
積回路の配線密度を大きくすることは困難であった。従
って回路構成の複雑なものを１パッケージ化するために
は、配線基板における配線領域を大きくしなければなら
ないため、搭載する半導体チップの数を多くできないと
いう欠点があった。In this conventional hybrid integrated circuit, a predetermined conductor wiring pattern is formed on a ceramic substrate or a printed circuit board in order to realize a predetermined electric circuit. Is determined by the precision in pattern formation. Usually, the minimum pattern width and the interval on the wiring board are each about 100 μm, for example. Since the wiring density is smaller than that of the wiring pattern formed on the silicon substrate, it has been difficult to increase the wiring density of the conventional hybrid integrated circuit. Accordingly, in order to package a complicated circuit configuration into one package, the wiring area on the wiring board must be increased, and there is a disadvantage that the number of semiconductor chips to be mounted cannot be increased.
【０００４】[0004]
【課題を解決するための手段】第１の発明の混成集積回
路は、アイランドと、このアイランドの周囲に設けられ
た外部リードと、前記アイランド上に固着された配線基
板と、この配線基板上に固着されたアルミ配線を有する
シリコン配線チップ及び複数の半導体チップと、少くと
も前記シリコン配線チップと前記配線基板と前記外部リ
ードとを接続するワイヤーと、前記アイランドと前記配
線基板と前記シリコン基板及び半導体チップと前記外部
リードの一部とを封止する樹脂とを含んで構成される。According to a first aspect of the present invention, there is provided a hybrid integrated circuit comprising: an island; external leads provided around the island; a wiring board fixed on the island; A silicon wiring chip having a fixed aluminum wiring and a plurality of semiconductor chips, at least a wire connecting the silicon wiring chip, the wiring substrate and the external lead, the island, the wiring substrate, the silicon substrate and the semiconductor It is configured to include a resin for sealing the chip and a part of the external lead.
【０００５】[0005]
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の第１の実施例の断面図である。以下
製造工程順に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a first embodiment of the present invention. Hereinafter, description will be made in the order of the manufacturing process.
【０００７】まず配線パターンが形成されているセラミ
ック基板５をアイランド６上に樹脂や半田等により固着
したのち、このセラミック基板５上に能動素子１と受動
素子３等の半導体チップ及びアルミ配線によって回路配
線の一部が形成されているシリコン配線チップ２をダイ
ボンディングする。更に各素子とシリコン配線チップ２
とセラミック基板５との間及びセラミック基板５と外部
リード７との間をワイヤー４により接続する。次にモー
ルド樹脂８にてアイランド６，セラミック基板５及び各
チップ等を封止する。First, a ceramic substrate 5 on which a wiring pattern is formed is fixed on an island 6 by a resin, solder, or the like, and a circuit is formed on the ceramic substrate 5 by semiconductor chips such as active elements 1 and passive elements 3 and aluminum wiring. The silicon wiring chip 2 on which a part of the wiring is formed is die-bonded. Furthermore, each element and silicon wiring chip 2
The ceramic substrate 5 and the ceramic substrate 5 and the external leads 7 are connected by wires 4. Next, the island 6, the ceramic substrate 5, the respective chips, and the like are sealed with the mold resin 8.
【０００８】このように構成された第１の実施例によれ
ば、シリコン配線チップ２により配線密度を大きくでき
るため、搭載する半導体チップの数を多くすることがで
きる。According to the first embodiment configured as described above, since the wiring density can be increased by the silicon wiring chip 2, the number of semiconductor chips to be mounted can be increased.
【０００９】なお、シリコン配線チップ２と能動素子１
及び受動素子３間を直接ワイヤー４で接続し、出来る限
りセラミック基板５上の配線を使用しないようにするこ
とにより、セラミック基板５上の配線領域を小さくする
ことができる。The silicon wiring chip 2 and the active element 1
By connecting the passive elements 3 directly with the wires 4 so as not to use the wiring on the ceramic substrate 5 as much as possible, the wiring area on the ceramic substrate 5 can be reduced.
【００１０】図２は本発明に関連する技術の断面図であ
る。図２において、アイランド６上にはアルミ配線が形
成されたシリコン基板９がダイボンディング法により固
着されており、このシリコン基板９上には半田バンプ１
１を介して複数のフリップチップ１０が搭載されてい
る。そしてシリコン基板９の配線は、金等からなるワイ
ヤー４により外部リード７に接続されている。そしてア
イランド６，シリコン基板８，フリップチップ１０及び
外部リード７の一部はモールド樹脂８により封止されて
いる。FIG. 2 is a sectional view of a technique related to the present invention. In FIG. 2, a silicon substrate 9 on which an aluminum wiring is formed is fixed on an island 6 by a die bonding method.
A plurality of flip-chips 10 are mounted via one. The wiring of the silicon substrate 9 is connected to the external leads 7 by wires 4 made of gold or the like. The island 6, the silicon substrate 8, the flip chip 10, and a part of the external lead 7 are sealed with the mold resin 8.
【００１１】このように構成された本発明に関連する技
術によれば、フリップチップ１０が搭載されている基板
は配線密度の高いシリコン基板９であるため、セラミッ
ク基板等従来の配線密度の低い基板や第１の実施例に比
べ、半導体チップをより多く搭載できる利点がある。[0011] The technique related to the present invention configured as described above.
According to the technique , since the substrate on which the flip chip 10 is mounted is the silicon substrate 9 having a high wiring density, the number of semiconductor chips is larger than that of a conventional substrate having a low wiring density such as a ceramic substrate or the first embodiment. There is an advantage that can be mounted.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、アルミ配
線を有する配線チップを半導体チップと一緒に搭載する
ことにより、混成集積回路の配線密度を大きくできるた
め、搭載する半導体チップの数をふやすことができると
いう効果を有する。As described above, according to the present invention, a wiring chip having aluminum wiring is mounted together with a semiconductor chip.
Accordingly, the wiring density of the hybrid integrated circuit can be increased, so that the number of semiconductor chips to be mounted can be increased.
【図１】本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明に関連する技術の断面図である。FIG. 2 is a sectional view of a technique related to the present invention .
【図３】従来の混成集積回路の一例の断面図である。FIG. 3 is a cross-sectional view of an example of a conventional hybrid integrated circuit.
１ 能動素子 ２ シリコン配線チップ ３ 受動素子 ４ ワイヤー ５ セラミック基板 ６ アイランド ７ 外部リード ８ モールド樹脂 ９ シリコン基板 １０ フリップチップ １１ 半田バンプ DESCRIPTION OF SYMBOLS 1 Active element 2 Silicon wiring chip 3 Passive element 4 Wire 5 Ceramic substrate 6 Island 7 External lead 8 Mold resin 9 Silicon substrate 10 Flip chip 11 Solder bump
Claims (1)
設けられた外部リードと、前記アイランド上に固着され
た配線基板と、この配線基板上に固着されたアルミ配線
を有するシリコン配線チップ及び複数の半導体チップ
と、少なくとも前記シリコン配線チップと前記配線基板
と前記外部リードとを接続するワイヤーと、前記アイラ
ンドと前記配線基板と前記シリコン配線チップ及び半導
体チップと前記外部リードの一部とを封止する樹脂とを
含むことを特徴とする混成集積回路。1. A silicon wiring chip having an island, external leads provided around the island, a wiring board fixed on the island, aluminum wiring fixed on the wiring board, and a plurality of semiconductors A chip, a wire for connecting at least the silicon wiring chip, the wiring substrate, and the external lead, and a resin for sealing the island, the wiring substrate, the silicon wiring chip, the semiconductor chip, and a part of the external lead. A hybrid integrated circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2581791A JP2913858B2 (en) | 1991-02-20 | 1991-02-20 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2581791A JP2913858B2 (en) | 1991-02-20 | 1991-02-20 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0645514A JPH0645514A (en) | 1994-02-18 |
| JP2913858B2 true JP2913858B2 (en) | 1999-06-28 |
Family
ID=12176421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2581791A Expired - Lifetime JP2913858B2 (en) | 1991-02-20 | 1991-02-20 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2913858B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402442B2 (en) | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
| JP4745925B2 (en) * | 2006-09-06 | 2011-08-10 | アスモ株式会社 | Connector integrated semiconductor module for automotive motor control |
-
1991
- 1991-02-20 JP JP2581791A patent/JP2913858B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0645514A (en) | 1994-02-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990316 |