JPH04164352A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04164352A JPH04164352A JP29156490A JP29156490A JPH04164352A JP H04164352 A JPH04164352 A JP H04164352A JP 29156490 A JP29156490 A JP 29156490A JP 29156490 A JP29156490 A JP 29156490A JP H04164352 A JPH04164352 A JP H04164352A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- resin
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 18
- 238000001721 transfer moulding Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 14
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 8
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000004593 Epoxy Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 239000012776 electronic material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to hybrid integrated circuit devices.
従来、リードフレーム上に絶縁エリアを設け、その上に
所定の配線が施されたプリント配線基板を貼り付け、さ
らに、能動素子および受動素子をヘアチップ状態にて搭
載し、ベアチップ上の所定の電極とプリント配線基板上
の所定の電極間およびプリント配線基板上の所定の電極
とリードフレーム上の所定の電極間を金線にてワイヤボ
ンディング法により接続し、トランスファモールド法に
より樹脂封止した構造をもつハイブリッドＩＣ（以下、
ＣＯＭＰＡＣＴと呼称する）がある（例えば、「最新ハ
イブリッドテクノロジーＪ Ｐｐ２１５〜ｐｐ２１９；
工業調査会、電子材料編集部、「最新ハイブリッドテク
ノロジーＪｐｐ２１５〜ｐｐ２１９；工業調査会、電子
材料編集部、「′８５ハイブリッドテクノロジー」月刊
Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ Ｗｏｒｌｄ臨時増刊号
、ｐｐ１８４〜ｐｐ１８７：プレスジャーナル、［モー
ルド型のハイブリッドＩＣ」第１回マイクロエレクトロ
シンポジウム論文集、ＩＳＨＭＪＡＰＡＮ）。Conventionally, an insulating area was provided on a lead frame, a printed wiring board with predetermined wiring was pasted on top of the insulating area, and active elements and passive elements were mounted in the form of hair chips, and the predetermined electrodes on the bare chip were mounted. It has a structure in which the predetermined electrodes on the printed wiring board and between the predetermined electrodes on the printed wiring board and the predetermined electrodes on the lead frame are connected using wire bonding method with gold wire and sealed with resin using transfer molding method. Hybrid IC (hereinafter referred to as
COMPACT) (for example, "Latest Hybrid Technology J Pp215-pp219;
Kogyo Kenkyukai, Electronic Materials Editorial Department, "Latest Hybrid Technology Jpp215-pp219; Kogyo Kenkyukai, Electronic Materials Editorial Department, '85 Hybrid Technology" Monthly Sem1conductor World Special Issue, pp184-pp187: Press Journal, [Mold Type "Hybrid IC" Proceedings of the 1st Microelectro Symposium, ISHM JAPAN).
この従来のハイブリッドＩＣ（ＣＯＭＰＡＣＴ）におい
て、複数個の半導体素子をベアチップ状態にてプリント
配線基板上に搭載し、トランスファモールド法にて樹脂
封止する場合、樹脂の流しこみ口（ゲートと呼称する）
より、樹脂を所定の金型内に充填させ硬化させるにおい
て、プリント配線基板上に搭載した複数の半導体素子に
対しては樹脂がゲートより流れ込む際、ゲートにより近
い半導体素子はど受ける粘性抵抗が大きく、半導体素子
の所定の電極から、プリント配線基板上の所定の電極へ
ワイヤボンディング法により接続された金線が粘性抵抗
により受ける力のために、金線が変形するという問題点
があった。In this conventional hybrid IC (COMPACT), when multiple semiconductor elements are mounted on a printed wiring board in the bare chip state and encapsulated with resin using the transfer molding method, a resin pouring port (referred to as a gate) is used.
Therefore, when filling resin into a predetermined mold and curing it, when the resin flows from the gate to multiple semiconductor elements mounted on a printed wiring board, the semiconductor elements closer to the gate receive greater viscous resistance. However, there has been a problem in that the gold wire connected from a predetermined electrode of a semiconductor element to a predetermined electrode on a printed wiring board by wire bonding is deformed due to the force exerted by viscous resistance.
本発明の混成集積回路装置は、少なくとも二つの能動素
子または受動素子をベアチップ状態にて搭載したプリン
ト配線基板をリードフレーム上に具備し、トランスファ
モールド法により樹脂封止した混成集積回路装置におい
て、所定の厚みを有する直方体の基本を該プリント配線
基板上の所定の位置に具備したことを特徴としている。The hybrid integrated circuit device of the present invention is a hybrid integrated circuit device that is equipped with a printed wiring board on which at least two active elements or passive elements are mounted in bare chip form on a lead frame, and is sealed with resin by transfer molding. The present invention is characterized in that a rectangular parallelepiped base having a thickness of 1 is provided at a predetermined position on the printed wiring board.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の混成集積回路装置の断面図
である。FIG. 1 is a sectional view of a hybrid integrated circuit device according to an embodiment of the present invention.
リードフレーム１上に、プリント配線基板２を貼り付け
、プリント配線基板２上に半導体チップ３をダイボンデ
ィングし、さらにエポキシ系樹脂でてきな直方体の絶縁
基板４を、第１図に示すように、例えば、絶縁ペースト
にて搭載し、１５０℃程度でキュアする、次に例えば、
２５μｍφの金線５にて、半導体チップ３の所定の電極
とプリント配線基板２上の所定の電極とをワイヤボンデ
ィングし、樹脂６にてトランスファモールド法にて、樹
脂封止して本発明による一実施例の混成集積回路装置が
得られる。A printed wiring board 2 is pasted on the lead frame 1, a semiconductor chip 3 is die-bonded onto the printed wiring board 2, and a large rectangular parallelepiped insulating board 4 made of epoxy resin is attached as shown in FIG. For example, it is mounted with insulating paste and cured at about 150°C, then, for example,
A predetermined electrode of the semiconductor chip 3 and a predetermined electrode on the printed wiring board 2 are wire-bonded using a gold wire 5 having a diameter of 25 μm, and the resin is sealed with a resin 6 using a transfer molding method, thereby forming a package according to the present invention. A hybrid integrated circuit device of the embodiment is obtained.
次に本発明の第、２の実施例について説明する。Next, a second embodiment of the present invention will be described.
第２図は、本発”’萌の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
プリント配線基板２上に半導体チップ３をダイボンディ
ングし、図示の如く、半導体チップ３の周囲に絶縁基体
４ａ、４ｂ、４ｃを搭載し、金線らにてワイヤボンディ
ングし、樹脂６をトランスファモールド法にて樹脂封止
して本発明の第２の実施例が得られる。A semiconductor chip 3 is die-bonded onto a printed wiring board 2, and as shown in the figure, insulating substrates 4a, 4b, and 4c are mounted around the semiconductor chip 3, wire-bonded with gold wire, etc., and a resin 6 is transferred by transfer molding. A second embodiment of the present invention is obtained by resin sealing.
以上説明したように本発明は、プリント配線基板上に半
導体ベアチップをタイボンディングし、所定の電極間を
金線にてワイヤボンディングし、トランスファモールド
法にて樹脂封止する場合、金線が樹脂封止時に受ける粘
性抵抗力により変形し、隣りの金線等とショートすると
いう問題に対して、樹脂封止時、絶縁基体が、金線の変
形を防ぐ防波堤の役割を果すため、金線の変形を防げる
という効果がある。As explained above, in the present invention, when a semiconductor bare chip is tie-bonded onto a printed wiring board, gold wire is wire-bonded between predetermined electrodes, and resin-sealed using a transfer molding method, the gold wire is resin-sealed. To deal with the problem of deformation due to viscous resistance and short-circuiting with neighboring gold wires, etc., during resin sealing, the insulating base acts as a bulwark to prevent deformation of the gold wire. It has the effect of preventing
従来、樹脂封止時の粘性抵抗力による金線の変形による
ショート等の不具合発生率が約０．５％程度あったもの
が、本発明によるとほぼ皆無になった。Conventionally, the incidence of defects such as short circuits due to deformation of the gold wire due to viscous resistance during resin sealing was approximately 0.5%, but according to the present invention, this has been virtually eliminated.
第１図および第２図は、本発明の実施例の断面図を示す
。
１・・・リードフレーム、２・・・プリント配線基板、
３・・・半導体チップ、４．４ａ、４ｂ、４ｃ・・・絶
縁基体、５・・・金線、６・・・樹脂。1 and 2 show cross-sectional views of embodiments of the invention. 1... Lead frame, 2... Printed wiring board,
3... Semiconductor chip, 4.4a, 4b, 4c... Insulating base, 5... Gold wire, 6... Resin.
Claims (1)
プ状態にて搭載したプリント配線基板をリードフレーム
上に具備し、トランスファモールド法により樹脂封止し
た混成集積回路装置において、所定の厚みを有する直方
体の基体を該プリント配線基板上の所定の位置に具備し
たことを特徴とする混成集積回路装置。In a hybrid integrated circuit device, which is equipped with a printed wiring board on which at least two active elements or passive elements are mounted in bare chip form on a lead frame, and which is sealed with resin by transfer molding, a rectangular parallelepiped base having a predetermined thickness is used. A hybrid integrated circuit device, characterized in that it is provided at a predetermined position on the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29156490A JPH04164352A (en) | 1990-10-29 | 1990-10-29 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29156490A JPH04164352A (en) | 1990-10-29 | 1990-10-29 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04164352A true JPH04164352A (en) | 1992-06-10 |
Family
ID=17770557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29156490A Pending JPH04164352A (en) | 1990-10-29 | 1990-10-29 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04164352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100411156C (en) * | 2004-03-24 | 2008-08-13 | 三洋电机株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
-
1990
- 1990-10-29 JP JP29156490A patent/JPH04164352A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100411156C (en) * | 2004-03-24 | 2008-08-13 | 三洋电机株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
| US7709941B2 (en) * | 2004-03-24 | 2010-05-04 | Sanyo Electric Co., Ltd. | Resin-sealed semiconductor device and method of manufacturing the same |
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