KR100499328B1 - Flip Chip Packaging Method using Dam - Google Patents
Flip Chip Packaging Method using Dam Download PDFInfo
- Publication number
- KR100499328B1 KR100499328B1 KR10-2003-0018592A KR20030018592A KR100499328B1 KR 100499328 B1 KR100499328 B1 KR 100499328B1 KR 20030018592 A KR20030018592 A KR 20030018592A KR 100499328 B1 KR100499328 B1 KR 100499328B1
- Authority
- KR
- South Korea
- Prior art keywords
- dam
- flip chip
- wafer
- matrix board
- chip
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 11
- 239000011159 matrix material Substances 0.000 claims abstract description 26
- 238000000465 moulding Methods 0.000 claims abstract description 15
- 238000005520 cutting process Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000004593 Epoxy Substances 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000007650 screen-printing Methods 0.000 claims abstract description 4
- 230000006835 compression Effects 0.000 claims abstract description 3
- 238000007906 compression Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 description 1
- AVYVHIKSFXVDBG-UHFFFAOYSA-N N-benzyl-N-hydroxy-2,2-dimethylbutanamide Chemical compound C(C1=CC=CC=C1)N(C(C(CC)(C)C)=O)O AVYVHIKSFXVDBG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 댐(DAM)을 이용한 플립칩 패키징 방법에 관한 것이다. 이러한 본 발명의 방법은, 웨이퍼에 스터드 범프를 형성하는 범프 형성단계; 웨이퍼의 일면에 테이프를 접착하는 테이프 접착단계; 테이프가 접착된 웨이퍼를 칩 단위로 절단하는 다이싱단계; 매트릭스 보드에 댐을 형성하는 단계; 댐이 형성된 매트릭스 보드에 칩을 열압착 및 초음파를 인가하여 접착하는 플립칩 본딩 단계; 플립칩이 본딩된 매트릭스 보드를 소정의 조건으로 가열하여 댐을 경화하는 단계; 및 매트릭스 보드를 커팅하여 개별칩 소자로 분리하는 단계를 포함하는 것을 특징으로 한다.여기서, 댐을 형성하는 단계는 스텐실 스크린 프린팅이나 디스펜싱, 혹은 도팅 중 어느 하나의 방법으로 댐을 형성하고, 상기 댐의 재료는 NCP, NCF, 이방성전도물질(ACF), ACP, 에폭시, 몰딩 콤파운드 중 어느 하나를 사용한다. 본 발명에 따르면 플립칩 본딩을 함에 있어서 열압착에 초음파를 부가하여 공정을 신속하게 처리할 수 있고, 특히 매트릭스 보드에 댐을 형성한 후 칩을 본딩하고 댐을 경화시킨 후 개별소자로 분리함으로써 웨이퍼상의 회로가 오염되는 것을 방지함과 아울러 대량생산의 효율성이 향상되는 효과가 있다.The present invention relates to a flip chip packaging method using a dam (DAM). Such a method of the present invention includes a bump forming step of forming a stud bump on a wafer; A tape adhesion step of adhering the tape to one surface of the wafer; A dicing step of cutting the wafer to which the tape is bonded in chip units; Forming a dam on the matrix board; A flip chip bonding step of bonding chips to a matrix board on which a dam is formed by applying thermal compression and ultrasonic waves; Curing the dam by heating the matrix board bonded with the flip chip to a predetermined condition; And cutting the matrix board to separate the individual chip elements. The dam forming step may include forming a dam by any one of stencil screen printing, dispensing, or dotting. The material of the dam is any one of NCP, NCF, anisotropic conductive material (ACF), ACP, epoxy, and molding compound. According to the present invention, in the case of flip chip bonding, an ultrasonic wave may be added to thermocompression to quickly process the process. In particular, after forming a dam on the matrix board, the chip is bonded, the dam is cured, and the wafer is separated into individual elements. In addition to preventing contamination of the circuit of the bed, there is an effect of improving the efficiency of mass production.
Description
본 발명은 반도체 패키징 기술에 관한 것으로, 더욱 상세하게는 댐(DAM)을 이용한 플립칩 패키징 방법에 관한 것이다.The present invention relates to a semiconductor packaging technology, and more particularly to a flip chip packaging method using a dam (DAM).
일반적으로, 반도체 패키지는 전기적으로 외부와 연결할 수 있는 핀과 칩(다이)을 장착시킬 수 있는 구조물인 리드 프레임, 리드 프레임과 본딩패드를 연결하는 선, 칩을 장착하는 패들, 및 봉합물질들로 이루어진다. 그리고 반도체 패키지는 사용되는 밀봉재료에 따라 수지 밀봉 패키지, TCP(Tape Carrier Package) 패키지, 글래스 밀봉 패키지, 금속 밀봉 패키지 등으로 구분되고, 실장방법에 따라 삽입형과 표면실장형(SMT: Surface Mount Technology)으로 구분된다. 삽입형 패키지로는 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로는 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array) 등이 있다.In general, a semiconductor package includes a lead frame, a structure for mounting a pin and a chip (die) to be electrically connected to the outside, a line connecting the lead frame and the bonding pad, a paddle for mounting the chip, and an encapsulant. Is done. The semiconductor package is classified into a resin sealing package, a tape carrier package (TCP), a glass sealing package, a metal sealing package, etc. according to the sealing material used, and an insert type and a surface mount type (SMT) according to the mounting method. Separated by. Insertable packages include DIP (Dual In-line Package) and PGA (Pin Grid Array), and surface mount types include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier) and CLCC (Ceramic Leaded Chip Carrier). And Ball Grid Array (BGA).
한편, 칩(Die)을 기판(Substrate)에 장착하거나 물리적인 연결방식을 본딩(bonding)이라 하는데, 본딩은 다이 본딩(Die Bonding), 와이어 본딩(Wire Bonding), TAB, 플립칩 본딩(Flip Chip Bonding) 등이 있다. 여기서, 플립칩 본딩은 칩의 접속 패드에 돌기(Dump)를 만들어 PCB 기판에 직접에 접속하는 방식으로 일명 C-4라고도 하며, 선접속 과정이 없고 가장 경박 단소할 뿐만 아니라 집적도나 성능면에서 탁월하여 극소형화되는 전자제품에 널리 각광받고 있는 기술이다.On the other hand, the chip (Die) is mounted on the substrate (Substrate) or the physical connection method is called (bonding), bonding is die bonding (Die Bonding), wire bonding (Wire Bonding), TAB, Flip Chip Bonding (Flip Chip bonding) Bonding). Here, flip chip bonding is called C-4 by making a bump on the chip's connection pad and directly connecting it to the PCB board, and there is no wire connection process, it is the lightest and simplest, and is excellent in integration and performance. It is a technology that is widely spotlighted in the miniaturized electronic products.
도 1은 일반적인 플립칩 본딩을 설명하기 위해 도시한 도면이다.1 is a diagram illustrating a general flip chip bonding.
도 1을 참조하면, 플립칩 본딩은 웨이퍼(10)로부터 절단된 칩(11)의 본딩 패드(12)에 스터드 펌프(stud bump: 13)를 형성한 후 칩(11)을 뒤집어(Flip) 기판(20)상의 리드패드(21)에 직접 접속하는 구조이다. 이때 칩(11)을 세라믹 패키지(도 2의 22)에 플립칩 본딩하는 패키지 타입 플립칩 본딩과, 메인보드(25)상에 직접 플립칩 본딩하는 온보드 타입 플립칩 본딩으로 구분된다.Referring to FIG. 1, in flip chip bonding, a stud pump 13 is formed on a bonding pad 12 of a chip 11 cut from a wafer 10, and then the chip 11 is flipped over to form a substrate. The structure directly connects to the lead pad 21 on (20). In this case, the chip 11 is divided into a package type flip chip bonding for flip chip bonding to a ceramic package (22 of FIG. 2) and an onboard type flip chip bonding for flip chip bonding directly onto the main board 25.
도 2a는 패키지 타입 플립칩 본딩의 예이고, 도 2b는 온보드 타입 플립칩 본딩의 예이다.2A is an example of package type flip chip bonding, and FIG. 2B is an example of onboard type flip chip bonding.
도 2a를 참조하면, 패키지 타입에서 칩(11)은 세라믹 패키지(22)에 플립칩 본딩되어 있고, 이 패키지가 메인보드(25)에 실장되어 있다. 세라믹 패키지(22)는 패키지 뚜껑(23)에 의해 밀봉되어 있으며, 온보드 타입은 칩(11)이 메인보드(25)상에 직접 플립칩 본딩된 후 수지(26) 등에 의해 범프(13) 연결부분이 몰딩되어 있다.Referring to FIG. 2A, in the package type, the chip 11 is flip chip bonded to the ceramic package 22, and the package is mounted on the main board 25. The ceramic package 22 is sealed by the package lid 23, and the onboard type is connected to the bump 13 by the resin 26 after the chip 11 is flip-chip bonded directly onto the main board 25. This is molded.
그런데 이와 같은 종래의 플립칩 본딩은 열압착방식을 사용하므로 공정속도가 느리고, 와이어 본딩은 소형 경박화에 한계성이 있는 문제점이 있다. 또한 플립칩 본딩에서 세라믹 패키지를 사용할 경우에는 각 패키지별로 일일이 작업을 해야 하고 패키지 뚜껑을 다 씌워야 하므로 대량생산이 어렵고 공정이 복잡한 문제점이 있고, 세라믹 패키지를 사용하지 않을 경우에는 웨이퍼 표면에 있는 회로가 오염될 우려가 있다.However, since the conventional flip chip bonding uses a thermocompression bonding method, the process speed is low, and wire bonding has a problem in that there is a limit in miniaturization and thinning. In addition, when using a ceramic package in flip chip bonding, each package must be worked on individually and the lid of the package must be covered. Therefore, mass production is difficult and the process is complicated. There is a risk of contamination.
본 발명은 상기와 같은 문제점을 해결하기 위하여 제안된 것으로, 공정속도가 빠르고, 웨이퍼 표면에 있는 회로의 오염을 방지할 수 있는 댐(DAM)을 이용한 플립칩 패키징 방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a flip chip packaging method using a dam (DAM) which is fast in process speed and prevents contamination of a circuit on a wafer surface.
상기와 같은 목적을 달성하기 위하여 본 발명의 방법은, 웨이퍼에 스터드 범프를 형성하는 범프 형성단계; 웨이퍼의 일면에 테이프를 접착하는 테이프 접착단계; 상기 테이프가 접착된 웨이퍼를 칩 단위로 절단하는 다이싱단계; 매트릭스 보드에 댐을 형성하는 단계; 상기 댐이 형성된 매트릭스 보드에 칩을 열압착 및 초음파를 인가하여 접착하는 플립칩 본딩 단계; 상기 플립칩이 본딩된 매트릭스 보드를 소정의 조건으로 가열하여 댐을 경화하는 단계; 및 상기 매트릭스 보드를 커팅하여 개별칩 소자로 분리하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method of the present invention, the bump forming step of forming a stud bump on the wafer; A tape adhesion step of adhering the tape to one surface of the wafer; A dicing step of cutting the tape-attached wafer into chips; Forming a dam on the matrix board; Flip chip bonding to bond the chip to the matrix board on which the dam is formed by applying thermal compression and ultrasonic waves; Curing the dam by heating the matrix board to which the flip chip is bonded under a predetermined condition; And cutting the matrix board to separate the individual chip elements.
여기서, 상기 댐을 형성하는 단계는 스텐실 스크린 프린팅이나 디스펜싱, 혹은 도팅 중 어느 하나의 방법으로 댐을 형성하고, 상기 댐의 재료는 NCP(Non-Conductive Paste), NCF(Non-Conductive Film), 이방성전도물질(ACF), ACP, 에폭시, 몰딩 콤파운드(molding compound) 중 어느 하나를 사용한다.The dam may be formed by any one of stencil screen printing, dispensing, or dotting, and the dam material may be formed of non-conductive paste (NCP), non-conductive film (NCF), Any one of anisotropic conductive material (ACF), ACP, epoxy, and molding compound is used.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 자세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 댐을 이용한 플립칩 패키징 방법을 도시한 순서도이다.3 is a flowchart illustrating a flip chip packaging method using a dam according to the present invention.
본 발명에 따른 댐을 이용한 플립칩 패키징 방법은 도 3에 도시된 바와 같이, 웨이퍼를 입력받아 골드 스터드 범프를 형성하는 단계(S1,S2), 테이프를 접착하는 단계(S3), 웨이퍼를 절단하는 단계(S4), 리드(Lead) 프레임을 준비하는 단계(S9), 리드 프레임에 댐을 형성하는 단계(S10), 댐이 형성된 리드 프레임에 칩을 접착하는 플립칩 접착단계(S5), 댐을 경화하는 단계(S6), 몰딩하는 단계(S7), 패키지별로 분리하는 단계(S8)로 이루어진다.In the flip chip packaging method using a dam according to the present invention, as shown in FIG. 3, a step of forming a gold stud bump by receiving a wafer (S1, S2), adhering a tape (S3), and cutting a wafer Step S4, preparing a lead frame (S9), forming a dam in the lead frame (S10), flip chip bonding step (S5) for bonding the chip to the lead frame is formed dam, dam Hardening step (S6), molding step (S7), it consists of a step (S8) of separating by package.
도 3을 참조하면, 스터드 범프(Stud Bump)를 형성하는 단계(S2)는 웨이퍼(10)의 알루미늄 패드(12)에 접속을 위한 골드 스터드 범프(Gold Stud Bump)를 형성하는 공정으로서, 도 4에 도시된 바와 같이 웨이퍼(10) 상의 칩(11)들에 구현된 알루미늄 본딩패드(12)에 금으로 된 스터드 범프(13)를 형성한다. 통상, 범프(Bump)의 형태는 알루미늄 패드(12) 위에 길게 돌기가 형성된 형태와 돌기가 낮은 형태가 있다. 도 4를 참조하면, 웨이퍼(10)에는 다수의 칩들(11)이 반도체 제조공정을 통해 제조되어 있고, 각 칩(11)의 본딩패드(12)에는 스터드 범프(13)가 형성되어 있다.Referring to FIG. 3, step S2 of forming a stud bump is a process of forming a gold stud bump for connection to the aluminum pad 12 of the wafer 10. As shown in FIG. 1, gold stud bumps 13 are formed on the aluminum bonding pads 12 implemented on the chips 11 on the wafer 10. In general, bumps have a form in which protrusions are formed on the aluminum pad 12 and low protrusions. Referring to FIG. 4, a plurality of chips 11 are manufactured on a wafer 10 through a semiconductor manufacturing process, and stud bumps 13 are formed on the bonding pads 12 of each chip 11.
테이프를 접착하는 공정(S3)은 범프(13)가 올려진 웨이퍼(10)를 다이싱할 경우에 다이(칩)(11)가 개별적으로 이탈하지 않도록 테이프로 고정해주는 공정이다. 테이프 접착시의 수직 구조는 도 5에 도시된 바와 같이, 양단에 위치한 프레임 링(54)으로 테이프(52)를 지지하면서 웨이퍼(10)를 테이프 접착면에 올려 놓아 접착시킨다.The step of adhering the tape (S3) is a step of fixing the die (chip) 11 with tape so as not to separate from the wafer 10 when the bump 13 is mounted. As shown in FIG. 5, the vertical structure at the time of tape adhesion is supported by placing the wafer 10 on the tape adhesive surface while supporting the tape 52 with the frame rings 54 positioned at both ends thereof.
웨이퍼 절단 공정(S4)은 웨이퍼 상태의 칩들을 절단기(도 6의 60)에 의해 개별적으로 분리하는 공정으로서, 절단시의 측단면도는 도 6에 도시된 바와 같이 절단기(60)의 블레이드(61)가 웨이퍼(10)를 완전히 자르고 테이프(52)는 일부만 잘라 절단된 후에도 테이프(52)에 의해 칩(11)들이 개별적으로 흩어지지 않게 되어 있다. 이와 같이 절단된 상태의 웨이퍼(10)는 도 6의 (나)에 도시된 바와 같은데, 도 6에서 참조번호 63은 웨이퍼의 두께(Wafer Thickness)를 나타내고, 참조번호 64는 절단 깊이(Cut Depth)를 나타내며, 참조번호 65는 인덱스(Index), 참조번호 66은 절단 두께(Cut Width)를 나타낸다.The wafer cutting step S4 is a step of separately separating chips in a wafer state by a cutting machine (60 of FIG. 6), and a side cross-sectional view at the time of cutting is shown by a blade 61 of the cutting machine 60 as shown in FIG. 6. Even after the wafer 10 is completely cut and the tape 52 is partially cut and cut, the chips 11 are not individually scattered by the tape 52. The wafer 10 in the cut state is as shown in FIG. 6B, in which reference numeral 63 denotes a wafer thickness, and reference numeral 64 denotes a cut depth. Reference numeral 65 denotes an index and reference numeral 66 denotes a cut width.
한편, 본 발명에 따라 댐을 형성하는 방식의 플립칩 본딩에서는 평판의 리드 프레임(71)에 각 칩(11)을 구분하는 벽(wall) 역할을 하는 댐(82)을 형성한 후 댐(82)안에 칩(11)을 본딩한다. 따라서 플립칩 본딩공정(S5)전에 리드 프레임(71)에 댐(82)을 형성하는 공정을 거쳐야 한다.Meanwhile, in flip chip bonding in which a dam is formed according to the present invention, a dam 82 is formed on a lead frame 71 of a flat plate and serves as a wall for separating each chip 11. The chip 11 is bonded in. Therefore, the dam 82 must be formed in the lead frame 71 before the flip chip bonding process S5.
도 7은 본 발명에 따라 댐이 형성되어 칩이 부착될 리드 프레임과 같은 매트릭스 보드(71)를 도시한 도면이고, 도 8은 매트릭스 보드(71)에 댐(82)을 형성하는 것을 나타낸다. 도 7에서 매트릭스 보드(71)는 일정간격으로 칩이 부착될 영역에 패드(72)가 형성되어 있다. 이와 같은 매트릭스 보드(71)에 스텐실 스크린 프린팅, 디스펜싱(dispensing), 또는 도팅(Dotting) 방법으로 댐(82)을 형성한다. FIG. 7 illustrates a matrix board 71 such as a lead frame to which a dam is formed and to which a chip is attached according to the present invention, and FIG. 8 illustrates forming a dam 82 on the matrix board 71. In FIG. 7, the pads 72 are formed in regions where chips are attached at regular intervals. The dam 82 is formed on the matrix board 71 by stencil screen printing, dispensing, or dotting.
도 8은 도 7과 같은 매트릭스 보드(71)에 댐(82)이 형성된 것을 도시한 평면도로서, 칩이 장착될 영역의 주변에 댐(82)을 형성함으로써 내부 회로가 오염되는 것을 방지할 수 있다. 댐(82)의 재질로는 NCP(Non-Conductive Paste), NCF(Non-Conductive Film), 이방성전도물질(ACF), ACP, 에폭시, 몰딩 콤파운드(molding compound) 등이 이용될 수 있다.FIG. 8 is a plan view illustrating that the dam 82 is formed on the matrix board 71 as shown in FIG. 7, and the internal circuit may be prevented from being contaminated by forming the dam 82 around the area where the chip is to be mounted. . As the material of the dam 82, a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive material (ACF), an ACP, an epoxy, a molding compound, or the like may be used.
이와 같이 댐(82)을 사용하는 본 발명의 방법은 세라믹이나 LTCC, HTCC, PCB, 리드 프레임 등과 같은 매트릭스 보드(71) 위에 직접 여러개의 칩을 올린 후 자르는 방법으로서 대량생산의 효율성을 높이고, 패키지 가격을 줄일 수 있다. 즉, 세라믹 패키지를 사용할 경우 한개 한개 일일이 작업해야 하고, 패키지 뚜껑을 다 씌워야 하므로 대량생산의 효율성이 떨어지는 문제점이 있으나 본 발명은 이러한 문제점을 해결한 것이다. 예컨대, 종래의 표면탄성파(SAW) 필터는 단일 세라믹 패키지의 크기로 인해 칩사이즈패키지(CSP)로 가는데 상당히 어려운이 있었지만 본 발명에 따라 댐(82)을 사용하면 웨이퍼 표면에 있는 회로를 보호하면서도 패키지의 크기를 칩사이즈로 줄일 수 있다.As such, the method of the present invention using the dam 82 is a method of raising and cutting several chips directly on a matrix board 71 such as ceramic, LTCC, HTCC, PCB, lead frame, etc., thereby increasing the efficiency of mass production and packaging. Can reduce the price. That is, when using a ceramic package has to work one by one, and cover the package lid, there is a problem that the efficiency of mass production is low, but the present invention solves this problem. For example, conventional surface acoustic wave (SAW) filters have been quite difficult to get to chip size packages (CSPs) due to the size of a single ceramic package, but the dam 82 according to the present invention allows the package to protect the circuits on the wafer surface while The size of can be reduced to the chip size.
플립칩 접합공정(S5)은 골드 스터드 범프된 칩(11)을 댐이 형성된 매트릭스 보드(71)에 초음파를 이용하여 접착하는 공정이다. 특히, 본 발명에 따른 플립칩 접착공정(S5)에서는 도 9에 도시된 바와 같이, 매트릭스 보드(71)에 히팅수단을 통해 열을 가하고 칩(11)에는 툴에 의해 초음파와 압력을 가해 범프(13)로 사용된 도전체가 열(heat), 초음파(Ultra sonic), 및 압력(Pressure)에 의해 발생된 에너지로 칩(11)과 매트릭스 보드(71)를 부가적인 접착물질 없이도 전기적으로 연결해준다. 이와 같이 본 발명에서는 기존의 열압착 플립칩 공법과 달리 열압착과 동시에 초음파를 가해줌으로써 종래보다 공정시간을 단축할 수 있는 잇점이 있다.The flip chip bonding step S5 is a step of bonding the gold stud bumped chip 11 to the matrix board 71 having the dam by using ultrasonic waves. In particular, in the flip chip bonding process S5 according to the present invention, as shown in FIG. 9, heat is applied to the matrix board 71 through a heating means, and ultrasonic waves and pressure are applied to the chip 11 by a tool to bump ( The conductor used in FIG. 13 electrically connects the chip 11 and the matrix board 71 without the need for additional adhesive material by energy generated by heat, ultra sonic, and pressure. Thus, in the present invention, unlike the conventional thermocompression flip chip method, by applying ultrasonic waves at the same time as the thermocompression method, there is an advantage that the process time can be shorter than the conventional method.
도 9를 참조하면, 매트릭스 보드(71)의 칩이 장착될 영역에는 댐(82)이 형성되어 있고, 이 댐(82)안에 칩을 초음파와 열, 압력을 인가하면서 접착하면 칩(11)이 접촉됨과 동시에 댐(82)이 매트릭스 보드(72)의 접촉공간을 채워 오물질이 접촉공간으로 침투하는 것을 방지할 수 있다.Referring to FIG. 9, a dam 82 is formed in an area where a chip of the matrix board 71 is to be mounted, and when the chip is bonded while applying ultrasonic waves, heat, and pressure to the dam 82, the chip 11 is formed. Simultaneously with the contact, the dam 82 may fill the contact space of the matrix board 72 to prevent infiltrating dirt into the contact space.
이와 같이 플립칩 접착이 끝난 후 커링 공정에서 댐을 경화시킨다(S6). 커링 공정(S6)은 도 10에 도시된 바와 같이, 매트릭스 보드(71) 위에 칩(11)을 본딩한 후 연질의 댐(82)을 고온으로 가열하여 단단하게 경화시키는 것이다.As such, after the flip chip bonding is completed, the dam is cured in the curing process (S6). Curing process (S6), as shown in Figure 10, after bonding the chip 11 on the matrix board 71, the soft dam 82 is heated to a high temperature to harden.
커링공정을 통해 댐(82)이 경화되면, 몰딩 공정(S7)에서 디스펜서(91)를 이용하여 몰딩한다. 이러한 몰딩 공정은 선택적인 공정으로서 경우에 따라서는 몰딩하지 않고 댐이 경화된 후 바로 다이 커팅하여 개별소자로 분리할 수도 있다. 도 11은 몰딩공정에서 디스펜서를 이용하여 몰딩 콤파운드로 전체 칩을 몰딩한 것을 나타낸다.When the dam 82 is cured through the curing process, the dam 82 is molded using the dispenser 91 in the molding process S7. This molding process is an optional process, and in some cases, may be die-cut and separated into individual elements immediately after the dam is cured without molding. 11 illustrates molding the entire chip into molding compound using a dispenser in the molding process.
이어, 몰딩공정을 거칠 경우 디스펜서(91)에 의해 몰딩 콤파운드(92)로 웨이퍼 전체를 몰딩한 후, 다이싱 공정과 같이 각 칩을 절단하여 도 12에 도시된 바와 같이 개별소자로 분리한다(S8). Subsequently, when the molding process is performed, the entire wafer is molded with the molding compound 92 by the dispenser 91, and then each chip is cut as in the dicing process and separated into individual devices as shown in FIG. 12 (S8). ).
이상에서 설명한 바와 같이, 본 발명에 따르면 플립칩 본딩을 함에 있어서 열압착에 초음파를 부가하여 공정을 신속하게 처리할 수 있고, 특히 매트릭스 보드에 댐을 형성한 후 칩을 본딩하고 댐을 경화시킨 후 개별소자로 분리함으로써 웨이퍼상의 회로가 오염되는 것을 방지함과 아울러 대량생산의 효율성이 향상되는 효과가 있다.As described above, according to the present invention, in the case of flip chip bonding, ultrasonic waves may be added to thermocompression to rapidly process the process. In particular, after forming a dam on the matrix board, bonding the chips and curing the dam Separation into individual devices prevents the circuits on the wafer from being contaminated and improves the efficiency of mass production.
도 1은 일반적인 플립칩 본딩을 설명하기 위해 도시한 도면,1 is a view illustrating a general flip chip bonding;
도 2a는 패키지 타입 플립칩 본딩의 예,2A is an example of a package type flip chip bonding,
도 2b는 온보드 타입 플립칩 본딩의 예,2B is an example of onboard type flip chip bonding,
도 3은 본 발명에 따른 댐을 이용한 플립칩 패키징 방법을 도시한 순서도,3 is a flowchart illustrating a flip chip packaging method using a dam according to the present invention;
도 4는 도 3에 도시된 스터드 범프 형성의 예,4 is an example of the stud bump formation shown in FIG.
도 5는 도 3에 도시된 테이프 접착의 예,5 is an example of the adhesive tape shown in FIG.
도 6a,b는 도 3에 도시된 웨이퍼 절단 공정의 예,6A and 6B show examples of the wafer cutting process shown in FIG.
도 7은 본 발명에 따라 칩이 장착될 리드 프레임의 예,7 is an example of a lead frame in which a chip is mounted according to the present invention;
도 8은 도 3에 도시된 댐 형성 공정의 예,8 is an example of the dam forming process shown in FIG.
도 9는 도 3에 도시된 플립칩 본딩 공정의 예,9 is an example of the flip chip bonding process shown in FIG.
도 10은 도 3에 도시된 댐 경화 공정의 예,10 is an example of the dam hardening process shown in FIG.
도 11은 도 3에 도시된 몰딩 공정의 예,11 is an example of the molding process shown in FIG.
도 12는 도 3에 도시된 패키지별 분리공정의 예.12 is an example of a separation process for each package shown in FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10: 웨이퍼 11: 칩(다이)10: wafer 11: chip (die)
12: 본딩 패드 13: 스터드 범프12: Bonding Pad 13: Stud Bump
20: 기판 21,72: 리드패드20: substrate 21,72: lead pad
22: 세라믹 패키지 23: 패키지 뚜껑22: ceramic package 23: package lid
25: 메인보드 52: 접착 테이프25: motherboard 52: adhesive tape
71: 리드 프레임 82: 댐71: lead frame 82: dam
91: 디스펜서 92: 몰딩재료91: dispenser 92: molding material
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0018592A KR100499328B1 (en) | 2003-03-25 | 2003-03-25 | Flip Chip Packaging Method using Dam |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0018592A KR100499328B1 (en) | 2003-03-25 | 2003-03-25 | Flip Chip Packaging Method using Dam |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040083898A KR20040083898A (en) | 2004-10-06 |
| KR100499328B1 true KR100499328B1 (en) | 2005-07-04 |
Family
ID=37367541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2003-0018592A KR100499328B1 (en) | 2003-03-25 | 2003-03-25 | Flip Chip Packaging Method using Dam |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100499328B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140121113A (en) | 2013-04-05 | 2014-10-15 | 엘지이노텍 주식회사 | Ultrasonic bonding apparatus for Camera module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101131351B1 (en) * | 2009-10-06 | 2012-04-04 | 삼성전기주식회사 | Substrate Strip |
-
2003
- 2003-03-25 KR KR10-2003-0018592A patent/KR100499328B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140121113A (en) | 2013-04-05 | 2014-10-15 | 엘지이노텍 주식회사 | Ultrasonic bonding apparatus for Camera module |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040083898A (en) | 2004-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6191487B1 (en) | Semiconductor and flip chip packages and method having a back-side connection | |
| US7205178B2 (en) | Land grid array packaged device and method of forming same | |
| JP3420057B2 (en) | Resin-sealed semiconductor device | |
| JP4633740B2 (en) | Flip-chip QFN package and method therefor | |
| US7160755B2 (en) | Method of forming a substrateless semiconductor package | |
| US6689640B1 (en) | Chip scale pin array | |
| US6777265B2 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
| US6737300B2 (en) | Chip scale package and manufacturing method | |
| US7871865B2 (en) | Stress free package and laminate-based isolator package | |
| US5923958A (en) | Method for semiconductor chip packaging | |
| JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
| US20030203539A1 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
| KR101119708B1 (en) | Land grid array packaged device and method of forming same | |
| US20090039506A1 (en) | Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof | |
| US20060163714A1 (en) | Package structure and fabrication method thereof | |
| US6339253B1 (en) | Semiconductor package | |
| US10930604B2 (en) | Ultra-thin multichip power devices | |
| KR100499328B1 (en) | Flip Chip Packaging Method using Dam | |
| US20070281397A1 (en) | Method of forming semiconductor packaged device | |
| US7579680B2 (en) | Packaging system for semiconductor devices | |
| KR20080074468A (en) | Surface mounting method of semi-conduct chip using the ultrasonic wave | |
| KR20080086178A (en) | Method of manufacturing stack package | |
| US20050178815A1 (en) | Method for preparing integrated circuit modules for attachment to printed circuit substrates | |
| JP2004055609A (en) | Method of resin sealing | |
| KR100529710B1 (en) | Flip Chip Packaging Method and LED Packaging Structure using thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |