KR960000221B1 - Semiconductor package - Google Patents

Abstract

an unidirectional conducting layer which electrically conducts only updown direction and is adhesive to one side of the internal leads; a semiconductor chip where a bonding pads electrically conducts with the internal leads by being adhering on the unidirectional conducting layer; a package body which protects the internal lead and the semiconductor chip by enveloping them.

Description

Semiconductor package

1 is a cross-sectional view of a semiconductor package according to the prior art.

2 is a schematic diagram illustrating a chip-on-board process according to the prior art.

3 is a cross-sectional view of the anisotropic conductive layer used in the method of FIG.

4 is a cross-sectional view of a state in which a semiconductor chip is mounted by the method of FIG.

5 is a cross-sectional view of a semiconductor package mounted on a printed circuit board using an anisotropic conductive layer according to the prior art.

6 is a cross-sectional view of one embodiment of a semiconductor package according to the present invention.

FIG. 7 is a plan view of a semiconductor chip mounted on the lead frame for semiconductor package of FIG.

8 is a partially enlarged cross-sectional view of FIG.

9 is a cross-sectional view of another embodiment of a semiconductor package according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to an anisotropic conductive layer in a lead-on-chip type semiconductor package in which a semiconductor chip is directly mounted on the leads. The present invention relates to a semiconductor package which can be thinned and bonded to each other in a simple manufacturing process.

In general, semiconductor chips are packaged and mounted on a printed circuit board (hereinafter, referred to as a PCB). In the general type of the semiconductor package, a semiconductor chip is mounted on a rectangular die pad serving as a heat sink for heat dissipation, and leads of metal rods are arranged at a predetermined interval around the die pad. One side of the leads is connected to the semiconductor chip and the gold wire, and the package body is formed of an encapsulation resin to surround and protect the semiconductor chip and the gold wire.

Recently, the size of the semiconductor chip itself is gradually increased according to the trend of high integration of the semiconductor chip, but the size of the semiconductor package used as a product is internationally standardized and is gradually becoming smaller. Therefore, the thickness of the package body is becoming thinner because the semiconductor chip, which is increased in size, needs to be sealed in the compact package body. In addition, the number of leads as input / output terminals has increased according to the trend of higher integration, and semiconductor packages of more than 260 pins are currently produced, and the leads are gradually pitched to become metal thin films. The design and production of semiconductor packages is becoming increasingly finer, requiring more precise equipment and new production methods. In addition, since the general resin-encapsulated semiconductor package structure has a limitation in reducing the thickness and size of the package body, a LOC method for directly mounting a semiconductor chip on a lead without a die pad for mounting a highly integrated semiconductor chip, or a semiconductor chip. The LOC method, which mounts directly on the PCB, is also used.

1 is a cross-sectional view of a conventional semiconductor package 10, which is an example of an LOC type.

Leads 12 that are input / output terminals are arranged at regular intervals, and bus bars 15 are formed inside the leads 12. The semiconductor chip 14 is attached to the inner means 11 and one side of the leads 12 and the lower part of the bus bar 15 to an adhesive means 17, for example, an adhesive or a polyimide tape having adhesiveness on both sides. It is implemented by Bonding pads (not shown) of the semiconductor chip 14 and the inner lead 11 are connected to the gold wire 16 by a wire bonding method, and surround the semiconductor chip 14 and the gold wire 16 to be protected. The package body 18 is formed of an epoxy molding compound (hereinafter referred to as EMC) by a conventional molding process, and the external leads 13, which are the other sides of the leads 12, are formed on the package body ( It protrudes in all directions of 18), and it is bent in a shape suitable for mounting, for example, a wing shape.

The general wire bonding process can be largely divided into an ultrasonic bonding method using an oscillation of ultrasonic waves or a thermo compresion method using heat, and an integrated circuit semiconductor chip is a semiconductor chip damaged or a wire disconnection. The thermocompression method which produces little and is easy to work is mainly used.

Looking at the thermal compression method in detail as follows.

First, the die-attached lead frame is mounted on a heater block and heated to a temperature of about 190 to 300 ° C., and then a wire ball is formed with an electric spark at the end of the gold wire mounted on the wire bonding capillary, Primary bonding is performed to compress the wire ball onto a bonding pad of the semiconductor chip. Then, the gold wire is extended on the inner lead by a looping operation of the capillary, and then second bonding is performed by stitch bonding to compress the other side of the gold wire to the inner lead.

The conventional LOC type semiconductor package has the following problems due to the effect of fine pitch due to high integration.

First, the semiconductor package manufacturing process is performed through various steps such as die attach process, wire bonding process, molding process, and trim process for removing unnecessary lead frame parts such as dam bars. In the wire bonding process, the gold wire is disconnected due to mechanical pressure or chemical action, cracks occur in the semiconductor chip, and during the molding process, a sweeping phenomenon in which the fine gold wire is pushed to one side due to the inflow pressure of EMC occurs. Short circuits or short circuits between leads occur.

Second, according to the trend of miniaturization and thinning of semiconductor products, for example, memory modules, semiconductor packages are also thinned, and thinner such as thin small out line package (TSOP) etc. Although the package is manufactured, there is a limit to the thinning and high-density packaging of the semiconductor package because of the height occupied by the gold wire.

Third, the LOC type semiconductor package is incompatible by using a center pad chip in which bonding pads are formed in the center of the chip due to the limitation of the length of the bonding wire.

In order to solve these problems, a flip chip type chip on board method of directly mounting a semiconductor chip on a PCB has been used. The flip chip method is a bare chip mounting method in which solder bumps are formed on pads of a semiconductor chip to be directly melt-bonded on a metal wiring of a PCB in a face down form, and high density mounting is possible. Since the semiconductor package forming process such as wire bonding and molding is not performed, the manufacturing process is precise but there are few steps. In addition, as well as the center pad chip, the bonding pads can be mounted on a conventional semiconductor chip formed in both the periphery and the center portion of the chip has excellent advantages, such as excellent compatibility, thinness and high density mounting is possible. However, there is a problem that the semiconductor chip and the bump are expensive, and the pitch between the connection pins is restricted.

In order to solve this problem, flip chip technology using an anisotropic conductive layer in which micro bumps are formed on a polyimide film at a predetermined pitch instead of solder bumps has been developed.

As an example of such a technique, a semiconductor chip using an anisotropic conductive layer disclosed in Japan's Sumitomo Metal Industry Co., Ltd., "High Density Micro Film Connector" (Nov. 1992, Electronic Materials, pp. 27-35) And a method of mounting a semiconductor package in detail with reference to FIGS. 2 through 5.

Pads 26 are formed on one side of the PCB 20 on which one or more metal wires 22 are formed so as to correspond to bonding pads (not shown) of the semiconductor chip 24. The vertical interconnection sheet (VIS) 27 made of an anisotropic conductive layer electrically conducting only up and down on the wafers) and the semiconductor chip 24, and then bonded by thermocompression bonding (FIG. 4). Reference). The vertically connected sheet 27 is formed with a predetermined pitch of conductive layers 27b which are micro bumps penetrating the polyimide film 27a of a predetermined thickness up and down (see FIG. 3). The conductive layer 27b is a conductive material such as gold (Au), and is formed by an electroplating method, and electrically connects the pads 26 corresponding to the bonding pads, and the remaining conductive layer 27b is insulated. have.

The bare chip mounting using the anisotropic conductive layer does not form expensive bumps, but the manufacturing cost is high. However, the pitch between the connecting pins can be made fine, it can be applied to long sides of about 100 ~ 300mm length, and it can realize low contact resistance, low inductance, etc. It is used in limited areas such as connections of thermal print heads. However, as in the case of other flip chips, it is a method of mounting by melting the metal, so it is impossible to rework replacing the defective semiconductor chip by testing the mounted semiconductor chip, and the entire product such as the memory module has to be treated badly. There is a problem such as falling. In addition, there are various problems in mounting all the semiconductor chips by the COB method.

As well as the bare chip mounting using the anisotropic conductive layer, as shown in FIG. 5, the method of mounting on the PCB 40 using the anisotropic conductive layer 47 in the state of the semiconductor package 30 Also used.

The semiconductor package 30 is a LOC type in which the semiconductor chip 34 is mounted below the internal lead 32, and the semiconductor chip 34 and the internal leads 32 are connected by gold wires 36. . The outer leads 33 protruding to the outside of the package body 38 surrounding and protecting the semiconductor chip 34 and the gold wire 36 are bent in a gull shape. The external leads 33 are adhered to a pad 46 connected to a metal wiring (not shown) formed on the PCB 40, and the upper and lower leads are interposed between the external leads 33 and the pad 46. The anisotropic conductive layer 47 which is electrically conductive only in the direction is interposed and bonded by the thermocompression bonding method.

The method of mounting the semiconductor package on the PCB using the anisotropic conductive layer has a simple mounting process. However, there is a problem that it is difficult to rework the defective semiconductor package, and the thickness of the semiconductor package itself is limited, which makes it difficult to thin the semiconductor product.

The present invention is to solve the above problems, an object of the present invention in the LOC type semiconductor package in which the semiconductor chip is mounted on the lead, the semiconductor package can be made thin by bonding the semiconductor chip to the anisotropic conductive layer, manufacturing The process is to provide a simple semiconductor package.

A feature of the semiconductor package according to the present invention for achieving the above objects is a lead formed of a predetermined interval and consisting of internal and external leads, and a LOC in which a semiconductor chip is mounted on one side of the internal leads. A semiconductor package comprising: An anisotropic conductive layer bonded to one side of the inner leads and electrically conducting only in the vertical direction; A semiconductor chip adhered to the anisotropic conductive layer, the bonding pad being electrically connected to the inner lead; The package is provided with a package body surrounding and protecting the inner lead and the semiconductor chip.

Hereinafter, preferred embodiments of the semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

6 to 8 are diagrams for describing the semiconductor package 50 according to the present invention, which will be described in association with each other.

In the lead frame 60 for the semiconductor package 50 according to the present invention, the leads 52 formed at predetermined intervals are composed of internal and external leads 51 and 53, and the internal leads 51 A bus bar 55 is formed so as to protrude from the four corners of the field and to be connected to each other and supported (see FIG. 7).

A rectangular anisotropic conductive layer 57 is electrically connected to the lower portions of the inner lead 51 and the bus bar 55 only in the vertical direction, and a bonding pad 59 is attached to the lower portion of the anisotropic conductive layer 57. Are mounted on the peripheral portion of the chip. The inner leads 51 and the bonding pads 59 are electrically connected to each other by an anisotropic conductive layer 57 interposed therebetween to surround and protect the semiconductor chip 54 and the inner leads 51. The package body 58 is formed of EMC. The outer leads 53 protruding to the outside of the package body 58 are bent into a shape that can be easily mounted on a PCB (not shown), for example, a gull wing shape.

As shown in FIG. 7, the bus bar 55 is connected to power input / output pads Vcc and Vss, and the internal leads 51 are connected to data lines.

As shown in FIG. 8, the anisotropic conductive layer 57 is formed in a matrix shape at a predetermined pitch on the polyimide film 57a having a predetermined thickness of an insulating material and the polyimide film 57a. The holes (not shown) and the conductive layer 57b filling the holes are formed by an electroplating method with a conductive material such as gold (Au). The conductive layer 57b is a micro bump, and bumps 57c are formed in a predetermined shape, for example, a hemispherical shape, for smooth electrical and mechanical contact with the semiconductor chip 54 and the inner lead 51 at upper and lower portions thereof. The size of each portion of the anisotropic conductive layer 57 is appropriately formed in consideration of the size of the semiconductor chip 54 and the bonding pad 59 to be mounted and the pitch and size of the internal leads 51. Specifically, for example, the thickness of the polyimide film 57a is about 4 to 10 µm, the diameter of the hole formed in the polyimide film 57a is 5 to 90 µm, and the pitch of the conductive layer 57b is The height of the bump 57c which protrudes above and below the conductive layer 57b at least 40 micrometers is formed in the magnitude | size of 3-4 micrometers or more.

Since the anisotropic conductive layer 57 contacts a plurality of conductive layers 57b to one bonding pad 59, reliability of electrical contact is improved, and the conductive layer 57b of the remaining part that does not participate in electrical contact is The electrical short is not generated because the semiconductor chip 54 is in contact with the insulating protective layer.

Looking at the manufacturing process of the semiconductor package 50 according to the present invention in detail.

First, the anisotropic conductive layer 57 and the internal lead 51 and the bus bar 55 in the state of the lead frame 60 are aligned and placed on the bonding pads 59 of the semiconductor chip 54 in order. Then, the inner lead 51 and the bus bar 55 are compressed using a thermocompressor, and at the same time, a predetermined heat, for example, about 120 ° C., is applied to both sides of the conductive layer 57b. 51 and the bus bar 55 are bonded to each other by bonding the bonding pads 59 with each other. Then, heat treatment is performed at about 200-250 ° C. to relieve stress in the thermocompression process, followed by molding to form the package body 58, and unnecessary parts of the lead frame 60, for example Dam bars, side rails, and the like that interconnect the leads are removed by trimming, and the external leads 53 are bent to complete the semiconductor.

9 is a cross-sectional view of another embodiment of a semiconductor package 70 according to the present invention, which is an example of a stack package.

First and second semiconductor chips 74a and (1) on the upper and lower side surfaces of the inner lead 71, which is one side of the leads 72 formed at regular intervals, and the bus bars 75 connected to support each other, respectively. 74b) is mounted by the thermocompression bonding method via the anisotropic electrically conductive insect 77 which electrically conducts only in an up-down direction. The first and second semiconductor chips 74a and 74b are memory chips for performing the same operation and are mirror chips in which bonding pads (not shown) are formed to be replaced with each other. The package body 78 is formed of EMC to surround and protect the first and second semiconductor chips 74a and 74b, the inner lead 71 and the bus bar 75, and the package body 78 The outer leads 73 protruding to the outside of the are bent into a shape suitable for mounting, for example, a J shape.

Only the case of the conductive layer which filled the hole in which the anisotropic conductive layer is arrange | positioned at the matrix shape which has a fixed pitch in the polyimide film was mentioned as the example. Although not shown, the anisotropic conductive layer is a dispersed type anisotropic conductive insect in which powders of conductive materials such as gold (Au) are closely distributed (hereinafter referred to as "dispersion type") in various kinds, for example, inside an elastic insulating rubber layer. Alternatively, the zebra-type anisotropic conductive layer in which the longitudinal metal thin films are placed on the insulating rubber layer at regular intervals (hereinafter, referred to as zebra type) may be moved. The dispersed anisotropic conductive layer is electrically conductive up and down only in a portion where the conductive material powder is pressed under pressure, and in the zebra type, only a portion in contact with the lead is electrically connected to each other by the metal thin film.

As described above, according to the semiconductor package according to the present invention, in the LOC type semiconductor package in which the semiconductor chip is mounted on one side of the lead, the anisotropic conductive layer is electrically connected to the semiconductor chip only in the vertical direction. Since it was carried out by a thermocompression method, the manufacturing process of the semiconductor package is simpler than the wire bonding method using a conventional gold wire, and since the gold wire itself is not necessary, no defect occurs due to wire sweeping during molding, and the thickness of the anisotropic conductive layer is increased. Since it is thin, the semiconductor package can be thinned. In addition, in the case of thinned leads used for highly integrated semiconductor packages, anisotropic conductive layers are bonded to one side of the leads, thereby preventing lead short circuits due to inflow pressure of the molding resin during the molding process. In addition, since one bonding pad is connected to the lead and bus bars by a plurality of conductive layers of the anisotropic conductive layer, there is an effect of improving reliability of electrical contact. In addition, since the laminated package can be easily manufactured using a mirror chip, there is a side effect of improving the mounting density.

Claims (6)

A lead-on-chip semiconductor package formed at regular intervals and composed of internal and external leads and mounted on a semiconductor chip on one side of the internal leads; An anisotropic conductive layer bonded to one side of the inner leads and electrically conducting only in the vertical direction; A semiconductor chip adhered to the anisotropic conductive layer, the bonding pad being electrically connected to the internal lead; And a package body surrounding and protecting the inner lead and the semiconductor chip. The semiconductor package of claim 1, wherein a bus bar is further formed on a portion of the inner lead that is not overlapped with the semiconductor chip and is electrically connected to the semiconductor chip. The semiconductor package according to claim 1, wherein the anisotropic conductive filler is composed of a conductive layer filling holes formed in a matrix shape at regular intervals in the polyimide film. 4. The semiconductor package according to claim 3, wherein a semispherical bump is formed on the upper and lower sides of the conductive layer so as to facilitate contact with the bonding pads and the internal leads of the semiconductor chip. The semiconductor package according to claim 1 or 2, wherein the anisotropic conductive layer is one of a dispersed type and a zebra type. The semiconductor package according to claim 1 or 2, wherein first and second semiconductor chips, which are mirror chips, are stacked on both side surfaces of the inner leads, respectively, via an anisotropic conductive layer.