KR950002001A - Semiconductor package - Google Patents

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Publication number
KR950002001A
KR950002001A KR1019930011668A KR930011668A KR950002001A KR 950002001 A KR950002001 A KR 950002001A KR 1019930011668 A KR1019930011668 A KR 1019930011668A KR 930011668 A KR930011668 A KR 930011668A KR 950002001 A KR950002001 A KR 950002001A
Authority
KR
South Korea
Prior art keywords
conductive layer
leads
anisotropic conductive
semiconductor package
semiconductor
Prior art date
Application number
KR1019930011668A
Other languages
Korean (ko)
Other versions
KR960000221B1 (en
Inventor
정도수
송병석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930011668A priority Critical patent/KR960000221B1/en
Publication of KR950002001A publication Critical patent/KR950002001A/en
Application granted granted Critical
Publication of KR960000221B1 publication Critical patent/KR960000221B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

이 발명은 반도체 칩과 리드들을 이방성 도전층으로 접착시키는 반도체 패키지에 관한 것으로서, 리드들의 일측면에 반도체 칩이 실장되는 LOC형 반도체 패키지에서, 반도체 칩과 리드의 접착을 상하방향으로만 전기적으로 도통되는 이방성 도전층을 개재시킨 후 열압착 방법으로 실시하였으므로, 종래 금선을 이용한 와이어 본딩 방법에 비해 반도체 패키지의 제조 공정이 간단하며, 금선 자체가 필요 없으므로 몰딩시의 와이어 스위핑에 의한 불량 발생이 없고, 이방성 도전층의 두께가 얇으므로 반도체 패키지의 박형화가 가능하다. 또한 고집적화된 반도체 패키지에 사용되는 박막화된 리드들의 경우 리드들의 일측이 이방성 도전층과 접착되어 지지되므로, 몰딩 공정시 몰딩 수지의 유입 유입에 의한 리드 단락을 방지할 수 있다. 또한 하나의 본딩 패드가 이방성 도전층의 다수개의 도전층에 의해 리드 및 버스바와 연결되므로 전기적 접촉의 신뢰성을 향상시킬 수 있으며, 미러칩을 이용하여 적층 패키지를 용이하게 제작할 수 있어 실장밀도를 향상시킬수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for adhering semiconductor chips and leads to an anisotropic conductive layer. In a LOC type semiconductor package in which semiconductor chips are mounted on one side of the leads, the electrical contact between the semiconductor chips and the leads is conducted only in the vertical direction. Since the thermal anisotropic conductive layer is interposed therebetween, the manufacturing process of the semiconductor package is simpler than the conventional wire bonding method using gold wires, and since no gold wires are required, there is no defect caused by wire sweeping during molding. Since the thickness of the anisotropic conductive layer is thin, the semiconductor package can be thinned. In addition, in the case of thinned leads used for highly integrated semiconductor packages, one side of the leads may be bonded to and supported by the anisotropic conductive layer, thereby preventing lead short circuits due to inflow and inflow of the molding resin during the molding process. In addition, since one bonding pad is connected to the leads and busbars by a plurality of conductive layers of the anisotropic conductive layer, the reliability of electrical contact can be improved, and the stacking package can be easily manufactured using a mirror chip to improve the mounting density. have.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 이 발명에 따른 반도체 패키지의 일 실시예의 단면도, 제7도는 제6도의 반도체 패키지용 리드프레임에 반도체 칩이 실장된 상태의 평면도, 제8도는 제6도의 일부 확대 단면도이다.FIG. 6 is a sectional view of an embodiment of a semiconductor package according to the present invention, FIG. 7 is a plan view of a semiconductor chip mounted on a lead frame for a semiconductor package of FIG. 6, and FIG. 8 is a partially enlarged sectional view of FIG.

Claims (6)

일정간격으로 형성되어 있으며 내부 및 외부 리드로 구성되어 있으며 리드들과, 상기 내부 리드들의 일측면에 반도체 칩이 실장되어 있는 리드－온－칩형 반도체 패키지에 있어서; 상기 내부 리드들의 일측면에 접착되어 있으며, 상하 방향으로만 전기적으로 도통시키는 이방성 도전층과, 상기 이방성 도전층 상에 접착되어, 본딩 패드가 내부 리드와 전기적으로 도통되는 반도체 칩과; 상기 내부 리드 및 반도체 칩을 감싸 보호하는 패키지 몸체를 구비하여 되는 반도체 패키지.In the lead-on-chip semiconductor package formed of a predetermined interval and composed of internal and external leads, and the semiconductor chip is mounted on one side of the internal leads; An anisotropic conductive layer adhered to one side of the inner leads and electrically conductive only in an up and down direction, and a semiconductor chip adhered on the anisotropic conductive layer so that a bonding pad is electrically connected to the inner lead; And a package body surrounding and protecting the inner lead and the semiconductor chip. 제1항에 있어서, 상기 내부 리드들과 중첩되지 않는 부분에 버스바가 추가로 형성되어 상기 반도체칩과 접착되며, 전기적으로도 연결되는 반도체 패키지.The semiconductor package of claim 1, wherein a bus bar is further formed at a portion that does not overlap the internal leads to be bonded to the semiconductor chip and electrically connected to the semiconductor chip. 제1항에 있어서, 상기 이방성 도전층이 폴리 이미드 필름에 일정간격으로 메트릭스 형상으로 형성되어 있는 홀을 메꾸는 도전층으로 구성되어 있는 반도체 패키지.The semiconductor package according to claim 1, wherein the anisotropic conductive layer is formed of a conductive layer that fills holes formed in a matrix shape in a polyimide film at regular intervals. 제3항에 있어서, 상기 도전층의 상측 밑 하측에 반도체 칩의 본딩 패드 및 내부 리드와의 접촉을 원활히하기 위하여 반구 형상의 범프가 형성되어 있는 이방성 도전층을 사용하는 반도체 패키지.The semiconductor package according to claim 3, wherein an anisotropic conductive layer having a hemispherical bump is formed in order to facilitate contact with the bonding pads and the internal leads of the semiconductor chip above and below the conductive layer. 제1항 또는 제2항에 있어서, 상기 이방성 도전층이 분산형 및 제브라형중 어느 하나인 반도체 패키지.The semiconductor package according to claim 1 or 2, wherein the anisotropic conductive layer is one of a dispersed type and a zebra type. 제1항 또는 제2항에 있어서, 상기 내부 리드들의 양측면에 서로 미러 칩인 제1 및 제2반도체 칩이 각각 이방성 도전층을 개재시켜 적층되어 실장되는 반도체 패키지.The semiconductor package according to claim 1 or 2, wherein first and second semiconductor chips, which are mirror chips, are stacked on both side surfaces of the inner leads, respectively, via an anisotropic conductive layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930011668A 1993-06-25 1993-06-25 Semiconductor package KR960000221B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930011668A KR960000221B1 (en) 1993-06-25 1993-06-25 Semiconductor package

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Application Number Priority Date Filing Date Title
KR1019930011668A KR960000221B1 (en) 1993-06-25 1993-06-25 Semiconductor package

Publications (2)

Publication Number Publication Date
KR950002001A true KR950002001A (en) 1995-01-04
KR960000221B1 KR960000221B1 (en) 1996-01-03

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990000204A (en) * 1997-06-03 1999-01-15 윤종용 Connection method of bonding pad and internal lead of semiconductor chip by adhesive means and LOC type semiconductor chip package using same
US9805769B2 (en) 2014-07-09 2017-10-31 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US9899075B2 (en) 2014-07-09 2018-02-20 Samsung Electronics Co., Ltd. Multi channel semiconductor device having multi dies and operation method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990000204A (en) * 1997-06-03 1999-01-15 윤종용 Connection method of bonding pad and internal lead of semiconductor chip by adhesive means and LOC type semiconductor chip package using same
US9805769B2 (en) 2014-07-09 2017-10-31 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US9899075B2 (en) 2014-07-09 2018-02-20 Samsung Electronics Co., Ltd. Multi channel semiconductor device having multi dies and operation method thereof
US10418087B2 (en) 2014-07-09 2019-09-17 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US10734059B2 (en) 2014-07-09 2020-08-04 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US10971208B2 (en) 2014-07-09 2021-04-06 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US11328760B2 (en) 2014-07-09 2022-05-10 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US11417386B2 (en) 2014-07-09 2022-08-16 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same
US11443794B2 (en) 2014-07-09 2022-09-13 Samsung Electronics Co., Ltd. Multi channel semiconductor device having multi dies and operation method thereof
US11721391B2 (en) 2014-07-09 2023-08-08 Samsung Electronics Co., Ltd. Multi channel semiconductor device having multi dies and operation method thereof
US11837273B2 (en) 2014-07-09 2023-12-05 Samsung Electronics Co., Ltd. Semiconductor device having interconnection in package and method for manufacturing the same

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Publication number Publication date
KR960000221B1 (en) 1996-01-03

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