JPS6370532A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6370532A
JPS6370532A JP61213854A JP21385486A JPS6370532A JP S6370532 A JPS6370532 A JP S6370532A JP 61213854 A JP61213854 A JP 61213854A JP 21385486 A JP21385486 A JP 21385486A JP S6370532 A JPS6370532 A JP S6370532A
Authority
JP
Japan
Prior art keywords
pellet
resin
pellets
bonding
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61213854A
Other languages
Japanese (ja)
Inventor
Katsuhiro Tabata
田畑　克弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61213854A priority Critical patent/JPS6370532A/en
Publication of JPS6370532A publication Critical patent/JPS6370532A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To realize compact and high density packages by resin sealing process by a method wherein two step semiconductor pellets are laminated on a leadframe while respective pellets and leads of the leadframe are connected to one another by bonding wires. CONSTITUTION:Two step pellets 3, 4 are laminated on a tab of lead-frame 1 and then the second step pellet 4 is bonded onto the first step pellet 3 using a conductive resin bonding agent. At this time, if the conduction between the first step pellet 3 and the second step pellet 4 is not reuired, a non-conductive resin bonding agent may be applicable. Bonding pads 8 of the first pellet 3 and leads 7 are connected to one another by bonding wires 5 while the other bonding pads 9 of the second pellet 4 and the leads 7 are connected to one another by the other bonding wires 6. Finally, after finishing the wire bonding process, element assemblies are filled in a metallic mold so that transfer molding process may be performed using resin such as epoxy resin or silicon resin etc. to manufacture DIL plastic packages.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、詳しくは半導体ペレットの
大型化に伴なうバクケージング技術の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly, to an improvement in backcaging technology as semiconductor pellets become larger.

〔従来の技術〕[Conventional technology]

従来の半導体装置にあっては、実装基体上にマウントす
る半導体ペレット（以下単にペレットとい５）は一つで
ある。例えば、デエアル・イン・ライン（ＤＩＬ）プラ
スチックパッケージにあっては、多連のリードフレーム
上にペレットをマウントし、ワイヤポンディングした後
に、モールド金星に入れて樹脂でトランスファモールド
し、個別に切断分離する方法がとられるが、切断分離後
の各パッケージ内には−のペレットがマウントされ収納
されている。In a conventional semiconductor device, only one semiconductor pellet (hereinafter simply referred to as pellet 5) is mounted on a mounting substrate. For example, in the case of deal-in-line (DIL) plastic packages, pellets are mounted on multiple lead frames, wire bonded, placed in mold Venus, transfer molded with resin, and individually cut and separated. However, after cutting and separation, - pellets are mounted and stored in each package.

なお、半導体パッケージのパッケージング技術について
述べた文献の例としては、１９８０年１月１５日（株）
工業１Ｉ４ｆ会発行「ＩＣ化実装技術」ｐ１３５〜１５
６があげられる。An example of a document describing packaging technology for semiconductor packages is January 15, 1980,
"IC Mounting Technology" published by Industrial 1I4F Association p135-15
6 can be given.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかるに、半導体集積回路装置における集積度の増大に
伴ない、ペレットは増々犬型化する傾向にある。ペレッ
トサイズが大きくなっても、それに相応してパッケージ
を大きくすることはできない。すなわち、パッケージに
はＭＩＬ規格などの規格があり、また、小型高密度実装
はパッケージ使用者のニーズでもある。However, as the degree of integration in semiconductor integrated circuit devices increases, pellets tend to become more dog-shaped. As the pellet size increases, the package cannot be correspondingly increased. That is, there are standards such as the MIL standard for packages, and compact, high-density packaging is also a need of package users.

七のため、ペレットサイズの大型化に伴ない、パッケー
ジ強度が劣化する傾向にあり、当該強度をになう、樹脂
封止部の当該樹脂を工夫するなどの対策が施されている
。Therefore, as the pellet size increases, the package strength tends to deteriorate, and countermeasures are being taken to improve the strength and improve the resin of the resin sealing part.

本発明は、かかる技術的背景の下、小型高密度＊装を実
現できる技術を提供することを目的とする。Against this technical background, the present invention aims to provide a technology that can realize compact, high-density* equipment.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および絡付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

本腰において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed herein is as follows.

丁なわち、本発明においては、複数のペレットを多段に
マウントするようにした。That is, in the present invention, a plurality of pellets are mounted in multiple stages.

〔作　用〕[For production]

このように、複数のペレットを多段にマウントすること
により、例えばペレットサイズが２倍となった場合には
、平面的にみて、ペレットが占めるパッケージ内での占
有ｉａ（床面積）が２倍となり、樹脂封止部における樹
脂層厚みが１／２となり、パッケージ強度が低下するが
、本発明では例えば２段にペレットを積層することによ
り、平面的にみたペレットの占有面４積を上記に比して
小さくすることができ、同一パッケージ内において、実
装密度を向上させ、小形高密度実装を笑風できる。In this way, by mounting multiple pellets in multiple stages, for example, if the pellet size doubles, the ia (floor area) occupied by the pellets within the package will double from a two-dimensional perspective. , the thickness of the resin layer in the resin sealing part becomes 1/2, and the package strength decreases, but in the present invention, for example, by stacking the pellets in two layers, the area occupied by the pellets in plan view is reduced by 4 areas compared to the above. It is possible to improve the packaging density within the same package, making compact and high-density packaging possible.

〔実施例〕〔Example〕

次に、本発明を図面に示す実施例に基づいて説明する。 Next, the present invention will be explained based on embodiments shown in the drawings.

実施例１゜ 第１図は本発明の実施例を示す樹脂封止型半導体装置の
構成断面図で、同図に示すように、リードフレーム（１
）のタブ（２）上に、二段にペレット（３）。Embodiment 1 FIG. 1 is a cross-sectional view of the structure of a resin-sealed semiconductor device showing an embodiment of the present invention.
) Pellet (3) in two tiers on the tab (2).

（４）を積み重ねる。当該各ペレット＋３１　、　（４
１について、それぞれボンディング用ワイヤ（５１、（
６１により、リードフレーム（１）のリード（７）と、
ワイヤボンディングする。Stack (4). Each pellet +31, (4
1, bonding wires (51, (
61, the lead (7) of the lead frame (1) and
Wire bonding.

第１段ペレット（３）や第２段ペレット（４）の取着は
、各種の方法により行なうことができ、例えば、第２段
ペレット（４）を第１段ペレット（３）に貼着するに、
導電性樹脂接着剤を用いて行なうことができる。Attachment of the first stage pellets (3) and the second stage pellets (4) can be carried out by various methods, for example, attaching the second stage pellets (4) to the first stage pellets (3). To,
This can be done using a conductive resin adhesive.

その具体例としては、Ａｇ粉を含むエポキシ樹脂系接着
剤ペースト（Ａｇペースト）により行なうことができ、
これら第１段ペレット（３）と第２段ペレット（４）と
の間に導通なとる必要のない場合には、非導電性の樹脂
接着剤などにより貼着するようにしてもよい。また、こ
れらを絶縁するために、第１段ペレット（３）と第２段
ペレット＋４１との当接面に絶縁層（図示せず）を介在
させてもよい。As a specific example, it can be performed using an epoxy resin adhesive paste (Ag paste) containing Ag powder,
If it is not necessary to establish electrical continuity between the first pellet (3) and the second pellet (4), they may be attached using a non-conductive resin adhesive or the like. Further, in order to insulate them, an insulating layer (not shown) may be interposed between the contact surfaces of the first stage pellet (3) and the second stage pellet +41.

第２図には、第１段ペレット（３）のボンデイングパク
ド部（８）とリード（力とのワイヤボンディングおよび
第２段ペレット（４１のポンディングパッド部（９）と
リード（７）とのワイヤボンディングを、平面的にかつ
模式的に示しである。Figure 2 shows wire bonding between the bonding pad part (8) of the first stage pellet (3) and the lead (force), and the bonding pad part (9) of the second stage pellet (41) and the lead (7). This is a plan view and schematic diagram of wire bonding.

かかるワイヤボンディング後に、当該素子組立品をモー
ルド金型に入れ、エポキシ樹脂やシリコン樹脂などの樹
脂により、トランスファーモールドを行ない、かかる主
要工程を経て、ＤＩＬのプラスチックパッケージを得る
。After such wire bonding, the element assembly is placed in a mold and transfer molded using a resin such as epoxy resin or silicone resin, and through these main steps, a DIL plastic package is obtained.

第３図は当該樹脂封止泣半導体装置の外観図の一例を示
す。FIG. 3 shows an example of an external view of the resin-sealed semiconductor device.

第１図および第３図にて、αＱは樹脂封止部である。In FIGS. 1 and 3, αQ is a resin sealing portion.

実施例２゜ 第４図は本発明の他の実施例を示す半導体装置の構成断
面図である。Embodiment 2 FIG. 4 is a cross-sectional view of the structure of a semiconductor device showing another embodiment of the present invention.

セラミック基板ａυのキャビティ（１３内に、第１段ペ
レット（３）を固着し、さらに、１２ｆｔ第１段ペレッ
ト（３１の上に、第２段ペレット（４１を貼着する。A first stage pellet (3) is fixed in the cavity (13) of the ceramic substrate aυ, and a second stage pellet (41) is further adhered on top of the 12ft first stage pellet (31).

セラミック基板Ｃ１１ｌの多段に′ｍ成された導体部α
３゜α荀と、第１段ペレット（３）と第２段ペレット（
４１とをそれぞれボンディング用ワイヤ（５１、＋６１
により、ワイヤボンディングする。Conductor portion α formed in multiple stages on ceramic substrate C11l
3゜α, 1st stage pellet (3) and 2nd stage pellet (
41 and bonding wires (51, +61
Wire bonding is performed.

当該導体部（１３、α４は、セラミック基板（１１１の
裏面に垂設されたリードピンα９と導通がとられている
。The conductor portion (13, α4) is electrically connected to a lead pin α9 vertically provided on the back surface of the ceramic substrate (111).

セラミック基板（１１１上には、キャップ傾を取着し、
ハーメチックシールを行なう。A cap tilt is attached on the ceramic substrate (111),
Perform hermetic sealing.

これら実施例において、第１段ペレット（３）および第
２段ペレット（４）は、それぞれ、例えばシリコン単結
晶基板から成り、周知の技術によってこれらペレット（
チップ）内には多数の回路素子が形成され、１つの回路
機能が与えられている。回路素子の具体例は、例えばＭ
ＯＳ）ランジスタから放り、これらの回路素子によって
、例えば論理回路およびメモリの回路機能が形成されて
いる。In these examples, the first stage pellet (3) and the second stage pellet (4) are each made of, for example, a silicon single crystal substrate, and these pellets (
A large number of circuit elements are formed within the chip (chip) and are provided with one circuit function. A specific example of the circuit element is, for example, M
OS) Apart from the transistors, these circuit elements form the circuit functions of, for example, logic circuits and memories.

リードフレーム（１）は、例えばＮｉ−Ｆｅ系合金やＣ
ｕ系合金により構成され、従来公知のリードフレームを
使用することができる。ボンディング用ワイヤ（５１、
（６１は、それぞれ例えばＡ〕線により構成される。The lead frame (1) is made of, for example, Ni-Fe alloy or C.
A conventionally known lead frame made of a U-based alloy can be used. Bonding wire (51,
(61 are each constituted by, for example, an A] line.

本発明によれば、このように、第１段ペレット（３）の
上に、第２段ペレット（４１を積み重ねるようにしたの
で、仮に、このようにベレッ）　（３１、（４１を積み
重ねずに、第１段ペレット（３）のサイズを大きくして
そのままパッケージングしたときには、平面的にみて、
その占有面積が大となり、樹脂封止部αｅの当該ペレッ
ト（３）との間隔も狭くならざるを得ず、白該樹脂封止
部α１の強度を劣化させてしま５が、本発明によれば、
同一サイズのパッケージにおいて、平面的にみて、ベレ
ン）　＋３１　、　［４１の占有面積（床面積）が上記
に比して小さくなり、したがって小形高密度実装化を実
現できた。According to the present invention, as described above, the second stage pellets (41) are stacked on top of the first stage pellets (3). , when the size of the first stage pellet (3) is increased and packaged as it is, when viewed from above,
The area occupied by the resin sealing part αe becomes large, and the distance between the resin sealing part αe and the pellet (3) also becomes narrow, which deteriorates the strength of the resin sealing part α1. Ba,
In a package of the same size, the occupied area (floor area) of Belen) +31 and [41 is smaller than the above when viewed from above, and therefore compact and high-density packaging can be realized.

第４図に示すような実施例において、ペレットサイズが
大となり、キャビティＱ３余裕がなくなってきた場合に
も非常に有利である。The embodiment shown in FIG. 4 is very advantageous even when the pellet size becomes large and there is no room for the cavity Q3.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範囲で種々変更可
能であることは−・５までもない。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples (although various changes can be made without departing from the gist of the invention).・Not even 5.

例えば、前記実施例ではペレットを二段に積み重ねる例
を示したが、三段以上であってもよい。For example, in the embodiment described above, the pellets are stacked in two layers, but the pellets may be stacked in three or more layers.

また、実装基体の例として、リードフレームやセラミッ
ク基板を示したが、他のものでも差支えなＸ、′１゜ 以上の説明では主としく本発明者によってなされた発明
をその背景となった利用分野であるＤｒＬプラスチック
パッケージやピングリットアレイセラミックパッケージ
に適用した場合について説明したが、それに限定される
ものではなく、他の各種半導体装置にも適用できる。In addition, although a lead frame and a ceramic substrate are shown as examples of the mounting substrate, other materials may also be used. Although the case where the present invention is applied to DrL plastic packages and pin-grit array ceramic packages, which are in the field, has been described, the present invention is not limited thereto, and can be applied to various other semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

本発明によれば、ペレットサイズが大型化しても、小形
高密度実装化を実現できた。According to the present invention, even if the pellet size increases, compact and high-density packaging can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示ｊ樹脂封止型半導体装置の
構成断面図。 第２図は本発明の実施例な示す要部説明平面図、第３図
は本発明の実施例を示す樹脂封止屋半導体装置の斜視図
、 第４囚は本発明の他の実施例を示す構成断面図である。 １・・・リードフレーム、２・・・タブ、３・・・ペレ
ット（第１段）、４・・・ペレット（第２段）、５・・
・ボンディング用ワイヤ、６・・・ボンディング用ワイ
ヤ、７・・・リード、８・・・ボンディング用パッド部
、９・・・ボンディング用パッド部、１０・・・樹脂封
止部、１１・・・セラミック基板、１２・・・キャビテ
ィ、１３・・・導体部、１４・・・導体部、１５・・・
リードビン、１６・・・キャップ。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention. Fig. 2 is a plan view illustrating the main parts of an embodiment of the present invention, Fig. 3 is a perspective view of a resin molded semiconductor device showing an embodiment of the present invention, and Fig. 4 shows another embodiment of the present invention. FIG. 1... Lead frame, 2... Tab, 3... Pellet (first stage), 4... Pellet (second stage), 5...
- Bonding wire, 6... Bonding wire, 7... Lead, 8... Bonding pad part, 9... Bonding pad part, 10... Resin sealing part, 11... Ceramic substrate, 12... Cavity, 13... Conductor portion, 14... Conductor portion, 15...
Lead bin, 16...cap.

Claims (1)

【特許請求の範囲】 １、実装基体上に複数の半導体ペレットを積層して成る
ことを特徴とする半導体装置。 ２、半導体装置が樹脂封止型半導体装置で、リードフレ
ーム上に半導体ペレットを二段に積層し、各ペレットと
前記リードフレームのリードとをボンディング用ワイヤ
により接続し、樹脂封止を行なって成る、特許請求の範
囲第１項記載の半導体装置。[Claims] 1. A semiconductor device comprising a plurality of semiconductor pellets stacked on a mounting substrate. 2. The semiconductor device is a resin-sealed semiconductor device, in which semiconductor pellets are stacked in two stages on a lead frame, each pellet is connected to the lead of the lead frame with a bonding wire, and resin-sealed. , a semiconductor device according to claim 1.
JP61213854A 1986-09-12 1986-09-12 Semiconductor device Pending JPS6370532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61213854A JPS6370532A (en) 1986-09-12 1986-09-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61213854A JPS6370532A (en) 1986-09-12 1986-09-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6370532A true JPS6370532A (en) 1988-03-30

Family

ID=16646119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61213854A Pending JPS6370532A (en) 1986-09-12 1986-09-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6370532A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287635A (en) * 1988-09-26 1990-03-28 Nec Corp Ceramic package semiconductor device
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5448121A (en) * 1992-11-30 1995-09-05 Fuji Xerox Co., Ltd. Pneumatic and magnetic bearing type motor
US5710470A (en) * 1991-04-04 1998-01-20 Ebara Corporation Hydrodynamic bearing assembly
US5874793A (en) * 1995-06-02 1999-02-23 Ibiden Co., Ltd. High speed rotor assembly
JP2022174198A (en) * 2018-03-02 2022-11-22 ローム株式会社 Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287635A (en) * 1988-09-26 1990-03-28 Nec Corp Ceramic package semiconductor device
US5710470A (en) * 1991-04-04 1998-01-20 Ebara Corporation Hydrodynamic bearing assembly
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5495398A (en) * 1992-05-22 1996-02-27 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5502289A (en) * 1992-05-22 1996-03-26 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5448121A (en) * 1992-11-30 1995-09-05 Fuji Xerox Co., Ltd. Pneumatic and magnetic bearing type motor
US5874793A (en) * 1995-06-02 1999-02-23 Ibiden Co., Ltd. High speed rotor assembly
JP2022174198A (en) * 2018-03-02 2022-11-22 ローム株式会社 Semiconductor device

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