KR100618541B1 - Method for fabricating multi-chip semiconductor package - Google Patents

Method for fabricating multi-chip semiconductor package Download PDF

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KR100618541B1
KR100618541B1 KR1019990027018A KR19990027018A KR100618541B1 KR 100618541 B1 KR100618541 B1 KR 100618541B1 KR 1019990027018 A KR1019990027018 A KR 1019990027018A KR 19990027018 A KR19990027018 A KR 19990027018A KR 100618541 B1 KR100618541 B1 KR 100618541B1
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semiconductor chip
wire
bonding
semiconductor
multilayer
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KR1019990027018A
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Korean (ko)
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KR20010008926A (en
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정일규
강선원
권대훈
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 크기 및 본딩 패드의 위치가 동일한 2개 이상의 반도체 칩을 적층하여 패키지한 다층 반도체 칩 패키지 제작 방법에 관한 것으로, 본 발명에 의하면 동일한 크기를 갖는 적어도 2 개 이상의 반도체 칩중 어느 하나의 반도체 칩의 본딩 패드와 인너 리드를 와이어 본딩한 후, 와이어 본딩된 반도체 칩의 상면으로부터 와이어가 노출되지 않도록 비전도성 접착물질을 도포한 다음 반도체 칩의 상면에 또다른 반도체 칩을 안착시킨 후, 상부에 위치한 반도체 칩과 리드 프레임의 해당 인너 리드를 와이어 본더에 의하여 와이어 본딩함으로써 그 크기를 최소화할 수 있으며, 반도체 패키지의 성능 및 집적도가 크게 향상된다. The present invention relates to a method for fabricating a multilayer semiconductor chip package in which two or more semiconductor chips having the same size and the position of bonding pads are stacked and packaged. According to the present invention, at least one semiconductor chip of at least two semiconductor chips having the same size is provided. After the wire bonding of the bonding pad and the inner lead, the non-conductive adhesive material is applied so that the wire is not exposed from the upper surface of the wire bonded semiconductor chip, and then another semiconductor chip is placed on the upper surface of the semiconductor chip, By wire-bonding the inner lead of the semiconductor chip and the lead frame by a wire bonder, the size thereof can be minimized, and the performance and integration of the semiconductor package are greatly improved.

Description

다층 반도체 칩 패키지 제작 방법{Method for fabricating multi-chip semiconductor package}Method for fabricating multi-chip semiconductor package

도 1은 종래 다층 반도체 칩 패키지의 몰드를 제거한 상태의 사시도.1 is a perspective view of a state in which a mold of a conventional multilayer semiconductor chip package is removed.

도 2는 종래 다층 반도체 칩 패키지의 다른 일례를 도시한 개념도.2 is a conceptual diagram illustrating another example of a conventional multilayer semiconductor chip package.

도 3은 본 발명에 의한 다층 반도체 칩 패키지의 몰드를 제거한 상태의 사시도.3 is a perspective view of a state in which a mold of the multilayer semiconductor chip package according to the present invention is removed.

도 4는 도 3의 B-B 단면도.4 is a cross-sectional view taken along line B-B in FIG.

도 5는 본 발명에 의한 다층 반도체 칩 패키지의 제작 과정의 일실시예를 도시한 설명도.5 is an explanatory diagram showing an embodiment of a manufacturing process of a multilayer semiconductor chip package according to the present invention;

도 6은 본 발명에 의한 다층 반도체 칩 패키지의 다른 실시예를 도시한 설명도.6 is an explanatory diagram showing another embodiment of the multilayer semiconductor chip package according to the present invention;

본 발명은 다층 반도체 칩 패키지 제작 방법에 관한 것으로 특히, 크기 및 본딩 패드의 위치가 동일한 2개 이상의 반도체 칩을 적층하여 패키지로 제작한 다층 반도체 칩 패키지 제작 방법에 관한 것이다.The present invention relates to a method for fabricating a multilayer semiconductor chip package, and more particularly, to a method for fabricating a multilayer semiconductor chip package manufactured by stacking two or more semiconductor chips having the same size and location of bonding pads in a package.

최근, 전자 및 정보기기의 다기능화, 고속화 및 대용량화에 대응하고 메모리 모듈의 실장밀도를 향상시켜 전자 및 정보기기를 소형화시키기 위해서 여러개의 반도체 패키지를 수직 또는 수평으로 적층시킨 적층형 반도체 패키지가 개발되고 있다.Recently, multilayer semiconductor packages have been developed in which a plurality of semiconductor packages are stacked vertically or horizontally in order to miniaturize electronic and information devices by coping with multifunction, high speed, and large capacity of electronic and information devices, and improving the mounting density of memory modules. .

다른 한편으로, 하나의 패키지에 복수개의 반도체 칩을 실장한 후, 반도체 칩과 리드 프레임을 와이어 본딩함으로써 반도체 패키지의 용량을 대형화하거나 처리 속도를 빠르게 하는 다층 반도체 칩 패키지가 개발되고 있다.On the other hand, after mounting a plurality of semiconductor chips in one package, a multilayer semiconductor chip package has been developed that increases the capacity of the semiconductor package or increases the processing speed by wire bonding the semiconductor chip and the lead frame.

도 1에는 다층 반도체 칩 패키지(100)의 일례가 도시되어 있는 바, 도 1은 다층 반도체 칩 패키지(100)의 몰드 부분을 제거한 후 반도체 칩(10,20)과 리드 프레임(40) 및 반도체 칩(10,20)과 리드 프레임(40)을 전기적으로 연결하는 와이어(50)의 사시도가 도시되고 있다.An example of the multilayer semiconductor chip package 100 is illustrated in FIG. 1, and FIG. 1 shows the semiconductor chips 10 and 20, the lead frame 40, and the semiconductor chip after removing the mold portion of the multilayer semiconductor chip package 100. A perspective view of a wire 50 electrically connecting the 10 and 20 and the lead frame 40 is shown.

이때, 다층 반도체 칩 패키지(100)중 하부에 위치한 반도체 칩(10)은 반드시 상부에 위치한 반도체 칩(20)보다 크기가 커야만 하는데, 이는 하부에 위치한 반도체 칩(10)과 리드 프레임(40)이 와이어 본딩되기 위해서는 필연적으로 최소 이격 거리 W를 필요로 하기 때문이다.At this time, the semiconductor chip 10 located at the bottom of the multilayer semiconductor chip package 100 must be larger than the semiconductor chip 20 located at the top, which is the semiconductor chip 10 and the lead frame 40 located at the bottom. This is because the wire bonding inevitably requires a minimum separation distance W.

이와 같은 최소 이격 거리 W에 의하여 동일한 크기를 갖는 2 개의 반도체 칩을 겹쳐서 다층 반도체 칩 패키지를 제작하는데 많은 어려움이 있음으로 주로 하부 반도체 칩(10)으로 칩 크기가 비교적 큰 메모리 반도체 칩을 사용하고, 상부 반도체 칩(20)으로 칩 크기가 비교적 작은 비 메모리 반도체 칩을 사용하여 다층 반도체 칩 패키지(100)를 제작한다.Since there are many difficulties in fabricating a multilayer semiconductor chip package by overlapping two semiconductor chips having the same size by such a minimum separation distance W, a memory semiconductor chip having a relatively large chip size is used as the lower semiconductor chip 10. The multilayer semiconductor chip package 100 is manufactured by using a non-memory semiconductor chip having a relatively small chip size as the upper semiconductor chip 20.

도 2에는 다층 반도체 칩 패키지(200)의 다른 일례가 도시되어 있는 바, 도 2의 다층 반도체 칩 패키지(200)는 크기가 동일한 2 개의 반도체 칩(110,120)의 후면이 서로 마주보도록 위치시킨 후, 외부를 향하고 있는 반도체 칩(110,120)의 본딩 패드(115,125)에 리드 프레임(130)의 인너 리드(133)를 안착시킨 상태로 접속하여 2 개의 반도체 칩(110,120)으로 이루어진 다층 반도체 칩 패키지(200)를 제작한 것이 도시되어 있다.FIG. 2 illustrates another example of the multilayer semiconductor chip package 200. In the multilayer semiconductor chip package 200 of FIG. 2, the back surfaces of two semiconductor chips 110 and 120 having the same size are positioned to face each other. The multilayer semiconductor chip package 200 including two semiconductor chips 110 and 120 by connecting the inner leads 133 of the lead frame 130 to the bonding pads 115 and 125 of the semiconductor chips 110 and 120 facing outside. It is shown that produced.

그러나, 도 1의 일례에 따르면 동일한 크기를 갖는 반도체 칩 예를 들면, 비 메모리 반도체 칩 2 개 이상, 메모리 반도체 칩 2 개 이상을 앞서 언급하였듯이 와이어 본딩 과정에서의 어려움으로 인하여 다층으로 제작하는데 많은 어려움이 있다.However, according to the example of FIG. 1, as described above, two or more non-memory semiconductor chips and two or more non-memory semiconductor chips having the same size may be difficult to manufacture in a multilayer due to the difficulty in the wire bonding process. There is this.

또한, 이와 같은 문제점을 극복 가능한 도 2의 일례에 의하면 동일한 크기를 갖는 반도체 칩 2 개(110,120)를 다층 반도체 칩 패키지(200)로 제작하는 것이 가능하지만, 이 경우 단지 크기가 동일한 2 개의 반도체 칩(110,120)만을 다층 반도체 칩 패키지(200)로 제작하는 것이 가능하고, 3 개 이상의 다층 반도체 칩을 다층으로 적층하여 다층 반도체 칩 패키지(200)를 제작하기 위해서는 또다른 방법을 강구해야 하는 어려움이 있다.In addition, according to the example of FIG. 2 capable of overcoming such a problem, it is possible to manufacture two semiconductor chips 110 and 120 having the same size as the multilayer semiconductor chip package 200, but in this case, only two semiconductor chips having the same size are used. It is possible to fabricate only (110, 120) as the multilayer semiconductor chip package 200, and in order to fabricate the multilayer semiconductor chip package 200 by stacking three or more multilayer semiconductor chips in a multilayer, there is a difficulty in finding another method. .

따라서, 본 발명은 이와 같은 종래 문제점을 감안한 것으로써, 본 발명의 목적은 크기 및 본딩 패드의 위치가 동일한 동일 종류의 반도체 칩을 적어도 2 개 이상 다층으로 적층할 수 있는 다층 반도체 칩의 제작 방법을 제공함에 있다. Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a method for manufacturing a multilayer semiconductor chip capable of stacking at least two or more semiconductor chips of the same type having the same size and the position of the bonding pads. In providing.                         

본 발명의 다른 목적은 후술될 본 발명의 상세한 설명에서 보다 명확해질 것이다.Other objects of the present invention will become more apparent from the following detailed description of the invention.

이와 같은 본 발명의 목적을 달성하기 위한 다층 반도체 칩 패키지는 다이 패드, 인너 리드, 아웃터 리드로 구성된 리드 프레임의 다이 패드에 반도체 칩을 접착하고, 반도체 칩의 본딩 패드와 인너 리드를 와이어 본딩한 후, 반도체 칩의 상면에 위치한 와이어가 노출되지 않도록 반도체 칩의 상면에 비전도성 접착물질을 도포하고, 비전도성 접착물질의 상면에 다른 반도체 칩을 접착한 후, 다른 반도체 칩의 본딩 패드와 인너 리드를 와이어 본딩하고, 반도체 칩 및 리드 프레임을 몰딩하여 제작한다.In order to achieve the object of the present invention, a multilayer semiconductor chip package may bond a semiconductor chip to a die pad of a lead frame including a die pad, an inner lead, and an outer lead, and wire bond the bonding pad and the inner lead of the semiconductor chip. The non-conductive adhesive material is applied to the upper surface of the semiconductor chip so that the wires located on the upper surface of the semiconductor chip are not exposed, the other semiconductor chip is attached to the upper surface of the non-conductive adhesive material, and then the bonding pads and the inner leads of the other semiconductor chip are Wire bonding is carried out, and a semiconductor chip and a lead frame are molded and produced.

이하, 본 발명에 의한 다층 반도체 칩 패키지의 제작 방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a multilayer semiconductor chip package according to the present invention will be described with reference to the accompanying drawings.

먼저, 도 3 또는 도 4에는 본 발명에 의한 제작 방법에 의하여 제작된 본 발명에 의한 다층 반도체 칩 패키지(300)의 사시도 및 단면도가 도시되어 있는 바, 도 3은 본 발명에 의한 다층 반도체 칩 패키지(300)의 몰드를 제거한 상태의 사시도이고, 도 4는 도 3의 B-B 단면도이다.First, Figure 3 or Figure 4 shows a perspective view and a cross-sectional view of the multilayer semiconductor chip package 300 according to the present invention produced by the manufacturing method according to the present invention, Figure 3 is a multilayer semiconductor chip package according to the present invention It is a perspective view of the state in which the mold of 300 was removed, and FIG. 4 is BB sectional drawing of FIG.

첨부된 도 3 또는 도 4를 참조하여, 본 발명에 의한 다층 반도체 칩 패키지(300)의 구성을 살펴보면, 다층 반도체 칩 패키지(300)는 일실시예로 인너 리드(213), 아웃터 리드(216) 및 다이 패드(219)로 구성된 리드 프레임(210), 다이 패드(219)에 접착제(220,도 4 참조)에 의하여 고정된 제 1 반도체 칩(230), 제 1 반도체 칩(230)의 본딩 패드와 리드 프레임(210)의 인너 리드(213)를 전기적으로 연결하는 제 1 와이어(240), 제 1 와이어(240)가 묻히도록 제 1 반도체 칩(230)의 상면에 도포되는 비전도성 접착물질(250), 제 1 와이어(240)와 쇼트되지 않도록 비전도성 접착물질(250)의 상면에 접착되는 제 2 반도체 칩(260), 제 2 반도체 칩(260)의 본딩 패드(265)와 리드 프레임(210)의 다른 인너 리드를 전기적으로 연결하는 제 2 와이어(270) 및 제 2 반도체 칩(260), 제 2 와이어(270) 및 인너 리드(213)를 감싸는 몰드 수지(280,가상선으로 도시)로 구성된다.Referring to the configuration of the multilayer semiconductor chip package 300 according to the present invention with reference to FIG. 3 or FIG. 4, the multilayer semiconductor chip package 300 may include an inner lead 213 and an outer lead 216. And a bonding pad of the first semiconductor chip 230 and the first semiconductor chip 230 fixed to the lead frame 210 including the die pad 219 and the die pad 219 by an adhesive 220 (see FIG. 4). And a non-conductive adhesive material applied to an upper surface of the first semiconductor chip 230 so that the first wire 240 and the first wire 240 are electrically connected to the inner lead 213 of the lead frame 210. 250, the second semiconductor chip 260 bonded to the top surface of the non-conductive adhesive material 250 so as not to short with the first wire 240, the bonding pad 265 and the lead frame of the second semiconductor chip 260 ( The second wire 270 and the second semiconductor chip 260, the second wire 270, and the inner lead 213 that electrically connect the other inner leads of the 210. ) And mold resin 280 (shown in phantom).

이와 같이 구성된 본 발명에 의한 다층 반도체 칩 패키지의 제작 방법을 첨부된 도 5를 참조하여 설명하면 다음과 같다.A method of fabricating a multilayer semiconductor chip package according to the present invention configured as described above will be described with reference to FIG. 5.

먼저, 도 5a에 도시된 바와 같이 리드 프레임(210)의 다이 패드(219)에 반도체 칩 제조 공정에 의하여 이미 제작된 제 1 반도체 칩(230)의 후면을 부착하기 위한 접착제(220)를 소정량 도포한다.First, as shown in FIG. 5A, a predetermined amount of adhesive 220 is attached to the die pad 219 of the lead frame 210 to attach the rear surface of the first semiconductor chip 230 manufactured by the semiconductor chip manufacturing process. Apply.

이후, 도 5b에 도시된 바와 같이 다이 패드(219)의 접착제(220)에 제 1 반도체 칩(230)의 후면을 안착한 후, 경화시키고 제 1 반도체 칩(230)의 에지(edge)에 형성된 본딩 패드(235)와 리드 프레임(210)의 인너 리드(213)를 와이어 본더에 의하여 와이어(240)로 본딩한다. 이때, 와이어(240)를 제 1 와이어라 칭하기로 한다.Thereafter, as shown in FIG. 5B, the rear surface of the first semiconductor chip 230 is seated on the adhesive 220 of the die pad 219, and then cured and bonded to the edge of the first semiconductor chip 230. The pad 235 and the inner lead 213 of the lead frame 210 are bonded to the wire 240 by a wire bonder. In this case, the wire 240 will be referred to as a first wire.

도 5b 공정에 의하여 제 1 반도체 칩(230)의 본딩 패드(235)와 인너 리드(213)가 와이어 본딩되면, 도 5c에 도시된 바와 같이 제 1 반도체 칩(230)의 상면에 비전도성 접착물질(250)을 도포한다.When the bonding pad 235 and the inner lead 213 of the first semiconductor chip 230 are wire bonded by the process of FIG. 5B, a non-conductive adhesive material is formed on the upper surface of the first semiconductor chip 230 as shown in FIG. 5C. 250 is applied.

이때, 비전도성 접착물질(250)의 두께는 매우 중요하다.At this time, the thickness of the non-conductive adhesive material 250 is very important.

비전도성 접착물질(250)은 제 1 반도체 칩(230)의 상면에 형성된 본딩 패드(235)에 접속된 제 1 와이어(240)가 노출되지 않을 정도로 두껍게 제 1 반도체 칩(230)의 상면에 도포한다.The non-conductive adhesive material 250 is applied to the top surface of the first semiconductor chip 230 so thick that the first wire 240 connected to the bonding pad 235 formed on the top surface of the first semiconductor chip 230 is not exposed. do.

이후, 도 5d에 도시된 바와 같이 비전도성 접착물질(250)의 상면에 제 2 반도체 칩(260)의 후면을 접착시킨다.Thereafter, as illustrated in FIG. 5D, the back surface of the second semiconductor chip 260 is adhered to the top surface of the nonconductive adhesive material 250.

이어서, 도 5e에 도시된 바와 같이 제 2 반도체 칩(260)의 상면에 형성된 본딩 패드(265)와 인너 리드(213)를 제 2 와이어(270)에 의하여 와이어 본딩한 후, 도 5f에 도시된 바와 같이 제 1 반도체 칩(230)-제 1 와이어(240)-비전도성 접착물질(250)-제 2 반도체 칩(260)-제 2 와이어(270) 및 리드 프레임(210)의 인너 리드(213)를 몰드 수지(280)로 몰딩한 후, 도시되지 않은 포밍/트리밍 공정 및 테스트 공정을 수행하여 다층 반도체 칩 패키지(300)를 제작한다.Subsequently, as shown in FIG. 5E, the bonding pad 265 and the inner lead 213 formed on the upper surface of the second semiconductor chip 260 are wire-bonded by the second wire 270, and then, as illustrated in FIG. 5F. As described above, the inner lead 213 of the first semiconductor chip 230-the first wire 240-the non-conductive adhesive material 250-the second semiconductor chip 260-the second wire 270 and the lead frame 210 is formed. ) Is molded into the mold resin 280, and then a forming / trimming process and a test process (not shown) are performed to fabricate the multilayer semiconductor chip package 300.

한편, 도 6에는 본 발명에 의한 다층 반도체 칩 패키지(400)의 다른 일실시예가 도시되어 있는 바, 도 6의 일실시예는 리드 프레임(310)의 다이 패드의 앞면, 뒷면에 모두 접착제(320)를 부착한 후, 2 개의 제 1, 제 2 반도체 칩(330,340)을 다이 어탯치하고, 제 1, 제 2 반도체 칩(330,340)의 본딩 패드(335,345)를 리드 프레임의 해당 인너 리드(313)에 제 1, 제 2 와이어(350,360)로 와이어 본딩한다.Meanwhile, another embodiment of the multilayer semiconductor chip package 400 according to the present invention is illustrated in FIG. 6. In one embodiment of FIG. 6, the adhesive 320 is applied to both the front and rear surfaces of the die pad of the lead frame 310. ) And die attach the two first and second semiconductor chips 330 and 340, and attach the bonding pads 335 and 345 of the first and second semiconductor chips 330 and 340 to the corresponding inner leads 313 of the lead frame. Wire bonding to the first and second wires (350,360).

이후, 제 1, 제 2 반도체 칩(330,340)의 상면에는 비전도성 접착물질(370)을 도포하되, 제 1, 제 2 와이어(350,360)가 비전도성 접착물질(370)의 외부로 돌출되지 않도록 도포한다.Subsequently, the non-conductive adhesive material 370 is coated on the upper surfaces of the first and second semiconductor chips 330 and 340, but the first and second wires 350 and 360 are not applied to the outside of the non-conductive adhesive material 370. do.

이어서, 비전도성 접착물질(370)의 상부에 제 3, 제 4 반도체 칩(380,390)을 접착하고, 제 3, 제 4 반도체 칩(380,390)의 상부에 형성된 본딩 패드(385,395)와 리드 프레임(310)의 해당 인너 리드(313)를 제 3, 제 4 와이어(396,397)로 와이어 본딩한다.Next, the third and fourth semiconductor chips 380 and 390 are adhered to the non-conductive adhesive material 370, and the bonding pads 385 and 395 and the lead frame 310 formed on the third and fourth semiconductor chips 380 and 390. The inner lead 313 of) is wire bonded to the third and fourth wires 396 and 397.

이후, 제 1, 제 2 반도체 칩(330,340)-제 1, 제 2 와이어(350,360)-비전도성 접착물질(370)-제 3, 제 4 반도체 칩(380,390)-제 3, 제 4 와이어(396,397)를 몰드 수지에 의하여 몰딩한 후, 트리밍/포밍 공정 및 테스트 공정을 거쳐 도 6에 도시된 다층 반도체 칩 패키지(400)가 제작된다.Thereafter, the first and second semiconductor chips 330 and 340-the first and second wires 350 and 360-the non-conductive adhesive material 370-the third and fourth semiconductor chips 380 and 390-the third and fourth wires 396 and 397 ) Is molded by a mold resin, and then the multilayer semiconductor chip package 400 shown in FIG. 6 is manufactured through a trimming / forming process and a test process.

본 발명에서는 바람직한 일실시예로 리드 프레임의 다이 패드의 일측면에 2 개의 반도체 칩 또는 다이 패드의 양측면에 4 개의 반도체 칩을 다층으로 적층한 것이 설명되고 있지만, 최근들어 반도체 칩의 두께가 점차 얇아지고 있는 추세로 볼때, 적어도 3 개 이상의 동일한 크기를 반도체 칩을 하나의 반도체 패키지에 다층으로 형성하는 것 또한 가능하다.In the present invention, a preferred embodiment is described in which two semiconductor chips are stacked on one side of a die pad of a lead frame or four semiconductor chips are stacked on both sides of a die pad. However, recently, the thickness of a semiconductor chip is gradually thinner. With the growing trend, it is also possible to form at least three or more identical sizes of semiconductor chips in one semiconductor package in multiple layers.

이상에서 상세하게 살펴본 바와 같이 동일한 크기를 갖는 적어도 2 개 이상의 반도체 칩중 어느 하나의 반도체 칩의 본딩 패드와 인너 리드를 와이어 본딩한 후, 와이어 본딩된 반도체 칩의 상면으로부터 와이어가 노출되지 않도록 비전도성 접착물질을 도포한 다음 반도체 칩의 상면에 또다른 반도체 칩을 안착시킨 후, 상부에 위치한 반도체 칩과 리드 프레임의 해당 인너 리드를 와이어 본더에 의하여 와이어 본딩함으로써 그 크기를 최소화할 수 있으며, 반도체 패키지의 성능 및 집적도가 크게 향상되는 효과가 있다.As described in detail above, after wire bonding the bonding pad and the inner lead of any one of the at least two semiconductor chips having the same size, the non-conductive adhesive may not be exposed from the upper surface of the wire bonded semiconductor chip. After applying the material and then placing another semiconductor chip on the upper surface of the semiconductor chip, the size of the semiconductor package can be minimized by wire bonding the upper lead of the semiconductor frame and the corresponding inner lead of the lead frame by a wire bonder. Performance and integration are greatly improved.

Claims (3)

다이 패드, 인너 리드, 아웃터 리드로 구성된 리드 프레임의 상기 다이 패드에 반도체 칩을 접착하는 단계와;Bonding a semiconductor chip to the die pad of a lead frame consisting of a die pad, an inner lead, and an outer lead; 상기 반도체 칩의 본딩 패드와 상기 인너 리드를 와이어 본딩하는 단계와;Wire bonding the bonding pad and the inner lead of the semiconductor chip; 상기 반도체 칩의 상면에 위치한 상기 와이어가 노출되지 않도록 상기 반도체 칩의 상면에 비전도성 접착물질을 도포하는 단계와;Applying a nonconductive adhesive to the upper surface of the semiconductor chip such that the wire located on the upper surface of the semiconductor chip is not exposed; 상기 비전도성 접착물질의 상면에 상기 반도체 칩과 동일한 크기를 갖는 다른 반도체 칩을 접착하는 단계와;Bonding another semiconductor chip having the same size as the semiconductor chip to an upper surface of the non-conductive adhesive material; 상기 다른 반도체 칩의 본딩 패드와 인너 리드를 와이어 본딩하는 단계와;Wire bonding a bonding pad and an inner lead of the another semiconductor chip; 상기 반도체 칩, 상기 리드 프레임을 몰딩하는 단계를 포함하는 다층 반도체 칩 제작 방법.And molding the semiconductor chip and the lead frame. 제 1 항에 있어서, 상기 반도체 칩은 적어도 3 개 이상으로, 상기 반도체 칩과 상기 반도체 칩의 사이에는 상기 비전도성 접착물질이 형성된 다층 반도체 칩 제작 방법.The method of claim 1, wherein at least three semiconductor chips are formed, and the nonconductive adhesive material is formed between the semiconductor chip and the semiconductor chip. 제 1 항에 있어서, 상기 반도체 칩은 상기 리드프레임의 상기 다이패드의 양면에 모두 형성된 다층 반도체 칩 제작 방법.The method of claim 1, wherein the semiconductor chip is formed on both surfaces of the die pad of the lead frame.
KR1019990027018A 1999-07-06 1999-07-06 Method for fabricating multi-chip semiconductor package KR100618541B1 (en)

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US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
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US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20040058478A1 (en) 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
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