KR20010061886A - Stack chip package - Google Patents
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- KR20010061886A KR20010061886A KR1019990064436A KR19990064436A KR20010061886A KR 20010061886 A KR20010061886 A KR 20010061886A KR 1019990064436 A KR1019990064436 A KR 1019990064436A KR 19990064436 A KR19990064436 A KR 19990064436A KR 20010061886 A KR20010061886 A KR 20010061886A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 복수의 반도체 칩이 리드프레임에 실장되어 전기적으로 연결됨으로써 단일 패키지로 구성되는적층 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package. More particularly, the present invention relates to a stacked chip package, in which a plurality of semiconductor chips are mounted on a lead frame and electrically connected to each other to form a single package.
최근의 반도체 산업 발전 그리고 사용자의 요구에 따라 전자 기기는 더욱 더 소형화 및 경량화가 요구되고 있다. 이에 주로 적용되는 기술중의 하나가 복수의 반도체 칩을 리드프레임에 탑재하여 하나의 패키지로 구성하는 멀티 칩 패키징(multi chip packaging) 기술이다.With the recent development of the semiconductor industry and the demands of users, electronic devices are increasingly required to be smaller and lighter. One of the technologies mainly applied thereto is a multi chip packaging technology in which a plurality of semiconductor chips are mounted in a lead frame and configured into one package.
멀티 칩 패키징(multi-chip packaging) 기술은 특히 소형화와 경량화가 요구되는 휴대용 전화기 등에서 실장면적의 축소와 경량화를 위해 많이 적용되고 있다. 예를 들어, 메모리 기능을 수행하는 플래시 메모리(flash memory) 소자와 에스램(SRAM; Synchronous RAM) 소자를 하나의 TSOP(Thin Small Outline Package)로 구성하면 각각의 반도체 소자를 내재하는 단위 반도체 칩 패키지 두 개를 이용하는 것보다 크기나 무게 및 실장면적에서 소형화와 경량화에 유리하다.Multi-chip packaging technology has been widely applied to reduce the mounting area and light weight, especially in portable telephones requiring miniaturization and light weight. For example, when a flash memory device and a synchronous RAM (SRAM) device that performs a memory function are configured into one thin small outline package (TSOP), a unit semiconductor chip package containing each semiconductor device is included. It is more advantageous for miniaturization and weight reduction in size, weight, and mounting area than using two.
일반적으로 두 개의 반도체 소자를 하나의 패키지 내에 구성하는 방법에는 두 개의 반도체 소자를 적층시키는 방법과 병렬로 배열시키는 방법이 있다. 전자의 경우 반도체 소자를 적층시키는 구조이므로 공정이 복잡하고 한정된 두께에서 안정된 공정을 확보하기 어려운 단점이 있고, 후자의 경우 평면상에 두 개의 반도체 칩을 배열시키는 구조이므로 크기 감소에 의한 소형화의 장점을 얻기가 어렵다. 보통 소형화와 경량화가 필요한 패키지에 적용되는 형태로서 반도체 소자를 적층시키는 형태가 많이 사용된다. 이와 같은 멀티 칩 패키징 기술이 적용된 형태의 반도체 칩 패키지를 적층 칩 패키지라 하며 그 예를 소개하면 다음과 같다.In general, a method of forming two semiconductor devices in one package includes a method of stacking two semiconductor devices and arranging them in parallel. The former has a disadvantage in that it is difficult to secure a stable process at a limited thickness due to the structure of stacking semiconductor elements. Difficult to obtain Usually, as a form applied to a package requiring miniaturization and weight reduction, a form in which semiconductor elements are stacked is frequently used. Such a semiconductor chip package to which the multi-chip packaging technology is applied is called a stacked chip package. An example thereof is as follows.
도 1은 종래 기술에 따른 적층 칩 패키지의 일 예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a stacked chip package according to the prior art.
도 1을 참조하면, 이 적층 칩 패키지(100)는 제 1반도체 칩(111)이 다이패드(121b)의 상면에 부착되어 있고, 그 제 1반도체 칩(111)의 상면에 다시 제 2반도체 칩(113)이 부착되어 있으며, 제 1반도체 칩(111)의 본딩패드(112)와 제 2반도체 칩(113)의 본딩패드(114)가 다이패드(121b)와 소정의 간격으로 이격되어 있는 리드(121a)의 내측 말단부에 본딩 와이어(125)로 와이어 본딩(wire bonding)되어 전기적인 연결을 이루고 있고, 외부환경으로부터의 보호를 위하여 에폭시 성형 수지(Epoxy Molding Compound)와 같은 플라스틱 봉지재로 패키지 몸체(127)가 형성되어 있는 구조이다. 여기서, 제 1반도체 칩(111)과 제 2반도체 칩(113)은 모두 본딩패드(112,114)가 형성되어 있지 않은 밑면이 부착에 이용된다. 이때 부착에 이용되는 접착수단(119)으로는 비전도성의 에폭시계 접착제가 이용되고 있다.Referring to FIG. 1, in the stacked chip package 100, a first semiconductor chip 111 is attached to an upper surface of a die pad 121b, and a second semiconductor chip is again attached to an upper surface of the first semiconductor chip 111. A lead 113 is attached and the bonding pad 112 of the first semiconductor chip 111 and the bonding pad 114 of the second semiconductor chip 113 are spaced apart from the die pad 121b at a predetermined interval. An electrical connection is made by wire bonding with the bonding wire 125 at the inner end of 121a, and the package body is made of a plastic encapsulant such as an epoxy molding compound for protection from the external environment. 127 is formed. Here, in the first semiconductor chip 111 and the second semiconductor chip 113, the bottom surfaces on which the bonding pads 112 and 114 are not formed are used for attachment. At this time, the non-conductive epoxy adhesive is used as the bonding means 119 used for the attachment.
이와 같은 종래의 적층 칩 패키지는 두 개의 반도체 칩을 내재하는 구조에는 적합하나 두 개 이상의 반도체 칩을 내재하도록 하는 구성에는 와이어 본딩에 대한 어려움이 있다. 특히, 칩 크기가 같을 경우에는 네 개 이상의 반도체 칩을 적층하기가 어려워 적층 칩 패키지 구현이 용이하지 않다.Such a conventional stacked chip package is suitable for a structure in which two semiconductor chips are embedded, but there is a difficulty in wire bonding in a configuration in which two or more semiconductor chips are embedded. In particular, when the chip size is the same, it is difficult to stack four or more semiconductor chips, which makes it difficult to implement a stacked chip package.
본 발명의 목적은 용량 및 집적도의 향상을 위하여 두 개 이상의 반도체 칩을 적층 형태로 패키징이 가능한 구조의 적층 칩 패키지를 제공하는 데 있다.Disclosure of Invention An object of the present invention is to provide a laminated chip package having a structure in which two or more semiconductor chips can be packaged in a stacked form in order to improve capacity and integration.
도 1은 종래 기술에 따른 적층 칩 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a stacked chip package according to the prior art;
도 2a는 본 발명에 따른 적층 칩 패키지의 일 실시예를 나타낸 단면도,Figure 2a is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention,
도 2b는 본 발명에 따른 적층 칩 패키지에 사용되는 리드프레임에 반도체 칩이 실장된 상태를 나타낸 평면도,2B is a plan view illustrating a semiconductor chip mounted on a lead frame used in a multilayer chip package according to the present invention;
도 3은 본 발명에 따른 적층 칩 패키지의 다른 실시예를 나타낸 단면도이다.3 is a cross-sectional view showing another embodiment of a stacked chip package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 적층 칩 패키지 11,13,15,17; 반도체 칩10; Stacked chip packages 11,13,15,17; Semiconductor chip
12,14,16,18; 본딩패드 19; 접착제12,14,16,18; Bonding pads 19; glue
20; 리드프레임 21a,22a; 리드20; Leadframes 21a and 22a; lead
21b,22b; 다이패드(die pad) 25; 본딩 와이어(bonding wire)21b, 22b; Die pad 25; Bonding wire
27; 패키지 몸체27; Package body
이와 같은 목적을 달성하기 위한 본 발명에 따른 적층 칩 패키지는, 칩 실장 영역과 리드를 갖는 리드프레임과, 상기 리드프레임의 칩 실장 영역에 실장되며 복수의 본딩패드가 형성된 적어도 2개 이상의 반도체 칩, 상기 본딩패드와 상기 리드를 전기적으로 연결시키는 본딩 와이어, 및 상기 반도체 칩과 상기 본딩 와이어 및 그 접합 부위를 봉지하는 패키지 몸체를 구비하는 적층 칩 패키지에 있어서, 상기 반도체 칩들은 상기 본딩패드가 활성면의 일측 가장자리에 형성되어 있으며,상기 반도체 칩들이 상기 본딩패드가 개방되도록 서로 빗겨 부착되어 적층된 형태를 가지며 상기 리드프레임의 칩 실장 영역에 실장되어 있는 것을 특징으로 한다.According to an aspect of the present invention, a stacked chip package includes a lead frame having a chip mounting area and a lead, at least two semiconductor chips mounted on the chip mounting area of the lead frame and having a plurality of bonding pads; A laminated chip package having a bonding wire for electrically connecting the bonding pad and the lead, and a package body encapsulating the semiconductor chip, the bonding wire, and a bonding portion thereof, wherein the semiconductor chips have an active surface. It is formed on one side edge of, The semiconductor chips are attached to each other so that the bonding pads are opened to be stacked and characterized in that it is mounted in the chip mounting region of the lead frame.
이하 첨부 도면을 참조하여 본 발명에 따른 적층 칩 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a multilayer chip package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a는 본 발명에 따른 적층 칩 패키지의 일 실시예를 나타낸 단면도이고, 도 2b는 본 발명에 따른 적층 칩 패키지에 사용되는 리드프레임에 반도체 칩이 실장된 상태를 나타낸 평면도이다.Figure 2a is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention, Figure 2b is a plan view showing a state in which a semiconductor chip is mounted on a lead frame used in the stacked chip package according to the present invention.
도 2a와 도 2b를 참조하면, 이 적층 칩 패키지(10)는 내부에 동일한 크기를 갖는 4개의 반도체 칩들(11,13,15,17)이 내장되어 있다. 이때 반도체 칩들은 모두 본딩패드들(12,14,16,18)이 집적회로가 형성된 활성면의 일측 가장자리에 형성되어 있는 형태의 것이다.2A and 2B, the multilayer chip package 10 includes four semiconductor chips 11, 13, 15, and 17 having the same size therein. In this case, all of the semiconductor chips are formed in which bonding pads 12, 14, 16, and 18 are formed at one edge of an active surface on which an integrated circuit is formed.
제 1반도체 칩(11)의 활성면 반대면인 밑면이 칩 실장 영역으로서의 상부 다이패드(21b)에 부착되어 있고, 제 1반도체 칩(11)의 본딩패드(12)가 개방되도록 제 1반도체 칩(11)의 활성면에 제 2반도체 칩(13)의 밑면이 부착되어 있다. 그리고, 하부 다이패드(22b)에 제 3반도체 칩(15)의 밑면이 부착되어 있고, 그 제 3반도체 칩(15)의 본딩패드(16)가 개방되도록 제 4반도체 칩(17)이 부착되어 있다. 한편,제 2반도체 칩(13)과 제 4반도체 칩(17)은 본딩패드들(14,18)이 개방되도록 활성면이 서로 부착되어 있다.A bottom surface opposite to the active surface of the first semiconductor chip 11 is attached to the upper die pad 21b as the chip mounting area, and the first semiconductor chip is opened so that the bonding pad 12 of the first semiconductor chip 11 is opened. The bottom surface of the second semiconductor chip 13 is attached to the active surface of (11). The bottom surface of the third semiconductor chip 15 is attached to the lower die pad 22b, and the fourth semiconductor chip 17 is attached so that the bonding pad 16 of the third semiconductor chip 15 is opened. have. On the other hand, the second semiconductor chip 13 and the fourth semiconductor chip 17 have active surfaces attached to each other such that the bonding pads 14 and 18 are opened.
제 1내지 제 4반도체 칩들(11,13,15,17)은 상부 다이패드(21b)와 하부 다이패드(22b)의 사이에서 빗겨 적층된 형태를 이루고 있다. 따라서, 각 반도체 칩들(11,13,15,17)은 본딩패드들(12,14,16,18)이 상방향으로 개방되어 있다. 이 개방된 본딩패드들(12,14,16,18)과 반도체 칩들(11,13,15,17)로부터 소정의 거리로 이격되어 있는 리드들(21a,22a)이 본딩 와이어(25)로 와이어 본딩되어 있다.The first to fourth semiconductor chips 11, 13, 15, and 17 are combed and stacked between the upper die pad 21b and the lower die pad 22b. Therefore, each of the semiconductor chips 11, 13, 15, and 17 has bonding pads 12, 14, 16, and 18 open upward. The open bonding pads 12, 14, 16, and 18 and the leads 21 a, 22 a spaced apart from the semiconductor chips 11, 13, 15, and 17 by a predetermined distance are connected to the bonding wire 25. Bonded
그리고, 반도체 칩들(11,13,15,17)과 본딩 와이어(25) 및 그 접합 부위는 에폭시 성형 수지와 같은 플라스틱 봉지재로 형성된 패키지 몸체(27)로 봉지되어 외부환경으로부터 물리적으로나 화학적으로 보호된다.In addition, the semiconductor chips 11, 13, 15, and 17, the bonding wire 25, and the bonding portion thereof are encapsulated with a package body 27 formed of a plastic encapsulating material such as an epoxy molding resin, thereby physically and chemically protecting from the external environment. do.
이와 같은 적층 칩 패키지는 제 1반도체 칩을 리드프레임의 다이패드에 실장하고 제 2반도체 칩을 실장하여 와이어 본딩하고 이와는 별도로 제 3반도체 칩을 다른 리드프레임의 다이패드에 실장하고 제 4반도체 칩을 실장하여 와이어 본딩한 상태에서, 두 리드 프레임을 부착하고 패키지 몸체를 형성한 후에 리드에 대한 절단 및 절곡 공정을 진행하여 제조될 수 있다.The stacked chip package mounts the first semiconductor chip on the die pad of the lead frame, wires the second semiconductor chip on the die pad of the lead frame, and separately mounts the third semiconductor chip on the die pad of the other lead frame and installs the fourth semiconductor chip. In the mounted and wire-bonded state, the two lead frames may be attached and the package body may be formed, and then the cutting and bending processes of the leads may be performed.
전술한 실시예에서와 같은 본 발명의 적층 칩 패키지는 반도체 칩들이 빗겨 적층된 형태를 가지고 있어 각각의 본딩패드와 리드의 와이어 본딩이 가능하며, 각각의 반도체 칩들의 크기가 동일하여도 구현이 가능하다. 즉, 반도체 칩들의 적층 가능 범위가 넓어져 4개 이상의 반도체 칩의 적층에도 무리가 없다.The stacked chip package of the present invention as in the above-described embodiment has a form in which semiconductor chips are combed and stacked to enable wire bonding between respective bonding pads and leads, and may be implemented even when the size of each semiconductor chip is the same. Do. In other words, the stackable range of semiconductor chips is widened, and stacking of four or more semiconductor chips can be performed without difficulty.
한편, 본 발명의 적층 칩 패키지는 위의 실시예에 한정되지 않고 본 발명의기술적 중심사상을 벗어나지 않는 범위 내에서 다양하게 변형 실시될 수 있다. 예를 들어, 반도체 칩들이 실장되는 영역으로서 상부 다이패드와 하부 다이패드가 형성된 리드프레임을 사용하고 있으나 다이패드가 존재하지 않고 리드에 바로 실장시키는 형태의 적용도 가능하다. 또한, 다이패드를 중심으로 상하로 반도체 칩들을 적층시키는 형태의 적용도 가능하다. 본 발명의 다른 실시예를 소개하기로 한다.Meanwhile, the stacked chip package of the present invention is not limited to the above embodiments and may be variously modified within a range not departing from the technical spirit of the present invention. For example, although a lead frame having an upper die pad and a lower die pad is used as an area in which semiconductor chips are mounted, an application in which a die pad does not exist and is directly mounted on a lead is also possible. In addition, it is also possible to apply the form of stacking the semiconductor chips up and down around the die pad. Another embodiment of the present invention will be introduced.
도 3은 본 발명에 따른 적층 칩 패키지의 다른 실시예를 나타낸 단면도이다.3 is a cross-sectional view showing another embodiment of a stacked chip package according to the present invention.
도 3을 참조하면, 이 적층 칩 패키지(50)는 다이패드(61b)의 상하로 각각 두 개씩의 반도체 칩들(51,53,55,57)이 본딩패드들(52,54,56,58)이 개방되도록 빗겨 적층된 구조로서, 각 반도체 칩들(51,53,55,57)은 활성면의 일측 가장자리에 본딩패드가 형성되어 있는 것이다. 제 1반도체 칩(51)이 다이패드(61b)의 상면에 본딩패드(52)가 상방향을 향하도록 부착되어 있고, 제 2반도체 칩(53)이 본딩패드(54)가 상방향을 향하도록 1반도체 칩(51)의 활성면에 부착되어 있다. 그리고, 제 3반도체 칩(55)이 본딩패드(56)가 하방향을 향하도록 다이패드(61b)의 밑면에 부착되어 있고, 제 4반도체 칩(57)이 본딩패드(58)가 하방향을 향하도록 제 3반도체 칩(55)의 활성면에 부착되어 있다. 각 반도체 칩들(51,53,55,57)의 본딩패드(52,54,56,58)는 리드(61a)와 본딩 와이어(65)로 와이어 본딩되어 있다. 그리고, 반도체 칩들(51,53,55,57)과 본딩 와이어(65) 및 그 접합 부위는 패키지 몸체(67)에 의해 봉지되어 있다.Referring to FIG. 3, in the stacked chip package 50, two semiconductor chips 51, 53, 55, and 57 are disposed on the die pad 61b, respectively, and bonding pads 52, 54, 56, and 58. The semiconductor chip 51, 53, 55, 57 has a bonding pad formed on one side edge of the active surface. The first semiconductor chip 51 is attached to the upper surface of the die pad 61b so that the bonding pads 52 face upward, and the second semiconductor chip 53 faces the bonding pads 54 upward. 1 is attached to the active surface of the semiconductor chip 51. The third semiconductor chip 55 is attached to the bottom surface of the die pad 61b so that the bonding pads 56 face downward, and the fourth semiconductor chip 57 has a bonding pad 58 facing downward. Facing the active surface of the third semiconductor chip 55. The bonding pads 52, 54, 56, and 58 of the semiconductor chips 51, 53, 55, and 57 are wire bonded to the lead 61a and the bonding wire 65. The semiconductor chips 51, 53, 55, 57, the bonding wire 65, and the junction portion thereof are sealed by the package body 67.
이와 같은 적층 칩 패키지는 제 1반도체 칩을 다이패드에 부착하고 제 2반도체 칩을 제 1반도체 칩에 부착시킨 후에 제 3반도체 칩을 부착하고 제 4반도체 칩을 제 3반도체 칩에 부착시킨 후 각각의 반도체 칩들과 리드를 와이어 본딩하고 패키지 몸체를 형성한 후 패키지 몸체의 외부로 노출된 리드에 대한 절단 및 절곡 공정으로 제조될 수 있다.In the stacked chip package, the first semiconductor chip is attached to the die pad, the second semiconductor chip is attached to the first semiconductor chip, the third semiconductor chip is attached, and the fourth semiconductor chip is attached to the third semiconductor chip. After the wire bonding of the semiconductor chips and the lead to form a package body can be manufactured by a cutting and bending process for the lead exposed to the outside of the package body.
이상과 같은 본 발명에 의한 적층 칩 패키지에 따르면 2개 이상의 반도체 칩이 적층 형태로 구성될 수 있기 때문에 보다 대용량으로 고밀도 실장이 가능하며, 이는 동일한 크기의 반도체 칩들로도 구현이 가능하다.According to the multilayer chip package according to the present invention as described above, since two or more semiconductor chips can be configured in a stacked form, high density mounting is possible with a larger capacity, which can be implemented with semiconductor chips of the same size.
Claims (3)
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| KR1019990064436A KR20010061886A (en) | 1999-12-29 | 1999-12-29 | Stack chip package |
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| KR1019990064436A KR20010061886A (en) | 1999-12-29 | 1999-12-29 | Stack chip package |
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| KR20010061886A true KR20010061886A (en) | 2001-07-07 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010088672A (en) * | 2001-08-20 | 2001-09-28 | 심재택 | pile-up type semi-conductor structure and semi-conductor thereof |
| KR100395797B1 (en) * | 2001-09-04 | 2003-08-25 | 주식회사 바른전자 | Semiconductor chip having electrode pad arrangement suitable for chip stacking and a chip stacked package device comprising such chips |
| KR100497974B1 (en) * | 2001-06-13 | 2005-07-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| KR100966684B1 (en) * | 2007-02-20 | 2010-06-29 | 가부시끼가이샤 도시바 | Semiconductor device and semiconductor module using the same |
| KR101013563B1 (en) * | 2009-02-25 | 2011-02-14 | 주식회사 하이닉스반도체 | Stack package |
| KR101432481B1 (en) * | 2012-11-09 | 2014-08-21 | 에스티에스반도체통신 주식회사 | Stacked package |
| KR20150063167A (en) * | 2006-08-16 | 2015-06-08 | 테세라, 인코포레이티드 | Microelectronic package |
| US9349672B2 (en) | 2007-08-16 | 2016-05-24 | Tessera, Inc. | Microelectronic package |
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1999
- 1999-12-29 KR KR1019990064436A patent/KR20010061886A/en not_active Application Discontinuation
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100497974B1 (en) * | 2001-06-13 | 2005-07-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| KR20010088672A (en) * | 2001-08-20 | 2001-09-28 | 심재택 | pile-up type semi-conductor structure and semi-conductor thereof |
| KR100395797B1 (en) * | 2001-09-04 | 2003-08-25 | 주식회사 바른전자 | Semiconductor chip having electrode pad arrangement suitable for chip stacking and a chip stacked package device comprising such chips |
| KR20150063167A (en) * | 2006-08-16 | 2015-06-08 | 테세라, 인코포레이티드 | Microelectronic package |
| KR100966684B1 (en) * | 2007-02-20 | 2010-06-29 | 가부시끼가이샤 도시바 | Semiconductor device and semiconductor module using the same |
| US9349672B2 (en) | 2007-08-16 | 2016-05-24 | Tessera, Inc. | Microelectronic package |
| KR101013563B1 (en) * | 2009-02-25 | 2011-02-14 | 주식회사 하이닉스반도체 | Stack package |
| US8237291B2 (en) | 2009-02-25 | 2012-08-07 | Hynix Semiconductor Inc. | Stack package |
| KR101432481B1 (en) * | 2012-11-09 | 2014-08-21 | 에스티에스반도체통신 주식회사 | Stacked package |
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