JPH10335366A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10335366A
JPH10335366A JP9142229A JP14222997A JPH10335366A JP H10335366 A JPH10335366 A JP H10335366A JP 9142229 A JP9142229 A JP 9142229A JP 14222997 A JP14222997 A JP 14222997A JP H10335366 A JPH10335366 A JP H10335366A
Authority
JP
Japan
Prior art keywords
semiconductor chip
pad
bonding
wire
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9142229A
Other languages
Japanese (ja)
Inventor
Makoto Tsubonoya
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9142229A priority Critical patent/JPH10335366A/en
Publication of JPH10335366A publication Critical patent/JPH10335366A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01—ELECTRIC ELEMENTS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To avoid damages on a chip, and to directly wire-bond pads by providing metallic protrusions at the pad. SOLUTION: A first semiconductor chip 10 and a second semiconductor chip 11 are fixed to an island 13. A pad 12 is connected through a bonding wire 16 with an outside connection lead 15. A metallic conductive piece such as a bump 17 is formed on one pad 12a from among pads 12a for operating an electrical connection between both semiconductor chips 10 and 11. The upper face of the metallic conductive piece is projected above a passivation coating. Then, a 1st bond of the bonding wire 16 is hit on the pad 12a of the first semiconductor chip 10, and the 2nd bond is hit on the surface of the bump 17 of the second semiconductor chip 11, so that necessary electrical connection is obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、同一パッケージ内
に複数の半導体チップを収納し、半導体チップ間のワイ
ヤ接続を容易ならしめた半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are housed in the same package and wire connection between the semiconductor chips is facilitated.

【０００２】[0002]

【従来の技術】半導体装置の封止技術として最も普及し
ているのが、半導体チップの周囲を熱硬化性のエポキシ
樹脂で封止するトランスファーモールド技術である。半
導体チップの支持素材としてリードフレームを用い、リ
ードフレームのアイランドに半導体チップをダイボンド
し、半導体チップのボンディングパッドとリードをワイ
ヤでワイヤボンドし、所望の外形形状を具備する金型内
にリードフレームをセットし、金型内にエポキシ樹脂を
注入、これを硬化させることにより製造する。2. Description of the Related Art A transfer molding technique for sealing the periphery of a semiconductor chip with a thermosetting epoxy resin is most widely used as a sealing technique for a semiconductor device. A lead frame is used as a support material for the semiconductor chip, the semiconductor chip is die-bonded to the lead frame island, the bonding pads of the semiconductor chip and the leads are wire-bonded with wires, and the lead frame is placed in a mold having a desired external shape. It is manufactured by setting, injecting an epoxy resin into a mold, and curing the epoxy resin.

【０００３】一方、各種電子機器に対する小型、軽量化
の波はとどまるところを知らず、これらに組み込まれる
半導体装置にも、一層の大容量、高機能、高集積化が望
まれることになる。そこで、以前から発想としては存在
していた（例えば、特開平０５ー１２１６４５号）、１
つのパッケージ内に複数の半導体チップを封止する技術
が注目され、実現化する動きが出てきた。つまり図５
（Ａ）（Ｂ）に示すように、アイランド１上に第１と第
２の半導体チップ２ａ、２ｂを固着し、第１と第２の半
導体チップ２ａ、２ｂのボンディングパッド３とリード
４とをボンディングワイヤ５で接続し、樹脂６で封止し
たものである。On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration. Therefore, there has been an idea from before (for example, Japanese Patent Laid-Open No. 05-121645).
Attention has been paid to a technology for sealing a plurality of semiconductor chips in one package, and there has been a move toward realization. That is, FIG.
(A) As shown in (B), the first and second semiconductor chips 2a and 2b are fixed on the island 1, and the bonding pads 3 and the leads 4 of the first and second semiconductor chips 2a and 2b are connected. They are connected by bonding wires 5 and sealed with resin 6.

【０００４】回路機能の組み合わせによって第１の半導
体チップ１ａと第２の半導体チップ１ｂとを電気的に接
続する場合は、上述した特開平０５ー１２１６４５号の
様にパッドからパッドに直接ボンディングワイヤを打つ
ことが考えられるが、ボールを形成しない２回目のボン
ディングをパッド上に直接打つと、キャピラリツールの
先端が半導体チップの表面に直接接触して半導体チップ
にダメージを与えることになる。そこで、外部接続リー
ド４の一つを中間点とし、第１の半導体チップ１ａと第
２の半導体チップ１ｂの両方から共通の外部接続リード
４にワイヤを打つか（図示しない）、または図５（Ａ）
（Ｂ）に示した様に、アイランド１とは電気的に絶縁し
た接続導体７をアイランド１上に固着し、接続導体７を
介して両半導体チップ１ａ、１ｂを接続していた。When the first semiconductor chip 1a and the second semiconductor chip 1b are electrically connected by a combination of circuit functions, a bonding wire is directly connected from pad to pad as described in Japanese Patent Application Laid-Open No. 05-121645. It is conceivable to hit, but if the second bonding without forming a ball is hit directly on the pad, the tip of the capillary tool will directly contact the surface of the semiconductor chip and damage the semiconductor chip. Therefore, one of the external connection leads 4 is set as an intermediate point, and a wire is driven from both the first semiconductor chip 1a and the second semiconductor chip 1b to the common external connection lead 4 (not shown), or FIG. A)
As shown in (B), a connection conductor 7 electrically insulated from the island 1 is fixed on the island 1, and the two semiconductor chips 1 a and 1 b are connected via the connection conductor 7.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、前者の
外部接続リードを介して接続する手法はボンディングワ
イヤ５が長くなるので他との接触事故等の要因になる
他、リード端子の本数増大になるという欠点があり、後
者の接続導体７を用いる手法は部品代と工数的に大幅な
コスト高になり、接続導体７を配置することによりパッ
ケージが大型化するという欠点があった。However, in the former method of connecting via the external connection lead, the bonding wire 5 becomes longer, which may cause a contact accident with others and increase the number of lead terminals. There is a drawback, and the latter method using the connection conductor 7 has a drawback in that the cost of parts and man-hour is greatly increased, and the arrangement of the connection conductor 7 results in an increase in size of the package.

【０００６】[0006]

【課題を解決するための手段】本発明は上述した従来の
課題に鑑み成されたもので、半導体チップのパッド上に
導体片を固着し、該導体片にワイヤの２ｎｄボンドを打
つことにより、キャピラリツールが半導体チップに接触
することなく、第１の半導体チップ１ａと第２の半導体
チップ１ｂとをボンディングワイヤで直接接続すること
を可能ならしめたものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and comprises fixing a conductor piece on a pad of a semiconductor chip and forming a second bond of a wire on the conductor piece. The first semiconductor chip 1a and the second semiconductor chip 1b can be directly connected by bonding wires without the capillary tool coming into contact with the semiconductor chip.

【０００７】[0007]

【発明の実施の形態】以下に本発明の一実施の形態を図
面を参照しながら詳細に説明する。図１は本発明の半導
体装置を示す（Ａ）平面図、（Ｂ）断面図である。図
中、１０、１１は各々第１と第２の半導体チップ、１２
は第１と第２の半導体チップ１０、１１の表面に形成し
たボンディングパッド、１３は半導体チップ１０、１１
を搭載するためのアイランド、１４は半導体チップ１
０、１１を固着するための接着剤、１５は外部接続リー
ド、１６はパッド１２と外部接続リード１５とを接続す
るボンディングワイヤ、１７は主要部を封止する樹脂を
示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIGS. 1A and 1B are a plan view and a sectional view, respectively, showing a semiconductor device of the present invention. In the figure, reference numerals 10 and 11 denote first and second semiconductor chips, respectively.
Is a bonding pad formed on the surface of the first and second semiconductor chips 10 and 11, and 13 is a semiconductor chip 10, 11
Island 14 for mounting the semiconductor chip 1
An adhesive for fixing 0 and 11 is shown, 15 is an external connection lead, 16 is a bonding wire connecting the pad 12 and the external connection lead 15, and 17 is a resin for sealing a main part.

【０００８】第１と第２の半導体チップ１０、１１のシ
リコン表面には、前工程において各種の能動、受動回路
素子を形成し、各素子を電極配線で接続することにより
所望の回路機能を達成している。ボンディングパッド１
２は前記電極材料からなり、各チップの周辺部分に複数
個配置されている。各半導体チップ１０、１１の表面に
はボンディングパッド１２を被覆するようにシリコン窒
化膜、シリコン酸化膜、ポリイミド系絶縁膜などのパッ
シベーション皮膜が形成され、ボンディングパッド１２
の上部だけが電気接続のために開口されている。Various active and passive circuit elements are formed on the silicon surface of the first and second semiconductor chips 10 and 11 in the previous process, and the desired circuit functions are achieved by connecting the elements by electrode wiring. doing. Bonding pad 1
Reference numeral 2 is made of the above-mentioned electrode material, and a plurality of the reference numerals 2 are arranged around each chip. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed on the surface of each of the semiconductor chips 10 and 11 so as to cover the bonding pad 12.
Only the top is open for electrical connection.

【０００９】各半導体チップ１０、１１は、リードフレ
ームのアイランド１３上に並べて接着剤１４によりダイ
ボンドされている。基板の導電型が同じ組み合わせであ
る場合は両者共にＡｇペーストなどのエポキシ系導電接
着剤を使用するが、導電型が異なる場合及び基板電位が
異なる場合は、どちらか一方または両方を絶縁性の接着
剤によってダイボンドしている。The semiconductor chips 10 and 11 are die-bonded with an adhesive 14 side by side on an island 13 of a lead frame. When the conductive type of the substrate is the same combination, use an epoxy-based conductive adhesive such as Ag paste for both, but when the conductive type is different and the substrate potential is different, either or both of them should be insulated. It is die-bonded by the agent.

【００１０】ボンディングワイヤ１６は直径３０ミクロ
ン程度の金線からなり、ボールボンディング方式により
パッド１２と外部接続リード１５とを電気的に接続す
る。すなわち、先端に金ボールを形成したボンディング
ワイヤ１６を各半導体チップ１０、１１のパッド１２上
に押しつけて１ｓｔボンドとし、キャビラリツールを移
動し、外部接続リード１５の先端部表面に押圧接着する
と共に切断して２ｎｄボンドとする方式である。各半導
体チップ１０、１１の、外部接続リード１５に近接する
３辺に位置するパッド１２は、ボールボンドにより外部
接続リード１５に接続する。残りの各１辺、すなわち、
第１と第２の半導体チップ１０、１１が相対向する辺に
位置するパッド１２ａは、第１の半導体チップ１０から
第２の半導体チップ１１にワイヤボンドして、両者を直
接電気的に接続する。２ｎｄボンド側となる第２の半導
体チップ１１のパッド１２ａ上には、ワイヤとの接続を
介するバンプ１７等の金属導体辺が固着されており、ボ
ンディングワイヤ１６の端部は前記金属導体辺にボンデ
ィングされている。詳細は後述する。The bonding wire 16 is made of a gold wire having a diameter of about 30 μm, and electrically connects the pad 12 and the external connection lead 15 by a ball bonding method. That is, a bonding wire 16 having a gold ball formed at the tip is pressed against the pad 12 of each of the semiconductor chips 10 and 11 to form a first bond, the cab tool is moved, and the bonding wire 16 is pressed and adhered to the surface of the tip of the external connection lead 15. This is a method of cutting into 2nd bonds. Pads 12 located on three sides of each of the semiconductor chips 10 and 11 adjacent to the external connection lead 15 are connected to the external connection lead 15 by ball bonding. Each of the remaining sides, ie
The pad 12a located on the side where the first and second semiconductor chips 10 and 11 face each other is wire-bonded from the first semiconductor chip 10 to the second semiconductor chip 11 to directly electrically connect the two. . A metal conductor side such as a bump 17 is fixed to the pad 12a of the second semiconductor chip 11 on the second bond side through connection with a wire, and an end of the bonding wire 16 is bonded to the metal conductor side. Have been. Details will be described later.

【００１１】第１と第２の半導体チップ１０、１１、外
部接続リード１５の先端部、およびボンディングワイヤ
１６を含む主要部は、周囲をエポキシ系の熱硬化樹脂１
８でモールドし、パッケージ化する。リード端子１５は
パッケージの側壁の、樹脂１８の厚みの約半分の位置か
ら外部に導出される。そして、樹脂１８の外部に導出さ
れたリード端子１５は一端下方に曲げられ、再度曲げら
れてＺ字型にフォーミングされている。このフォーミン
グ形状は、リード端子１５の裏面側固着部分をプリント
基板に形成した導電パターンに対向接着する、表面実装
用途の為の形状である。The main parts including the first and second semiconductor chips 10 and 11, the tip of the external connection lead 15, and the bonding wire 16 are surrounded by an epoxy-based thermosetting resin 1.
8. Mold and package. The lead terminal 15 is led out from a position on the side wall of the package which is about half the thickness of the resin 18. The lead terminal 15 led out of the resin 18 is bent downward at one end, bent again, and formed into a Z-shape. This forming shape is a shape for surface mounting use in which the fixed portion on the rear surface side of the lead terminal 15 is opposed to the conductive pattern formed on the printed circuit board.

【００１２】図２に、相対向する辺に形成したパッド１
２ａ付近の拡大図を示す。パッド１２ａは半導体基板上
の絶縁膜２０の上にアルミなどの電極配線材料で１３０
×１３０μ程度の矩形の大きさで形成され、絶縁膜２０
上を引き回した電極配線２１にて内部回路と接続してい
る。パッド１２ａの上部をパッシベーション皮膜２２が
被覆し、上部に開口部２３を形成してパッド１２ａ表面
を露出している。第２の半導体チップ１１のパッド１２
ａは、２ｎｄボンド用に長方形に拡大しており、その表
面に金又は半田等のバンプ１７が形成されている。バン
プ１７は第２の半導体チップ１１のウェハ工程の最終段
階で、無電界または電解メッキ法によりパッド１２ａ表
面にだけ選択的に形成したもので、パッシベーション皮
膜２２より上に突出するように、例えば高さ１００μ程
度に形成したものである。外部接続リード１５との接続
を行うパッド１２には、バンプ１７を形成してもしなく
ても良い。そして、第１の半導体チップ１０のパッド１
２ａ表面にボンディングワイヤ１６の１ｓｔボンドが打
たれ、２ｎｄボンドがバンプ１７の表面に打たれる。FIG. 2 shows pads 1 formed on opposing sides.
An enlarged view near 2a is shown. The pad 12a is formed of an electrode wiring material such as aluminum on the insulating film 20 on the semiconductor substrate.
The insulating film 20 is formed in a rectangular size of about × 130 μm.
It is connected to the internal circuit by the electrode wiring 21 routed upward. An upper portion of the pad 12a is covered with a passivation film 22, and an opening 23 is formed on the upper portion to expose the surface of the pad 12a. Pad 12 of second semiconductor chip 11
“a” is enlarged in a rectangular shape for a second bond, and a bump 17 made of gold or solder is formed on the surface thereof. The bumps 17 are selectively formed only on the surfaces of the pads 12 a by an electric field-free or electrolytic plating method at the final stage of the wafer process of the second semiconductor chip 11. It is formed to have a thickness of about 100 μm. The bumps 17 may or may not be formed on the pads 12 for connection to the external connection leads 15. Then, the pad 1 of the first semiconductor chip 10
The first bond of the bonding wire 16 is hit on the surface of 2a, and the second bond is hit on the surface of the bump 17.

【００１３】図３、図４にワイヤボンド工程の概略図を
工程順に示した。先ず図３（Ａ）に示すように、キャピ
ラリ２５の貫通孔２６に挿通されたワイヤ１６の先端に
金ボール２７を形成し、該金ボール２７を第１の半導体
チップ１０のパッド１２ａ表面に押圧・加熱超音波振動
により固着して１ｓｔボンドとし、図３（Ｂ）に示すよ
うにキャピラリ２５を上方向、続いて横方向に移動し
て、図３（Ｃ）に示すようにバンプ１７上部にワイヤ１
６を再度押圧・加熱超音波振動により固着して２ｎｄボ
ンドとする。前記２ｎｄボンドの時は、図４に示すよう
に、キャピラリ２５の先端部２８でワイヤ１６を押潰す
ことによりワイヤ１６を切断するので、先端部２８が被
固着面２９に機械的に直接接触することになる。しかし
本発明では、パッド１２ａ上に形成したバンプ１７の上
に２ｎｄボンドを打ち、バンプ１７の被固着面２９がパ
ッシベーション皮膜２２より上方に位置するので、キャ
ピラリの先端部２８が第２の半導体チップ１１表面にダ
メージを与えることがない。FIGS. 3 and 4 show schematic views of the wire bonding step in the order of steps. First, as shown in FIG. 3A, a gold ball 27 is formed at the tip of the wire 16 inserted into the through hole 26 of the capillary 25, and the gold ball 27 is pressed against the surface of the pad 12a of the first semiconductor chip 10. -The first bond is formed by heating ultrasonic vibration to form a first bond, and the capillary 25 is moved upward and subsequently laterally as shown in FIG. 3 (B), and is moved to the top of the bump 17 as shown in FIG. 3 (C). Wire 1
6 is again fixed by pressing and heating ultrasonic vibration to form a second bond. At the time of the 2nd bond, as shown in FIG. 4, the wire 16 is cut by crushing the wire 16 at the tip 28 of the capillary 25, so that the tip 28 comes into direct mechanical contact with the surface 29 to be fixed. Will be. However, in the present invention, a second bond is formed on the bump 17 formed on the pad 12a, and the fixed surface 29 of the bump 17 is located above the passivation film 22, so that the tip 28 of the capillary is connected to the second semiconductor chip. 11 Does not damage the surface.

【００１４】そして図４（Ｂ）に示すように、キャピラ
リ２５上方に位置する図示せぬクランパがワイヤ１６を
挟み固定し、その状態でキャピラリ２５を上方に移動す
ることにより、２ｎｄボンドされたワイヤ１６と貫通孔
２６内部のワイヤとを分離する。以上に説明したよう
に、本発明では第２の半導体チップ１０上のボンディン
グパッド１２ａ上にバンプ１７を形成し、チップ表面よ
り突出した該バンプ１７上にワイヤ１６の２ｎｄボンド
を打つので、キャピラリ２５によって半導体チップ表面
にダメージを与えることなく、第１の半導体チップ１０
と第２の半導体チップ１１とを直接ボンディングワイヤ
１６で接続できるものである。Then, as shown in FIG. 4B, a clamper (not shown) located above the capillary 25 sandwiches and fixes the wire 16 and moves the capillary 25 upward in this state, thereby forming the second-bonded wire. 16 and the wire inside the through hole 26 are separated. As described above, in the present invention, the bump 17 is formed on the bonding pad 12a on the second semiconductor chip 10 and the second bond of the wire 16 is formed on the bump 17 protruding from the chip surface. The first semiconductor chip 10 without damaging the surface of the semiconductor chip.
And the second semiconductor chip 11 can be directly connected by the bonding wire 16.

【００１５】尚、バンプ１７の他にも、例えば金、アル
ミ等の金属片をパッド１２ａ上に接着剤で固着しても良
く、要はボンディングワイヤ１６が接続可能な材料で、
その固着表面２９がパッシベーション皮膜２２より高い
位置に存在し、その大きさがキャピラリ２５先端部分２
８の大きさより大であればよい。In addition, besides the bump 17, a metal piece such as gold, aluminum or the like may be fixed on the pad 12a with an adhesive, that is, a material to which the bonding wire 16 can be connected.
The fixing surface 29 is present at a position higher than the passivation film 22 and the size thereof is
It suffices if the size is larger than 8.

【００１６】[0016]

【発明の効果】以上に説明した通り、本発明によれば、
チップにダメージを与えることなく第１の半導体チップ
１０と第２の半導体チップ１１とを直接ボンディングワ
イヤ１６で接続できる利点を有する。その為、複数の半
導体チップを収納した半導体装置を安価に製造すること
ができる利点を有する。更に、従来例のように接続を仲
介する部分がないので、半導体装置の横方向の寸法を縮
小できる利点を有する他、部品代等のコストを大幅に減
じることができる。As described above, according to the present invention,
There is an advantage that the first semiconductor chip 10 and the second semiconductor chip 11 can be directly connected by the bonding wires 16 without damaging the chip. Therefore, there is an advantage that a semiconductor device containing a plurality of semiconductor chips can be manufactured at low cost. Furthermore, since there is no portion that mediates the connection unlike the conventional example, the semiconductor device has an advantage that the lateral dimension of the semiconductor device can be reduced, and the cost of parts and the like can be significantly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を説明するための（Ａ）平面図、（Ｂ）
断面図である。FIG. 1A is a plan view for explaining the present invention, and FIG.
It is sectional drawing.

【図２】本発明のパッド１２ａ付近を示す（Ａ）断面
図、（Ｂ）平面図である。FIGS. 2A and 2B are a cross-sectional view and a plan view showing a vicinity of a pad 12a of the present invention.

【図３】ワイヤボンド工程を説明するための断面図であ
る。FIG. 3 is a cross-sectional view for explaining a wire bonding step.

【図４】ワイヤボンド工程を説明するための断面図であ
る。FIG. 4 is a cross-sectional view for explaining a wire bonding step.

【図５】従来例を説明するための（Ａ）平面図、（Ｂ）
断面図である。5A is a plan view for explaining a conventional example, and FIG.
It is sectional drawing.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 アイランドの上に少なくとも２個の半導
体チップを並べて設置し、前記半導体チップ上のボンデ
ィングパッドと外部接続リードとをボンディングワイヤ
で各々接続し、更に前記半導体チップのボンディングパ
ッドと他の半導体チップのボンディングパッドとをボン
ディングワイヤで接続し、主要部を封止した半導体装置
であって、 前記半導体チップのボンディングパッド上に１ｓｔボン
ドを打つと共に、前記他の半導体チップのボンディング
パッドに導体片が固着され、前記導体片に前記ボンディ
ングワイヤの２ｎｄボンドが打たれていることを特徴と
する半導体装置。At least two semiconductor chips are arranged side by side on an island, a bonding pad on the semiconductor chip is connected to an external connection lead by a bonding wire, and a bonding pad of the semiconductor chip is connected to another bonding chip. A semiconductor device in which a main part is sealed by connecting a bonding pad of a semiconductor chip with a bonding wire, wherein a first bond is formed on the bonding pad of the semiconductor chip, and a conductor piece is bonded to the bonding pad of the other semiconductor chip. Wherein a second bond of the bonding wire is formed on the conductor piece. 【請求項２】 前記ワイヤボンディングがボールボンド
であることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said wire bonding is ball bonding. 【請求項３】 前記導体片が金バンプ又は半田バンプで
あることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said conductor pieces are gold bumps or solder bumps.
JP9142229A 1997-05-30 1997-05-30 Semiconductor device Pending JPH10335366A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9142229A JPH10335366A (en) 1997-05-30 1997-05-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9142229A JPH10335366A (en) 1997-05-30 1997-05-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10335366A true JPH10335366A (en) 1998-12-18

Family

ID=15310432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9142229A Pending JPH10335366A (en) 1997-05-30 1997-05-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10335366A (en)

Cited By (7)

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Publication number Priority date Publication date Assignee Title
KR100491234B1 (en) * 2001-12-03 2005-05-25 미쓰비시덴키 가부시키가이샤 Semiconductor integrated circuit device
JP2006261542A (en) * 2005-03-18 2006-09-28 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2007220790A (en) * 2006-02-15 2007-08-30 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2008028414A (en) * 2007-09-14 2008-02-07 Renesas Technology Corp Semiconductor device
JP2009295988A (en) * 2008-06-09 2009-12-17 Micronas Gmbh Semiconductor assembly with specially formed bond wires, and method for fabricating such arrangement
JP2014220439A (en) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 Method of manufacturing semiconductor device and semiconductor device
CN107785347A (en) * 2016-08-24 2018-03-09 三星显示有限公司 Semiconductor chip and electronic installation

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100491234B1 (en) * 2001-12-03 2005-05-25 미쓰비시덴키 가부시키가이샤 Semiconductor integrated circuit device
US7148567B2 (en) 2001-12-03 2006-12-12 Renesas Technology Corp. Semiconductor integrated circuit device
JP2006261542A (en) * 2005-03-18 2006-09-28 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP4666592B2 (en) * 2005-03-18 2011-04-06 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2007220790A (en) * 2006-02-15 2007-08-30 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2008028414A (en) * 2007-09-14 2008-02-07 Renesas Technology Corp Semiconductor device
JP2009295988A (en) * 2008-06-09 2009-12-17 Micronas Gmbh Semiconductor assembly with specially formed bond wires, and method for fabricating such arrangement
JP2014220439A (en) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 Method of manufacturing semiconductor device and semiconductor device
CN107785347A (en) * 2016-08-24 2018-03-09 三星显示有限公司 Semiconductor chip and electronic installation
CN107785347B (en) * 2016-08-24 2023-08-15 三星显示有限公司 Semiconductor chip and electronic device

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