JPH053284A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH053284A JPH053284A JP18196791A JP18196791A JPH053284A JP H053284 A JPH053284 A JP H053284A JP 18196791 A JP18196791 A JP 18196791A JP 18196791 A JP18196791 A JP 18196791A JP H053284 A JPH053284 A JP H053284A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- die pad
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型半導体装
置、特に複数の半導体チップを樹脂封止した樹脂封止型
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device in which a plurality of semiconductor chips are resin-sealed.
【０００２】[0002]
【従来の技術】樹脂封止型半導体装置は一般に一個の半
導体チップを樹脂封止してなる。そして、一個の半導体
チップを樹脂封止した半導体制御装置や半導体記憶装置
を、マザーボードと称される多層回路基板上に平面的に
配置して実装していた。2. Description of the Related Art Generally, a resin-sealed semiconductor device is formed by resin-sealing one semiconductor chip. Then, a semiconductor control device and a semiconductor memory device in which one semiconductor chip is resin-sealed are arranged and mounted two-dimensionally on a multilayer circuit board called a mother board.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述した従
来の技術によれば、樹脂封止型半導体装置から引き出さ
れる各配線が多層回路基板に占める面積の割合は、デー
タバスが多ビット化する程大きくなる。そして、配線パ
ターンの高密度化に伴って配線膜が細く且つ長くなる。
また、樹脂封止型半導体装置は多端子化する程サイズが
大きくなり、多層回路基板上に多数の樹脂封止型半導体
装置を配置したときの樹脂封止型半導体装置自身のサイ
ズの総和も大きくなる。By the way, according to the above-mentioned conventional technique, the ratio of the area occupied by each wiring drawn from the resin-sealed semiconductor device to the multi-layer circuit board is such that the data bus has many bits. growing. The wiring film becomes thin and long as the wiring pattern becomes denser.
In addition, the size of the resin-sealed semiconductor device increases as the number of terminals increases, and the total size of the resin-sealed semiconductor device itself when a large number of resin-sealed semiconductor devices are arranged on the multilayer circuit board also increases. Become.
【０００４】本発明はこのような問題点を解決すべく為
されたものであり、占有面積に対する集積回路の密度が
高い樹脂封止型半導体装置を提供することを目的とす
る。The present invention has been made to solve such a problem, and an object of the present invention is to provide a resin-sealed semiconductor device having a high density of integrated circuits with respect to an occupied area.
【０００５】[0005]
【課題を解決するための手段】本発明樹脂封止型半導体
装置は、ダイパッドの表裏両面に半導体チップを接着
し、樹脂封止したことを特徴とする。The resin-encapsulated semiconductor device of the present invention is characterized in that semiconductor chips are adhered to both front and back surfaces of a die pad and resin-encapsulated.
【０００６】[0006]
【実施例】以下、本発明樹脂封止型半導体装置を図示実
施例に従って詳細に説明する。図（Ａ）、（Ｂ）は本発
明樹脂封止型半導体装置の一つの実施例を示すもので、
（Ａ）は樹脂封止前の状態を示す断面図、（Ｂ）は封止
樹脂の第１の半導体チップより上の部分を切り欠いて示
す断面図であり、図２はダイパッドに第１の半導体チッ
プを取り付けた状態の斜視図である。図面において、１
はリードフレーム５のダイパッド、２ａは該ダイパッド
１の裏面に上面が低応力エポキシ樹脂３を介して接着さ
れた第１の半導体チップで、例えばメモリである。尚、
第１の半導体チップ２ａはその両端部の電極４、４、…
がダイパッド１から食み出している。The resin-encapsulated semiconductor device of the present invention will be described in detail below with reference to the illustrated embodiments. FIGS. 1A and 1B show one embodiment of the resin-sealed semiconductor device of the present invention.
FIG. 2A is a sectional view showing a state before resin sealing, FIG. 2B is a sectional view showing a portion of the sealing resin above the first semiconductor chip, and FIG. It is a perspective view of a state where a semiconductor chip is attached. In the drawings, 1
Is a die pad of the lead frame 5, and 2a is a first semiconductor chip whose upper surface is adhered to the back surface of the die pad 1 via a low stress epoxy resin 3, which is, for example, a memory. still,
The first semiconductor chip 2a has electrodes 4, 4, ...
Is protruding from the die pad 1.
【０００７】２ｂは上記ダイパッド１の表面に下面が低
応力エポキシ樹脂３を介して接着された第２の半導体チ
ップで、例えばＣＰＵ、ロジックアレイであり、第１の
半導体チップ２ａより小さい。リードフレーム５は、第
１の半導体チップ２ａに接続される各インナーリードは
デプレスにより第２の半導体チップ２ａと同じ高さまで
低くされ、該各インナーリードの肩部と第１の半導体チ
ップ２ａの各電極４、４、…とはワイヤ６、６、…を介
して電気的に接続されている。尚、ダイパッド１はデプ
レスによりインナーリードの先端よりも高く、インナー
リードの肩部よりも低いところに位置するようにされて
いる。Reference numeral 2b is a second semiconductor chip whose lower surface is adhered to the surface of the die pad 1 through a low stress epoxy resin 3, for example, a CPU or a logic array, which is smaller than the first semiconductor chip 2a. In the lead frame 5, each inner lead connected to the first semiconductor chip 2a is lowered to the same height as the second semiconductor chip 2a by depressing, and the shoulder portion of each inner lead and each of the first semiconductor chip 2a are The electrodes 4, 4, ... Are electrically connected via the wires 6, 6 ,. The die pad 1 is positioned so as to be higher than the tips of the inner leads and lower than the shoulders of the inner leads by depressing.
【０００８】７は第２の半導体チップ２ｂの電極８、
８、…とリードフレーム５のインナーリードとの間を接
続するためのＴＡＢテープで、例えばポリイミド（ある
いはカラエポ系樹脂等）からなる平面形状矩形枠状のベ
ースキャリア９の表面にそれを内側から外側によぎるよ
うにリード１０、１０、…が形成されている。そして、
各リード１０、１０、…の内端部は例えば金バンプ１
１、１１、…を介して第２の半導体チップ２ｂの電極
８、８、…に接続され、外端部はリードフレーム５のリ
ードに接続されている。Reference numeral 7 is an electrode 8 of the second semiconductor chip 2b,
, And the inner leads of the lead frame 5 are connected to each other from the inside to the outside of the base carrier 9 having a planar rectangular frame shape made of, for example, polyimide (or color epoxy resin). The leads 10, 10, ... Are formed so as to cross over. And
The inner ends of the leads 10, 10, ... Are, for example, gold bumps 1.
Are connected to the electrodes 8, 8, ... Of the second semiconductor chip 2b via the terminals 1, 11, ..., And the outer ends are connected to the leads of the lead frame 5.
【０００９】尚、１２、１２、１２、１２はダイパッド
１を支持するサポートバーで、樹脂封止型半導体装置の
最終的段階では封止樹脂１３（図１では２点鎖線で示
す）から露出した部分は切断除去される。Reference numerals 12, 12, 12 and 12 denote support bars for supporting the die pad 1, which are exposed from the sealing resin 13 (shown by a chain double-dashed line in FIG. 1) at the final stage of the resin-sealed semiconductor device. The part is cut off.
【００１０】本樹脂封止型半導体装置においては、第１
の半導体チップ２ａに半導体装置の一対の相対する側縁
部にのみ電極４、４、…が形成されており、第２の半導
体チップ２ｂには４つの側縁部にすべて電極８、８、…
が形成されている。そして、第１の半導体チップ２ａの
電極４、４、…はほとんどリードフレーム５のインナー
リード５ａ、５ａ、…及びＴＡＢリード７のリード１
０、１０、…を介して第２の半導体チップ２ｂの電極
８、８、…と接続されている。即ち、アドレス線、デー
タ入出力線の互いに対応するものどうしが樹脂封止型半
導体装置内部で接続されている。In the present resin-sealed semiconductor device, the first
, Are formed only on a pair of opposing side edges of the semiconductor device, and the second semiconductor chip 2b is provided with electrodes 8, 8, ... On all four side edges.
Are formed. The electrodes 4, 4, ... Of the first semiconductor chip 2a are almost the inner leads 5a, 5a, ... of the lead frame 5 and the leads 1 of the TAB lead 7.
Are connected to the electrodes 8, 8, ... Of the second semiconductor chip 2b through 0, 10 ,. That is, the address lines and the data input / output lines corresponding to each other are connected inside the resin-sealed semiconductor device.
【００１１】本樹脂封止型半導体装置によれば、２つの
半導体チップ２ａ、２ｂはダイパッド１の両面に配置さ
れ樹脂封止されているので、装置の占有面積を広くする
ことなくマルチチップ化して装置内部の回路集積密度を
高めることができる。そして、樹脂封止型半導体装置内
部の半導体チップ２ａと２ｂとの間における電気的接続
は、封止樹脂１３内部で行われ、樹脂封止型半導体装置
を搭載する多層回路基板の配線により行う必要がない。
従って、多層回路基板の配線の数を多く、配線長を長
く、配線密度等を高くすることなく大容量の回路を実装
できる。According to this resin-encapsulated semiconductor device, since the two semiconductor chips 2a and 2b are arranged on both sides of the die pad 1 and resin-encapsulated, the device can be made into a multi-chip without increasing the occupied area. The circuit integration density inside the device can be increased. The electrical connection between the semiconductor chips 2a and 2b inside the resin-encapsulated semiconductor device is performed inside the encapsulation resin 13, and needs to be performed by wiring of the multilayer circuit board on which the resin-encapsulated semiconductor device is mounted. There is no.
Therefore, it is possible to mount a large-capacity circuit without increasing the wiring density, increasing the number of wirings on the multilayer circuit board, and increasing the wiring length.
【００１２】また、本樹脂封止型半導体装置によれば、
ダイパッド１に半導体チップ２ａ、２ｂに接着した状態
で、即ちダイパッド１をベースとしてＴＡＢテープの接
続、ワイヤボンディングができ、組立がやり易くなる。
そして、樹脂封止時においても半導体チップ２ａ、２ｂ
はダイパッド１の両面に固定されているので注入されて
くる樹脂によって動く虞れが少ない。従って、不良も生
じにくくなり、マルチチップ化が容易になる。According to the present resin-sealed semiconductor device,
The TAB tape can be connected and the wire bonding can be performed with the die pad 1 adhered to the semiconductor chips 2a and 2b, that is, with the die pad 1 as a base, which facilitates the assembly.
The semiconductor chips 2a and 2b are also encapsulated in the resin.
Is fixed on both sides of the die pad 1, so there is little risk of movement due to the injected resin. Therefore, defects are less likely to occur, and multi-chip fabrication is facilitated.
【００１３】図３及び図４は本発明樹脂封止型半導体装
置の他の実施例を示すものであり、図３は封止樹脂の第
２の半導体チップより上側を切り欠いて示す平面図、図
４はダイパッドと第１の半導体チップを示す斜視図であ
る。本実施例は、ダイパッド１の相対する一対の側辺部
（第１の半導体チップ２ａの電極４、４、…が形成され
ていない方と対応する一対の側辺部）を少し張り出さ
せ、ダイパッド１の面積を広くすることにより放熱性を
高めると共に、張り出した部分１４、１４に接着性強化
用孔１５、１５、…を形成し、樹脂封止したときに封止
樹脂１３がこの孔１５、１５、…に入って接着力が強く
なるようにしたものである。尚、それ以外の点では本実
施例は、図１、図２に示す実施例と異なるところはな
い。3 and 4 show another embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 3 is a plan view showing a notch above the second semiconductor chip of the encapsulating resin. FIG. 4 is a perspective view showing the die pad and the first semiconductor chip. In the present embodiment, a pair of opposing side portions of the die pad 1 (a pair of side portions corresponding to the side where the electrodes 4, 4, ... Of the first semiconductor chip 2a are not formed) are slightly overhanged, By increasing the area of the die pad 1 to improve heat dissipation, holes 15 for strengthening adhesiveness are formed in the overhanging portions 14 and 14, and the resin 15 is sealed by the sealing resin 13 when the resin is sealed. , 15, ... so that the adhesive strength is increased. Other than that, this embodiment is the same as the embodiment shown in FIGS. 1 and 2.
【００１４】尚、上記実施例においては、ＴＡＢテープ
としてベースにポリイミド樹脂を用いたものを使用して
いたが、ＴＡＢリードの長さが長くなったりした場合の
取扱い容易性やリード変形性を考慮して強度の強いガラ
エポ系樹脂フィルムによりベースを形成したものを用い
るようにしても良い。また、上記実施例においては、ダ
イパッド１と半導体チップ２ａ、２ｂを接着する接着剤
３として低応力エポキシ樹脂を用いていたが、それに代
えて熱可塑性接着剤が両面に塗布されたポリイミドフィ
ルムを用いるようにしても良い。また、上記実施例にお
いては第１の半導体チップ２ａの電極４、４、…とイン
ナーリード５ａ、５ａ、…との接続をワイヤ６により行
っているが、第２の半導体チップ２ｂの電極８、８、…
とインナーリード５ａ、５ａ、…の肩部との接続と同様
にＴＡＢテープを用いて接続するようにしても良い。In the above embodiment, a TAB tape using a polyimide resin as a base was used, but in consideration of ease of handling and lead deformability when the length of the TAB lead becomes long. It is also possible to use a glass epoxy resin film having a strong base as the base. Further, in the above embodiment, the low stress epoxy resin is used as the adhesive 3 for bonding the die pad 1 and the semiconductor chips 2a and 2b, but instead, a polyimide film having thermoplastic adhesive applied on both sides is used. You may do it. Further, in the above embodiment, the electrodes 4, 4, ... Of the first semiconductor chip 2a are connected to the inner leads 5a, 5a ,. 8, ...
The connection may be made by using a TAB tape in the same manner as the connection between the inner leads 5a, 5a ,.
【００１５】[0015]
【発明の効果】本発明樹脂封止型半導体装置は、第１の
半導体チップの上面にダイパッドを接着し、上記ダイパ
ッドの上面に該第１の半導体チップよりも小さな第２の
半導体チップを接着し、該第１の半導体チップと第２の
半導体チップの各電極をリードフレームのインナーリー
ドに電気的に接続したことを特徴とするものである。本
樹脂封止型半導体装置によれば２つの半導体チップがダ
イパッドの両面に接着され樹脂封止されているので装置
の占有面積を広くすることなくマルチチップ化して装置
の集積回路の集積密度を高めることができる。そして、
ダイパッドの両面に半導体チップを接着し、その状態で
ＴＡＢテープを用いる等して電極とインナーリードとの
接続をし、樹脂封止することができるので半導体チップ
を安定にした状態で組立ができる。また、樹脂封止型半
導体装置の内部で２つの半導体チップ間の電気的接続が
できるので、樹脂封止型半導体装置を実装する回路基板
の配線膜の数、集積密度を低減することが可能になる。In the resin-encapsulated semiconductor device of the present invention, the die pad is bonded to the upper surface of the first semiconductor chip, and the second semiconductor chip smaller than the first semiconductor chip is bonded to the upper surface of the die pad. The respective electrodes of the first semiconductor chip and the second semiconductor chip are electrically connected to the inner leads of the lead frame. According to this resin-encapsulated semiconductor device, two semiconductor chips are adhered to both sides of the die pad and resin-encapsulated, so that the device is multi-chiped without increasing the occupied area and the integration density of the integrated circuit of the device is increased. be able to. And
Since the semiconductor chip is adhered to both surfaces of the die pad, and the TAB tape is used in this state to connect the electrode and the inner lead and resin sealing can be performed, the semiconductor chip can be assembled in a stable state. Further, since the two semiconductor chips can be electrically connected inside the resin-sealed semiconductor device, it is possible to reduce the number of wiring films and the integration density of the circuit board on which the resin-sealed semiconductor device is mounted. Become.
【図１】（Ａ）、（Ｂ）は本発明樹脂封止型半導体装置
の一つの実施例を示すもので、（Ａ）は断面図、（Ｂ）
は封止樹脂の上部を切り欠いて示す平面図である。1A and 1B show one embodiment of a resin-encapsulated semiconductor device of the present invention, where FIG. 1A is a sectional view and FIG.
[FIG. 4] is a plan view showing an upper portion of the sealing resin by cutting out.
【図２】上記実施例のダイパッドの裏面に第１の半導体
チップの表面を接着した状態を示す斜視図である。FIG. 2 is a perspective view showing a state in which the front surface of the first semiconductor chip is bonded to the back surface of the die pad of the above embodiment.
【図３】本発明樹脂封止型半導体装置の他の実施例の封
止樹脂の上部を切り欠いて示す平面図である。FIG. 3 is a plan view showing a notched upper portion of a sealing resin of another embodiment of the resin-sealed semiconductor device of the present invention.
【図４】上記他の実施例のダイパッドの裏面に第１の半
導体チップの表面を接着した状態を示す斜視図である。FIG. 4 is a perspective view showing a state in which the front surface of a first semiconductor chip is bonded to the back surface of a die pad according to another embodiment.
１ ダイパッド ２ａ 第１の半導体チップ ２ｂ 第２の半導体チップ ４ 第１の半導体チップの電極 ５ リードフレーム ５ａ リードフレームのリード ８ 第２の半導体チップの電極 １３ 封止樹脂 1 die pad 2a first semiconductor chip 2b second semiconductor chip 4 electrode of first semiconductor chip 5 lead frame 5a lead of lead frame 8 electrode of second semiconductor chip 13 sealing resin
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成３年１１月２１日[Submission date] November 21, 1991
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００６】[0006]
【実施例】以下、本発明樹脂封止型半導体装置を図示実
施例に従って詳細に説明する。図１（Ａ）、（Ｂ）は本
発明樹脂封止型半導体装置の一つの実施例を示すもの
で、（Ａ）は樹脂封止前の状態を示す断面図、（Ｂ）は
封止樹脂の第２の半導体チップより上の部分を切り欠い
て示す断面図であり、図２はダイパッドに第１の半導体
チップを取り付けた状態の斜視図である。図面におい
て、１はリードフレーム５のダイパッド、２ａは該ダイ
パッド１の裏面に上面が低応力エポキシ樹脂３を介して
接着された第１の半導体チップで、例えばメモリであ
る。尚、第１の半導体チップ２ａはその両端部の電極
４、４、…がダイパッド１から食み出している。The resin-encapsulated semiconductor device of the present invention will be described in detail below with reference to the illustrated embodiments. Figure 1 (A), (B) intended to show one embodiment of the present invention the resin-sealed semiconductor device, (A) is a sectional view showing a state before resin sealing, (B) sealing resin 2 is a cross-sectional view showing a part above the second semiconductor chip by cutting away, and FIG. 2 is a perspective view showing a state in which the first semiconductor chip is attached to the die pad. In the drawing, 1 is a die pad of the lead frame 5, and 2a is a first semiconductor chip whose upper surface is adhered to the back surface of the die pad 1 via a low stress epoxy resin 3, for example, a memory. The electrodes 4, 4, ... At both ends of the first semiconductor chip 2a protrude from the die pad 1.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００７】２ｂは上記ダイパッド１の表面に下面が低
応力エポキシ樹脂３を介して接着された第２の半導体チ
ップで、例えばＣＰＵ、ロジックアレイであり、第１の
半導体チップ２ａより小さい。リードフレーム５は、第
１の半導体チップ２ａに接続される各インナーリードは
デプレスにより第１の半導体チップ２ａと同じ高さまで
低くされ、該各インナーリードの肩部と第１の半導体チ
ップ２ａの各電極４、４、…とはワイヤ６、６、…を介
して電気的に接続されている。尚、ダイパッド１はデプ
レスによりインナーリードの先端よりも高く、インナー
リードの肩部よりも低いところに位置するようにされて
いる。Reference numeral 2b is a second semiconductor chip whose lower surface is adhered to the surface of the die pad 1 through a low stress epoxy resin 3, for example, a CPU or a logic array, which is smaller than the first semiconductor chip 2a. In the lead frame 5, each inner lead connected to the first semiconductor chip 2a is lowered to the same height as the first semiconductor chip 2a by depressing, and the shoulder portion of each inner lead and each of the first semiconductor chip 2a are reduced. The electrodes 4, 4, ... Are electrically connected via the wires 6, 6 ,. The die pad 1 is positioned so as to be higher than the tips of the inner leads and lower than the shoulders of the inner leads by depressing.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００８[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００８】７は第２の半導体チップ２ｂの電極８、
８、…とリードフレーム５のインナーリードとの間を接
続するためのＴＡＢテープで、例えばポリイミド（ある
いはカラエポ系樹脂等）からなる平面形状矩形枠状のベ
ースフィルム９の表面にそれを内側から外側によぎるよ
うにリード１０、１０、…が形成されている。そして、
各リード１０、１０、…の内端部は例えば金バンプ１
１、１１、…を介して第２の半導体チップ２ｂの電極
８、８、…に接続され、外端部はリードフレーム５のリ
ードに接続されている。Reference numeral 7 is an electrode 8 of the second semiconductor chip 2b,
.. and the inner lead of the lead frame 5 are connected to each other on the surface of the base film 9 having a planar rectangular frame made of, for example, polyimide (or color epoxy resin) from the inside to the outside. The leads 10, 10, ... Are formed so as to cross each other. And
The inner ends of the leads 10, 10, ... Are, for example, gold bumps 1.
Are connected to the electrodes 8, 8, ... Of the second semiconductor chip 2b via the terminals 1, 11, ..., And the outer ends are connected to the leads of the lead frame 5.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１５[Correction target item name] 0015
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１５】[0015]
【発明の効果】本発明樹脂封止型半導体装置は、第１の
半導体チップの上面にダイパッドを接着し、上記ダイパ
ッドの上面に該第１の半導体チップよりも小さな第２の
半導体チップを接着し、該第１の半導体チップと第２の
半導体チップの各電極をリードフレームのインナーリー
ドに電気的に接続したことを特徴とするものである。本
樹脂封止型半導体装置によれば２つの半導体チップがダ
イパッドの両面に接着され樹脂封止されているので装置
の占有面積を広くすることなくマルチチップ化して装置
の集積回路の集積密度を高めることができる。そして、
ダイパッドの両面に半導体チップを接着し、その状態で
ＴＡＢテープを用いる等して電極とインナーリードとの
接続をし、樹脂封止することができるので半導体チップ
を安定にした状態で組立ができる。また、樹脂封止型半
導体装置の内部で２つの半導体チップ間の電気的接続が
できるので、樹脂封止型半導体装置を実装する回路基板
の配線膜の数を低減し、集積密度を高めることが可能に
なる。In the resin-encapsulated semiconductor device of the present invention, the die pad is bonded to the upper surface of the first semiconductor chip, and the second semiconductor chip smaller than the first semiconductor chip is bonded to the upper surface of the die pad. The respective electrodes of the first semiconductor chip and the second semiconductor chip are electrically connected to the inner leads of the lead frame. According to this resin-encapsulated semiconductor device, two semiconductor chips are adhered to both sides of the die pad and resin-encapsulated, so that the device is multi-chiped without increasing the occupied area and the integration density of the integrated circuit of the device is increased. be able to. And
Since the semiconductor chip is adhered to both surfaces of the die pad, and the TAB tape is used in this state to connect the electrode and the inner lead and resin sealing can be performed, the semiconductor chip can be assembled in a stable state. Further, since the inside of the resin-sealed semiconductor device can the electrical connection between the two semiconductor chips, to reduce the number of wiring film of a circuit board for mounting the resin-sealed semiconductor device, increase the integration density Rukoto Will be possible.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/60 ３０１ Ｂ 6918−4Ｍ ３１１ Ｒ 6918−4Ｍ 23/28 Ａ 8617−4Ｍ 23/50 Ｗ 9272−4Ｍ Ｓ 9272−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication H01L 21/60 301 B 6918-4M 311 R 6918-4M 23/28 A 8617-4M 23/50 W 9272-4M S 9272-4M
Claims (1)
を接着し、上記ダイパッドの上面に上記第１の半導体チ
ップよりも小さな第２の半導体チップを接着し、上記第
１の半導体チップと第２の半導体チップの各電極をリー
ドフレームのインナーリードに電気的に接続したことを
特徴とする樹脂封止型半導体装置Claim: What is claimed is: 1. A die pad is adhered to an upper surface of a first semiconductor chip, and a second semiconductor chip smaller than the first semiconductor chip is adhered to an upper surface of the die pad. Of the semiconductor chip and the second semiconductor chip are electrically connected to inner leads of a lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18196791A JPH053284A (en) | 1991-06-25 | 1991-06-25 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18196791A JPH053284A (en) | 1991-06-25 | 1991-06-25 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH053284A true JPH053284A (en) | 1993-01-08 |
Family
ID=16109998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18196791A Pending JPH053284A (en) | 1991-06-25 | 1991-06-25 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH053284A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
| US6777264B2 (en) | 2000-03-07 | 2004-08-17 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device having a die pad without a downset |
| TWI384601B (en) * | 2008-05-12 | 2013-02-01 | Advanced Semiconductor Eng | Package structure and method for manufacturing the same |
-
1991
- 1991-06-25 JP JP18196791A patent/JPH053284A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793108A (en) * | 1995-05-30 | 1998-08-11 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit having a plurality of semiconductor chips |
| US6777264B2 (en) | 2000-03-07 | 2004-08-17 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor device having a die pad without a downset |
| TWI384601B (en) * | 2008-05-12 | 2013-02-01 | Advanced Semiconductor Eng | Package structure and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6458625B2 (en) | Multi chip semiconductor package and method of construction | |
| US5620928A (en) | Ultra thin ball grid array using a flex tape or printed wiring board substrate and method | |
| KR100441532B1 (en) | Semiconductor device | |
| US5637828A (en) | High density semiconductor package | |
| US5373188A (en) | Packaged semiconductor device including multiple semiconductor chips and cross-over lead | |
| US20020158318A1 (en) | Multi-chip module | |
| JP2000133767A (en) | Laminated semiconductor package and its manufacture | |
| JP2001313363A (en) | Resin-encapsulated semiconductor device | |
| JPH09312375A (en) | Lead frame, semiconductor device and manufacture thereof | |
| JP2001156251A (en) | Semiconductor device | |
| JPH07153904A (en) | Manufacture of laminar type semiconductor device, and semiconductor package manufactured thereby | |
| US5719748A (en) | Semiconductor package with a bridge for chip area connection | |
| JPH053284A (en) | Resin-sealed semiconductor device | |
| JP3183064B2 (en) | Semiconductor device | |
| JPH0322544A (en) | Semiconductor device | |
| JPH1093013A (en) | Semiconductor device | |
| JPH04144269A (en) | Hybrid integrated circuit device | |
| KR100207902B1 (en) | Multi chip package using lead frame | |
| KR20000040586A (en) | Multi chip package having printed circuit substrate | |
| JP3466354B2 (en) | Semiconductor device | |
| JP3250992B2 (en) | Stacked chip package | |
| JP2990120B2 (en) | Semiconductor device | |
| JPH08279590A (en) | Multi-chip module lsi and method of assembling its package | |
| JPH11111910A (en) | Multichip mount semiconductor device and its manufacture | |
| JPH02180061A (en) | Lead frame and semiconductor device |