JPH08279590A - Multi-chip module lsi and method of assembling its package - Google Patents

Abstract

PURPOSE: To improve packaging of a multi-chip module and to realize the multi-chip module with a small package suitable to high density mounting. CONSTITUTION: Two bare chips 23 and 24 are arranged on both side of a die pad 22 facing each other. A lead 21 connected with the first bare chip 23 is led out from a side of a package mold 27 to the outside as in an ordinary package. A lead 25 connected with the second bare chip 24 is led out from the bottom of the package mold 27. Thus, a multi-chip module LSI having the same surface area and thickness as those of an ordinary single package is realized, and the mountability and functions of the LSI are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module type LSI constituted by sealing a plurality of chips in one package and a package assembling method thereof.

[0002]

2. Description of the Related Art In recent years, new forms of semiconductor packages have been developed one after another in order to meet the demands of electronic devices such as computers such as small size, light weight, high speed, and high function.
There are many types today. As an example of a typical package structure currently used, a 14-pin SOP is used.
(Small Out-line Package) is shown in FIG.

As shown in FIG. 6, the die pad 1
A bare chip 12 is placed on the bare chip 1 and the bare chip 1
Reference numeral 2 is connected to a lead 13 for establishing electrical connection with an external circuit and a bonding wire 14. These die pad 11, bare chip 12, and lead 13
The base body including is sealed by the package mold 15.

The LSI package having such a structure is used by being mounted on the printed circuit board 16 of various electronic devices as shown in FIG.

By the way, in an electronic device such as a computer which is required to have a high function, it is necessary to mount a large number of LSIs on a system board, so that high density mounting is required. In this case, if an LSI having a single chip structure in which one chip as shown in FIG. 6 is accommodated in one package is used, the number of required LSIs increases, which increases the mounting area of the entire computer system. Occurs.

Therefore, recently, a multi-chip module (MC
M) structured LSIs are drawing attention. When a multi-chip module is adopted, the mounting area can be reduced as compared with the case where a plurality of chips are individually packaged and mounted, and the inter-chip delay of signals is reduced, so that the system speed can be increased.

However, since the conventional multi-chip module has a structure in which a plurality of chips are arranged side by side on the base substrate and the chips are connected by using a thin film wiring layer or the like, compared to a single-chip structure LSI, There is a problem that it itself becomes large. In particular, two identical chips are used to increase the memory capacity and the number of gates.
The conventional MCM structure in which these two chips are arranged side by side is unsuitable for high-density mounting when they are housed in a package. This is because, in such a case, wiring between chips is basically unnecessary and it is not necessary to use a thin film wiring layer.

[0008]

As described above, since the conventional multi-chip module has a structure in which a plurality of chips are arranged side by side on a base substrate, the package becomes larger than that of an LSI having a single-chip structure, which is sufficient. There was a drawback that the mounting efficiency could not be increased.

The present invention has been made in view of the above circumstances, and improves the chip arrangement in a multi-chip module and is suitable for high-density mounting in a small package and high-performance multi-chip module type LSI and its package assembly. The purpose is to provide a method.

[0010]

Means and Actions for Solving the Problems
In a multi-chip module type LSI configured by sealing a plurality of chips in one package, a lead frame having a die pad, a first bare chip mounted on the surface of the die pad of the lead frame, A second bare chip mounted on the back surface of the die pad; and a multi-chip structure in which bare chips are arranged on both sides of the die pad.

In this multi-chip module type LSI, two bare chips are arranged facing each other on the front surface and the back surface of the die pad. Therefore, the surface area of the package can be reduced to about 1/2 of that of the conventional structure in which two chips are arranged side by side on the base substrate.

Also, the first bare chip connected to the first bare chip
The lead member is led out to the outside from the side surface of the package as usual, and the second lead member connected to the second bare chip is led to the outside from the bottom surface of the package. It is possible to realize a structure in which leads are arranged for electrical conduction.

By adopting such a lead structure, the thickness of packaging can be made equal to that of a single package. Therefore, a small package and high-performance multi-chip module type LSI can be realized.

Further, it is preferable that the first and second lead members led out to the outside are arranged alternately in the same row along the side edge of the package. With such a lead arrangement, the leads of the entire package can be tested at one time without distinguishing the first lead member led out from the side surface and the second lead member led out from the back surface, and after mounting the components, It becomes possible to facilitate inspection and solder correction.

Further, the LSI of the present invention comprises an insulating member,
A first bare chip arranged on the front surface of the insulating member and connected to the first lead; and a second bare chip arranged on the rear surface of the insulating member and connected to the second lead. Characterize things.

By thus arranging the two chips so as to face each other via the insulating member, even in a tape carrier package having no die pad, the chips can be arranged in multiple layers in the same manner as a plastic package having a die pad.

Further, according to the present invention, in a package assembling method of a multi-chip module type LSI constituted by encapsulating a plurality of chips in one package, a first bare chip is die-bonded on a die pad surface of a lead frame. Then, the inner lead of the lead frame and the first bare chip are wire-bonded, and mold sealing is performed in a state where the region is protected so that resin is not injected into the region near the back surface side of the die pad. The sealed substrate is turned upside down, the second bare chip is die-bonded on the back surface of the die pad, the lead frame is arranged on the substrate, and the inner lead of the lead frame and the second bare chip are arranged. Wire bonding, and apply resin to the area near the back side of the die pad. And performing mold sealing for injecting.

According to this package assembling method, bare chips are arranged on both sides of the die pad only by performing the usual single package assembling steps of die bonding, wire bonding, and mold sealing on the front surface and the back surface of the substrate. The aforementioned multi-chip structure can be easily realized.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Here, a case where the package structure of the multi-chip module type LSI according to the embodiment of the present invention is applied to a 24-pin SOP will be described.

FIG. 1A is a top view of the 24-pin SOP, FIG. 1B is a side view, and FIG. 1C is BB 'of FIG. 1A.
A cross-sectional view taken along the line, and FIG. 1D is C in FIG.
It is sectional drawing which followed the -C 'line.

In this multi-chip module type LSI, as shown in FIGS. 1 (C) and 1 (D), a first bare chip 23 is mounted on the surface of the die pad 22 of the lead frame. A second bare chip 24 is mounted on the back surface of the die pad 22.

The bare chips 23 and 24 are the same chip composed of, for example, a memory chip or a gate array for ASIC.

As shown in FIG. 1C, the first bare chip 23 has an inner lead portion 21a of the lead 21 existing on the same lead frame as the die pad 22.
And a bonding wire 26. The lead 21 is led out to the outside from the side surface of the external package mold 27 as illustrated in order to electrically connect the first bare chip 23 and the printed board. The lead 21 led out to the outside is shaped into a bent gull wing shape as illustrated.

As shown in FIG. 1D, the second bare chip 23 has the inner lead portion 25a of the lead 25 and the bonding wire existing on the second lead frame arranged below the die pad 22. Connected by 28. In order to electrically connect the second bare chip 24 and the printed board, the lead 25 is led out to the outside from the bottom surface of the package mold 27, and extends straight along the bottom extension line of the package mold 27 to the outside. There is.

As described above, the multi-chip module type LSI has a structure in which the two bare chips 23 and 24 are arranged to face each other on the front surface and the back surface of the die pad 22, respectively. Therefore, the surface area of the package can be reduced to about 1/2 of that of the conventional multi-chip module structure in which two chips are arranged side by side on the base substrate.

The leads 21 connected to the first bare chip 23 are led out to the outside from the side surface of the package mold 27, as in the normal SOP structure.
Since the lead 25 connected to the bare chip 24 is led out from the bottom surface of the package mold 27, a lead is arranged on the side surface and the bottom surface of the package mold 27 for electrical connection with the printed circuit board. Has been realized.

With such a lead structure, the thickness of the packaging can be made equal to that of the single package. Therefore, the surface area and thickness are the same as those of a normal single-package 24-pin SOP, and it is possible to realize a multi-chip module type LSI with high mounting efficiency and high functionality.

Further, the leads 21 and 25 led out to the outside
As shown in FIGS. 1 (A) and 1 (B), are arranged alternately along the side edge of the package mold 27 in the same row. Therefore, the seven leads 21 and the seven leads 25 are arranged on one end side of the package mold 27 that constitutes the 24-pin SOP.

As a result, it is possible to realize a simple lead layout without complicatedly routing the leads 25 inside the package mold 27. Furthermore, according to such a lead arrangement, the leads of the entire package can be tested at one time without distinguishing the lead 21 led out from the side surface and the lead 25 led out from the back surface, and the inspection after the component mounting is performed. It is possible to easily correct solder and solder.

In this embodiment, in the lead arrangement in which the leads 21 and 25 are alternately arranged, 14 leads 21 and 25 leads are drawn out at one end of the package mold 27, and It is realized by performing wire bonding with the bare chip 23 every other wire, and wire bonding with the lead 25 and the bare chip 24 every other wire while being shifted by one pitch.

In this case, at the position where the lead 21 is used as a lead (pin) for establishing electrical connection with the printed circuit board (pin position corresponding to the line BB '),
As shown in FIG. 1C, the lead 25 is electrically separated from the bare chip 24 without wire bonding. In addition, the position (C) at which the lead 25 is used as a lead (pin) for establishing electrical conduction with the printed circuit board.
1 (D) at the pin position corresponding to the -C 'line).
As shown in FIG. 4, the lead 21 is now electrically separated from the bare chip 23 without being wire-bonded.

Next, a method of assembling the LSI package shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG.
A lead frame in which the leads 21 and the die pad 22 are integrally formed is arranged on the die A processed as shown in the figure, and then the bare chip 23 separated by dicing is die-bonded on the surface of the die pad 22. To do.

This die bonding process is performed, for example, in the following procedure. That is, first, the paste is applied on the surface of the die pad 22 by a dispenser or the like. Next, the bare chip 23 is attached to the die pad 22.
After being moved up, it is adhered on the surface of the die pad 22 by pressure or the like.

Next, as shown in FIG.
A wire bonding step is performed in which the bonding pad of the bare chip 23 and the lead 21 are connected by a bonding wire 26 made of an ultrafine wire such as aluminum.

Next, as shown in FIG. 2C, the mold B is placed on the mold A to bend the leads 21 as shown in the drawing, and the extra portions of the leads 21 are removed. To cut. After that, resin is injected from the resin injection nozzle to perform mold sealing. In this case, the presence of the mold A located below the die pad 22 prevents the resin from being injected into the periphery of the back surface side of the die pad 22.

Next, as shown in FIG.
After the resin is cured and the mold A is removed, the entire substrate is turned upside down. The die pad 22 located on the upper side
The bare chip 24 is die-bonded on the rear surface of the.

Next, as shown in FIG. 3A, a lead frame including leads 25 preprocessed in the shape as shown is arranged, and the bonding pads of the bare chip 24 and the leads 25 are made of aluminum or the like. The wire bonding step of connecting with the bonding wire 28 made of the ultrafine wire is performed.

After that, as shown in FIG. 3B, the mold C is covered as shown in the figure, and resin is injected from the resin injection nozzle to perform mold sealing. Then, after curing the resin and removing the molds B and C as shown in FIG. 3C, a deburring step is performed.

In this way, the 24-pin SOP having the package structure of FIG. 1 is assembled. According to this package assembling method, bare chips 23 and 24 are arranged on both surfaces of the die pad 22 only by performing the usual single package assembling steps such as die bonding, wire bonding, and mold sealing on the front surface and the back surface of the substrate. The above-mentioned multi-chip structure can be easily realized.

The package structure of FIG. 1 and FIG.
The package assembly method described with reference to FIG.
Not only OP but also various other packages can be similarly applied.

FIG. 4 shows a package structure of the multi-chip module type LSI of FIG.
1 In-line Package). 4A is a top view of the 24-pin DIP, FIG. 4B is a side view, and FIG. 4C is D of FIG. 4A.
It is sectional drawing which followed the -D 'line.

FIG. 5 shows a package structure of the multi-chip module type LSI of FIG.
(Quad Flat Package). 5A is a top view of the 32-pin QFP, FIG. 4B is a side view, and FIG. 4C is a cross-sectional view taken along the line EE ′ of FIG. 4A.

Further, the package structure of FIG. 1 can be applied not only to plastic packages but also to ceramic packages without die pads and tape carrier packages.

In this case, an insulating member is prepared in place of the die pad, the first bare chip is arranged on the surface of this insulating member and connected to the first lead, and the second bare chip is formed on the rear surface of the insulating member. It is sufficient to dispose the bare chip and connect it to the second lead.

[0046]

As described above, according to the present invention, the chip arrangement in the multi-chip module is improved and the two bare chips are arranged opposite to each other on the front surface and the back surface of the die pad, which is suitable for high-density mounting. Small package and high-performance multi-chip module type LSI
Can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a package structure of a multi-chip module type LSI according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a part of the process of assembling the package of the multi-chip module type LSI of the same embodiment.

FIG. 3 is a cross-sectional view for explaining the remaining steps of the package assembling step of the multi-chip module type LSI of the same embodiment.

FIG. 4 is a diagram showing a structure of a DIP to which the package structure of the multi-chip module type LSI of the embodiment is applied.

FIG. 5 is a diagram showing a structure of a QFP to which the package structure of the multi-chip module type LSI of the embodiment is applied.

FIG. 6 is a view showing a package structure of a conventional single package.

FIG. 7 is a diagram showing a state in which the single package of FIG. 6 is mounted on a printed board.

[Explanation of symbols]

21 ... First lead, 22 ... Die pad, 23 ... First bare chip, 24 ... Second bare chip, 25 ... Second lead, 2
6 ... 1st bonding wire, 27 ... Package mold, 28 ... 2nd bonding wire.

Claims (5)

[Claims] 1. A multi-chip module type LSI configured by sealing a plurality of chips in one package, a lead frame having a die pad, and a first frame mounted on the surface of the die pad of the lead frame. And a second bare chip mounted on the back surface of the die pad, and having a multi-chip structure in which bare chips are arranged on both surfaces of the die pad, respectively. 2. A plurality of first lead members connected to the first bare chip and led out from a side surface of the package, and a plurality of first lead members connected to the second bare chip and led out to the outside from a bottom surface of the package. 2. The multi-chip according to claim 1, further comprising: a plurality of second lead members, wherein the leads are arranged on the side surface and the bottom surface of the package for electrical connection with the printed circuit board. Modular LS
I. 3. The first and second lead members led out to the outside are alternately arranged along the side edge of the package in the same row. Multi-chip module type LSI. 4. A multi-chip module type LSI configured by sealing a plurality of chips in one package, wherein an insulating member and an inner portion of the first tape carrier package arranged on the surface of the insulating member. A multi-chip module comprising: a first bare chip connected to a lead; and a second bare chip arranged on a back surface of the insulating member and connected to an inner lead of a second tape carrier package. Type LSI. 5. A method of assembling a multi-chip module type LSI package, comprising a plurality of chips sealed in one package, wherein a first bare chip is die-bonded on a die pad surface of a lead frame, and the lead is formed. The inner lead of the frame and the first bare chip are wire-bonded, and mold sealing is performed in a state in which the region near the back surface side of the die pad is protected from resin injection, and the mold sealing is performed. The base is turned upside down, the second bare chip is die-bonded on the back surface of the die pad, the lead frame is arranged on the base, and the inner lead of the lead frame and the second bare chip are wire-bonded. , For injecting resin into the region near the back surface side of the die pad A method of assembling a package, which comprises: