JP2001127244A - Multichip semiconductor device and method of manufacturing the same - Google Patents

Multichip semiconductor device and method of manufacturing the same

Info

Publication number
JP2001127244A
JP2001127244A JP31051399A JP31051399A JP2001127244A JP 2001127244 A JP2001127244 A JP 2001127244A JP 31051399 A JP31051399 A JP 31051399A JP 31051399 A JP31051399 A JP 31051399A JP 2001127244 A JP2001127244 A JP 2001127244A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
lead frame
multi
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31051399A
Other languages
Japanese (ja)
Inventor
Tomoko Takizawa
朋子 滝澤
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP31051399A priority Critical patent/JP2001127244A/en
Publication of JP2001127244A publication Critical patent/JP2001127244A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PROBLEM TO BE SOLVED: To sufficiently fix a chip at the time of wire bonding in a manufacturing process of a multi-chip package in which two semiconductor chips are stacked one on top of another, and to effectively exert an action of promoting alloy formation by ultrasonic waves. Thus, it is possible to obtain high bonding reliability. SOLUTION: An opening 12 for installing a lower chip 14b is provided in an island 11 portion of a lead frame. The upper chip 14a is fixed with the opening 12 bridged to the island 11 via an adhesive, and wire bonding is performed. The lower chip 14b is fitted into the opening 12 of the island, and the upper chip 14b is
a, and wire bonding is performed on the lower chip 14b (a) and (b). The molding resin 17 is formed by the transfer molding method (c).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-chip module structure in which at least a pair of semiconductor chips are mounted on the same substrate or a lead frame, and a method of manufacturing the same. The present invention relates to a semiconductor device having a structure in which chips are stacked and arranged so that both active element surfaces face upward, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A multi-chip module in which a plurality of bare chips are mounted in the same package is known as one form of a high-density mounting method, and a high-speed operation can be realized by shortening a wiring distance between chips. Therefore, it is widely used for various purposes. FIG. 9 is a cross-sectional view showing the structure of a conventional multichip module in which two semiconductor chips are mounted on the same lead frame. Hereinafter, a conventional multichip semiconductor device and a method of manufacturing the same will be described with reference to FIG. First, the lower chip 14b is fixed on the lead frame island 11 via an adhesive so that the active element surface faces upward. Subsequently, the upper chip 14a mounted on the upper chip 14a is similarly fixed on the lower chip 14b via an adhesive so that the active element surface faces upward. Here, the two semiconductor chips 14a and 14b are rectangular as shown in FIG. 8, and the two semiconductor chips are stacked such that their long sides are orthogonal to each other. After the mounting of the two semiconductor chips is completed, wire bonding is performed. That is,
Bonding pad 1 on semiconductor chips 14a, 14b
5 (see FIG. 8) and inner lead 13 of the lead frame
Are connected by a bonding wire 16.

[0003]

Generally, bonding pads on a semiconductor chip are formed of aluminum,
Au wire is used for the bonding wire.
Then, the two are joined by a thermocompression bonding method. At that time, Al
Ultrasonic vibration is applied to the bonding tool so that alloying of Au and Au is performed favorably (so-called thermocompression bonding using ultrasonic waves). Thus, in the above-described conventional manufacturing process, two adhesive layers are interposed between the upper chip 14a and the island 11, and the fixing of the semiconductor chip 14a is not strong. Furthermore, the upper chip 1
The region where the bonding pad 4a exists protrudes from the lower chip 14b in a cantilever shape. for that reason,
The upper chip, particularly the region where the bonding pad is present, is in a state of being easily vibrated. As a result, the ultrasonic vibration energy of the bonding tool does not effectively act on the metal joint, and the alloying of the joint becomes insufficient, so that reliable wire bonding cannot be performed.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to enable a chip to be firmly fixed at the time of wire bonding so that the vibration energy of ultrasonic waves can be reduced. The present invention is to effectively work for bonding between the bonding wire and the bonding pad, thereby reducing bonding defects between the bonding wire and the bonding pad and improving bonding reliability.

[0005]

The object of the present invention is to provide an opening or a recess for disposing a lower chip on an island or a wiring board of a lead frame, and to bridge the upper chip on the island by bridging the opening or the recess. Alternatively, the problem can be solved by being fixed on the wiring board.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a multichip semiconductor device according to the present invention, at least one of two semiconductor chips having a rectangular planar shape is stacked with an active element surface facing upward and mounted on a lead frame or a wiring board. Wherein an opening or a recess having a rectangular planar shape is formed in the island of the lead frame or the wiring board, the upper chip is mounted on the island or the wiring board across the opening or the recess, and The side chip is arranged in the opening or the recess and is adhered to the back surface of the upper chip.

In the method of manufacturing a multichip semiconductor device according to the present invention, at least one semiconductor chip having a rectangular planar shape is stacked with the active element surface facing upward to form a chip-shaped opening. A method of manufacturing a semiconductor device mounted on a lead frame or a wiring board, comprising: (1) fixing an upper chip to an island of the lead frame or the wiring board by bridging the opening; A) fixing the active element surface of the lower chip to the back surface of the upper chip and disposing the lower chip in the opening; and (3) bonding pads formed on the active element surface of the chip and inner of the lead frame. Connecting a lead or a wiring on a wiring board with a bonding wire.

In another method of manufacturing a multi-chip semiconductor device according to the present invention, there is provided a lead frame or a semiconductor device having at least one semiconductor chip having a rectangular planar shape stacked with the active element surface facing upward and having a recess. A method of manufacturing a semiconductor device mounted on a wiring board,
(1) disposing a lower chip in the recess;
(2) bonding the upper chip to the surface of the lower chip and the island of the lead frame or the wiring substrate by bridging the concave portion with the recess, and (3) forming the active chip surface of the chip. Connecting the bonding pad and the inner lead of the lead frame or the wiring on the wiring board by a bonding wire.

[0009]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIG. 1 is a plan view of a lead frame used in a first embodiment of the present invention. As shown in FIG. 1, a lead frame 10 has four islands suspended at four corners at the center and supported by frame members by leads.
1 and an inner lead 13 extending in all directions from the periphery of the island toward the frame portion. An opening 12 for accommodating a lower chip is formed in the center of the island 11. The opening 12 is formed to have a size into which the lower chip is fitted. FIG. 2 (a),
FIG. 2B is a plan view and a cross-sectional view illustrating one manufacturing process step of the first embodiment. The semiconductor chip used in this embodiment is the one shown in FIG. 8 (the same applies to other embodiments).

As shown in FIGS. 2A and 2B, the upper chip 14a is connected to the island 11 of the lead frame.
Is fixed in a state where the opening 12 is bridged through an adhesive. Next, the bonding pad 16 of the upper chip 14a and the inner lead 13 are connected to each other by the bonding wire 16 which is an Au thin wire by using thermocompression combined with ultrasonic waves. Next, the lower chip 14b having an active element surface coated with an adhesive is fitted into the opening 12 of the island 11,
It is fixed to the back surface of the upper chip 14a. Then, the bonding pads of the lower chip 14b and the inner leads 1
3 is also connected by a bonding wire 16. After that, resin sealing is performed by the transfer molding method,
As shown in FIG. 2C, the upper and lower chips 14a and 14b are sealed with a mold resin 17.

[Second Embodiment] In the first embodiment, the case where the thickness of the semiconductor chip and the thickness of the lead frame are the same is described. However, in the second embodiment,
The semiconductor chip is formed thicker than the lead frame. FIGS. 3A and 3B are cross-sectional views of two orthogonal cross sections showing a state at a manufacturing process stage of the second embodiment. In this embodiment, a recess 18 having a depth equal to the thickness of the chip 14b and capable of accommodating the lower chip 14b is formed in the island 11 of the lead frame. First, the bottom of the recess 18 or the lower chip 14b
An adhesive is applied to the back surface or both of them, and the lower chip 14b is fitted into the recess of the island 11 and fixed.
Subsequently, using an adhesive, the upper side chip 14a is
8 on the lower chip and island 1
1 on. Next, the chips 14a, 14b and the inner leads 13 are connected by bonding wires 16.

3 (a ') and 3 (a ") are sectional views showing a modification of the second embodiment.In the second embodiment, a concave portion 18 having a bottom is formed in an island 11. But
A part or the whole of the concave portion 18 may be removed. FIG.
In the example shown in (a '), a part of the bottom surface of the concave portion is removed, and a concave portion removing hole 19 is opened there. Further, in the example shown in FIG. 3 (a "), the entire concave portion is removed and an opening 12 is provided there. In the example shown in FIG. The chip is fixed by the same method.

Third Embodiment FIG. 4 is a plan view of a wiring board used in a third embodiment of the present invention. As shown in the figure, a wiring substrate 20 uses a polyimide film 21 as a base material, an opening 22 for accommodating a semiconductor chip is opened in the center, and a wiring extending in all directions around the opening 22. 23 are formed. A pad 24 is formed at the outer end of the wiring 23, and a through hole 25 is opened below the pad 24. Sprocket holes 26 are formed on both sides of the polyimide film 21.

FIGS. 5A to 5C are sectional views sequentially showing the manufacturing steps of the third embodiment of the present invention. FIG. 5 (a)
As shown in FIG. 2, the upper chip 14a is
No. 0 is fixed to the polyimide film 21 in a state of bridging the opening 22 via an adhesive. Next, a bonding wire 16 is connected between the bonding pad of the upper chip 14a and the inner end of the wiring 23 by using a thermocompression bonding method with ultrasonic waves. Next, the lower chip 14b having the active element surface coated with an adhesive is attached to the polyimide film 21.
And is fixed to the back surface of the upper chip 14a. After that, the connection between the bonding pad of the lower chip 14b and the inner end of the wiring 23 is also made by a bonding wire. Thereafter, resin sealing is performed by a transfer molding method, and as shown in FIG. 5B, the upper and lower chips 14a and 14b are
7. Next, solder balls 27 are formed on the pad portions of the wirings 23, and then the polyimide film outside the upper mold resin 17 is cut off to obtain the semiconductor device of the present embodiment shown in FIG. Can be

[Fourth Embodiment] FIGS. 6 (a) to 6 (c)
It is sectional drawing which showed the manufacturing process of the 3rd Example of this invention in order. Although the third embodiment uses a flexible film as the base material of the wiring board, a rigid wiring board is used in the present embodiment. As shown in FIG. 6A, the upper chip 14a is connected to the substrate 31 of the wiring substrate 30.
Is fixed in a state where the opening 32 is bridged through an adhesive. Next, the bonding wire 16 is connected between the bonding pad of the upper chip 14a and the inner end portion of the wiring 33 by using the thermocompression bonding method with ultrasonic waves. Next, as shown in FIG. 6B, the lower chip 14b having the active element surface coated with an adhesive is placed in the opening 32 of the substrate 31.
And fixed to the back surface of the upper chip 14a. FIG. 6B is a cross-sectional view taken along a cross section orthogonal to the cross section of FIG. 6A. Subsequently, a portion of the opening 32 that is not embedded in the lower chip 14b is filled with resin by a potting method or the like, and a resin film 34 is formed on the lower surface of the lower chip 14b. Next, the bonding wire 16 is also connected between the bonding pad of the lower chip 14 b and the inner end of the wiring 33. Then, chip 14
A resin film 35 for sealing a and b is formed by a potting method to obtain the semiconductor device of the present embodiment shown in FIG.

[Fifth Embodiment] FIGS. 7 (a) to 7 (c)
It is sectional drawing which showed the manufacturing process of the 5th Example of this invention in order. Also in this embodiment, a rigid wiring board is used. The wiring board is provided with a recess for accommodating the lower chip. Further, a front surface wiring 33a and a rear surface wiring 33b are formed on the wiring substrate 30, and the wirings 33a and 33b on the front and rear surfaces of the substrate are connected via through holes. First, as shown in FIG. 7A, an adhesive is applied to the bottom surface of the concave portion 36 provided on the wiring substrate 30 and / or the back surface of the lower chip 14b.
The lower chip 14b is fitted and fixed in the recess 36.
Subsequently, using an adhesive, the upper side chip 14a is
6 on the lower chip 14b and the substrate 3
1 on. Next, the upper and lower chips 14a, 14b and the inner end of the surface wiring 33a are connected by the bonding wires 16. Then, FIG.
As shown in (b), a molding resin 17 is formed by performing resin sealing by a transfer molding method. Next, the solder ball 27 is formed on the pad portion of the back wiring 33b to obtain the semiconductor device of the present embodiment shown in FIG.

Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the gist of the present invention. For example, the wire bonding for the upper chip and the lower chip may be performed each time each chip is fixed, or may be continuously performed after both chips are fixed. Further, in the embodiment, both the upper and lower chips are rectangular, but it is not always necessary to do so, and it is sufficient that at least one is rectangular.
Further, for the upper chip, the bonding pads may be present not only along two sides of the chip but also along four sides. Further, in the embodiments, the semiconductor device having only one pair of semiconductor chips has been described, but the present invention is also applicable to a semiconductor device having a plurality of pairs of semiconductor chips.

[0018]

As described above, according to the present invention, the upper chip is fixed on the island or the wiring board in such a manner as to bridge the opening or the recess formed in the island or the wiring board. Since wire bonding to the upper chip is performed, wire bonding to the upper chip can be performed in a state where the chip is firmly fixed. Therefore, according to the present invention, it becomes possible to sufficiently apply the ultrasonic vibration to the metal joint at the time of wire bonding, thereby realizing good alloying and improving the bonding reliability.

[Brief description of the drawings]

FIG. 1 is a plan view of a lead frame used in a first embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 3 is a sectional view showing a second embodiment of the present invention and a modified example thereof.

FIG. 4 is a plan view of a wiring board used in a third embodiment of the present invention.

FIG. 5 is a sectional view illustrating a third embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating a fourth embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view illustrating a fifth embodiment of the present invention in the order of steps.

FIG. 8 is a plan view of a semiconductor chip used in an embodiment of the present invention and a conventional example.

FIG. 9 is a sectional view showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Lead frame 11 Island 12 opening 13 Inner lead 14a Upper chip 14b Lower chip 15 Bonding pad 16 Bonding wire 17 Mold resin 18 Depression 19 Depression removal hole 20, 30 Wiring board 21 Polyimide film 22, 32 Opening 23, 33 Wiring 24 Pad 25 Through hole 26 Sprocket hole 27 Solder ball 31 Substrate 33a Surface wiring 33b Back wiring 34 Resin film 35 Resin coating 36 Depression

Claims (10)

    [Claims]
  1. At least one planar shape is a rectangular shape.
    In a multi-chip semiconductor device in which a plurality of semiconductor chips are stacked with an active element surface facing upward and mounted on a lead frame or a wiring board, an opening or a recess having a rectangular planar shape is formed in the island of the lead frame or the wiring board. Is formed, the upper chip is mounted on the island or the wiring board by bridging the opening or the recess, and the lower chip is disposed in the opening or the recess and is adhered to the back surface of the upper chip. A multi-chip semiconductor device, comprising:
  2. 2. An upper chip and a lower chip each have a rectangular planar shape, each chip is provided with a bonding pad along two short sides, and the upper chip and the lower chip have long sides. 2. The multi-chip semiconductor device according to claim 1, wherein the multi-chip semiconductor devices are stacked so as to cross at right angles.
  3. 3. The bonding pads formed on the active element surfaces of the upper and lower chips and the inner leads of the lead frame or the wiring of the wiring board are connected by bonding wires. 3. The multi-chip semiconductor device according to 1 or 2.
  4. 4. The multi-chip semiconductor device according to claim 1, wherein the upper and lower chips are sealed with a potting resin or a mold resin.
  5. 5. The wiring board according to claim 1, wherein a thickness of the wiring board is larger than a chip thickness of the lower chip, and a portion of the opening that is not embedded with the chip is filled with resin. 12. A multichip semiconductor device according to
  6. 6. At least one of the two planar shapes is rectangular.
    A method of manufacturing a multi-chip semiconductor device in which a plurality of semiconductor chips are stacked with an active element surface facing upward and mounted on a lead frame or a wiring board in which a chip-shaped opening is formed; Fixing the chip to the island of the lead frame or the wiring substrate by bridging the opening; and (2) fixing the active element surface of the lower chip to the back surface of the upper chip to open the lower chip to the opening. (3) connecting the bonding pads formed on the active element surface of the chip to the inner leads of the lead frame or the wiring on the wiring board by bonding wires. Of manufacturing a multi-chip semiconductor device.
  7. 7. After the step (1), the step (2)
    Prior to the step, a step of connecting the bonding pads formed on the active element surface of the upper chip with the inner leads of the lead frame or the wiring on the wiring board by bonding wires is inserted. A method for manufacturing a multi-chip semiconductor device according to claim 6.
  8. 8. The method according to claim 6, wherein after the step (2), a step of filling a portion not filled by the lower chip left in the opening with a resin is inserted. 8. The method for manufacturing a multi-chip semiconductor device according to claim 7.
  9. 9. At least one of the two planar shapes is rectangular.
    A method for manufacturing a multi-chip semiconductor device in which a plurality of semiconductor chips are stacked with an active element surface facing upward and mounted on a lead frame or a wiring board having a recess, wherein: (2) bonding the upper chip to the surface of the lower chip and the island of the lead frame or the wiring substrate by bridging the upper chip with the recess, and (3) active chip. Connecting the bonding pad formed on the element surface to the inner lead of the lead frame or the wiring on the wiring board by a bonding wire.
  10. 10. After the step (1), prior to the step (2), the bonding pads formed on the active element surface of the lower chip and the inner leads of the lead frame or on the wiring substrate. 10. The method for manufacturing a multi-chip semiconductor device according to claim 9, wherein a step of connecting with a wiring by a bonding wire is inserted.
JP31051399A 1999-11-01 1999-11-01 Multichip semiconductor device and method of manufacturing the same Pending JP2001127244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31051399A JP2001127244A (en) 1999-11-01 1999-11-01 Multichip semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31051399A JP2001127244A (en) 1999-11-01 1999-11-01 Multichip semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2001127244A true JP2001127244A (en) 2001-05-11

Family

ID=18006143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31051399A Pending JP2001127244A (en) 1999-11-01 1999-11-01 Multichip semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2001127244A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237565A (en) * 2001-02-08 2002-08-23 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US6661091B1 (en) 2002-05-17 2003-12-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2008522397A (en) * 2004-11-26 2008-06-26 イムベラ エレクトロニクス オサケユキチュア Electronic module and manufacturing method thereof
WO2017172010A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Leadframe top-hat multi-chip solution

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237565A (en) * 2001-02-08 2002-08-23 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP4637380B2 (en) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 Semiconductor device
US6661091B1 (en) 2002-05-17 2003-12-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2008522397A (en) * 2004-11-26 2008-06-26 イムベラ エレクトロニクス オサケユキチュア Electronic module and manufacturing method thereof
WO2017172010A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Leadframe top-hat multi-chip solution

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