TWI384601B - Package structure and method for manufacturing the same - Google Patents

Package structure and method for manufacturing the same Download PDF

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Publication number
TWI384601B
TWI384601B TW097117483A TW97117483A TWI384601B TW I384601 B TWI384601 B TW I384601B TW 097117483 A TW097117483 A TW 097117483A TW 97117483 A TW97117483 A TW 97117483A TW I384601 B TWI384601 B TW I384601B
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Taiwan
Prior art keywords
pads
lead frame
package structure
wafer
pad
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TW097117483A
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Chinese (zh)
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TW200947655A (en
Inventor
Kyong-Rok Park
Moon-Gyu Song
Kwun-Joong Kim
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Advanced Semiconductor Eng
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Priority to TW097117483A priority Critical patent/TWI384601B/en
Publication of TW200947655A publication Critical patent/TW200947655A/en
Application granted granted Critical
Publication of TWI384601B publication Critical patent/TWI384601B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A package structure and a method for manufacturing the same. The package structure includes a lead frame, a first chip, a plurality of conductive bumps, a second chip, a plurality of second soldering wires and a sealant. The lead frame has a plurality of first soldering pads and a plurality of second soldering pads. The first and second soldering pads are totally separated from each other. The first chip having a plurality of first conductive pads is disposed on a first surface of the lead frame. The conductive bumps are used for electrically connecting the first conductive pads and the first soldering pads. The second chip having plurality of second conductive pads is disposed on the first chip. The second soldering wires are used for electrically connecting parts of the second conductive pads and the second soldering pads. The sealant seals up the first chip, the second chip, the conductive bumps, the second soldering wires and the lead frame, and exposes a second surface of the lead frame.

Description

封裝結構及其製造方法Package structure and manufacturing method thereof

本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種以導線架承載晶片之封裝結構及其製造方法。The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure for carrying a wafer with a lead frame and a method of fabricating the same.

隨著電子產業的蓬勃發展，半導體封裝技術不斷地進步。一般而言，半導體封裝技術係利用基板承載晶片，並以封膠密封晶片及基板，以避免晶片受潮或因碰撞而損壞。其中，晶片上之電性接點更藉由基板傳導致外界，以便於與印刷電路板電性連接。With the booming electronics industry, semiconductor packaging technology continues to advance. In general, semiconductor packaging technology utilizes a substrate to carry a wafer and seals the wafer and substrate with a sealant to prevent the wafer from being wetted or damaged by collision. The electrical contacts on the wafer are further transmitted to the outside by the substrate to facilitate electrical connection with the printed circuit board.

然而，在電子產品追求「輕、薄、短、小」的潮流下，業界不斷地致力於縮小封裝結構之體積以符合潮流。However, in the pursuit of "light, thin, short, and small" trends in electronic products, the industry is constantly striving to reduce the size of the package structure to meet the trend.

本發明係有關於一種封裝結構及其製造方法，其利用導線架之設計使得封裝結構更符合「輕、薄、短、小」之目標。The invention relates to a package structure and a manufacturing method thereof, which utilizes the design of the lead frame to make the package structure more suitable for the goal of “light, thin, short and small”.

根據本發明之一方面，提出一種封裝結構。封裝結構包括一導線架、一第一晶片、數個導電凸塊、一第二晶片、數條第二銲線及一封膠。導線架具有數個第一銲墊及數個第二銲墊。此些第一銲墊及此些第二銲墊係完全分離。第一晶片設置於導線架之第一表面上，第一晶片具有數個第 一接墊。此些導電凸塊電性連接此些第一接墊及此些第一銲墊。第二晶片設置於第一晶片之上。第二晶片具有數個第二接墊。此些第二銲線電性連接部分之此些第二接墊及此些第二銲墊。封膠密封第一晶片、第二晶片、此些導電凸塊、此些第二銲線及導線架，並裸露導線架之第二表面。According to an aspect of the invention, a package structure is proposed. The package structure comprises a lead frame, a first wafer, a plurality of conductive bumps, a second wafer, a plurality of second bonding wires and a glue. The lead frame has a plurality of first pads and a plurality of second pads. The first pads and the second pads are completely separated. The first wafer is disposed on the first surface of the lead frame, and the first wafer has a plurality of A pad. The conductive bumps are electrically connected to the first pads and the first pads. The second wafer is disposed on the first wafer. The second wafer has a plurality of second pads. The second bonding pads of the second bonding wires are electrically connected to the second pads and the second pads. The sealant seals the first wafer, the second wafer, the conductive bumps, the second bonding wires and the lead frame, and exposes the second surface of the lead frame.

根據本發明之另一方面，提出一種封裝結構之製造方法。半導體封裝方法包括：提供一導線架，導線架具有數個第一銲墊及數個第二銲墊，此些第一銲墊及此些第二銲墊係相互連接。提供第一晶片，第一晶片具有數個第一接墊。設置數個導電凸塊於此些第一接墊上。以此些導電凸塊焊接此些第一接墊及此些第一銲墊。設置一第二晶片於第一晶片上，第二晶片具有數個第二接墊。以數個第二銲線焊接部分之此些第二接墊及此些第二銲墊。以一封膠密封第一晶片、第二晶片、此些導電凸塊、此些第二銲線及導線架，並裸露導線架之第二表面。切割導線架，以使此些第一銲墊及此些二銲墊完全分離。According to another aspect of the present invention, a method of fabricating a package structure is presented. The semiconductor package method includes: providing a lead frame having a plurality of first pads and a plurality of second pads, wherein the first pads and the second pads are connected to each other. A first wafer is provided, the first wafer having a plurality of first pads. A plurality of conductive bumps are disposed on the first pads. The first pads and the first pads are soldered by the conductive bumps. A second wafer is disposed on the first wafer, and the second wafer has a plurality of second pads. The second pads and the second pads are soldered to the plurality of second bonding wires. The first wafer, the second wafer, the conductive bumps, the second bonding wires and the lead frame are sealed with a glue, and the second surface of the lead frame is exposed. The lead frame is cut to completely separate the first pads and the two pads.

為讓本發明之上述內容能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the above-mentioned contents of the present invention more comprehensible, the preferred embodiments are described below, and the detailed description is as follows:

第一實施例First embodiment

請參照第1圖，其繪示本發明第一實施例之封裝結構100之示意圖。封裝結構100包括一導線架(Lead Frame) 130、一第一晶片110、數個導電凸塊140、一第二晶片120、數條第一銲線150、數條第二銲線160及一封膠170。導線架130具有數個第一銲墊131及數個第二銲墊132。第一銲墊131及第二銲墊132係完全分離。第一晶片110設置於導線架130之第一表面130a上。第一晶片110具有數個第一接墊111。導電凸塊140用以電性連接第一接墊111及第一銲墊131。第二晶片120設置於第一晶片110之上，第二晶片120具有數個第二接墊121。第一銲線150電性連接第二接墊121及第一銲墊131。第二銲線160電性連接第二接墊121及第二銲墊132。封膠170密封第一晶片110、第二晶片120、導電凸塊140、第一銲線150、第二銲線160及導線架130，並裸露導線架130之第二表面130b。Please refer to FIG. 1 , which is a schematic diagram of a package structure 100 according to a first embodiment of the present invention. The package structure 100 includes a lead frame (Lead Frame) 130, a first wafer 110, a plurality of conductive bumps 140, a second wafer 120, a plurality of first bonding wires 150, a plurality of second bonding wires 160, and an adhesive 170. The lead frame 130 has a plurality of first pads 131 and a plurality of second pads 132. The first pad 131 and the second pad 132 are completely separated. The first wafer 110 is disposed on the first surface 130a of the lead frame 130. The first wafer 110 has a plurality of first pads 111. The conductive bumps 140 are electrically connected to the first pads 111 and the first pads 131. The second wafer 120 is disposed on the first wafer 110, and the second wafer 120 has a plurality of second pads 121. The first bonding wire 150 is electrically connected to the second pad 121 and the first pad 131. The second bonding wire 160 is electrically connected to the second pad 121 and the second pad 132. The sealant 170 seals the first wafer 110, the second wafer 120, the conductive bumps 140, the first bonding wires 150, the second bonding wires 160, and the lead frame 130, and exposes the second surface 130b of the lead frame 130.

其中，封裝結構100具有一槽孔170c形成於封裝結構100之下表面，槽孔170c係位於第一銲墊131及第二銲墊132之間。換句話說，導線架130具有一貫穿槽孔130c，係貫穿第一表面130a及第二表面130b。貫穿槽孔130c係為中空結構，封膠170覆蓋於貫穿槽孔130c之外，而未填入於貫穿槽孔130c。也就是說，貫穿槽孔130c係為一個無封膠170之凹口。The package structure 100 has a slot 170c formed on the lower surface of the package structure 100, and the slot 170c is located between the first pad 131 and the second pad 132. In other words, the lead frame 130 has a through slot 130c extending through the first surface 130a and the second surface 130b. The through-hole 130c is a hollow structure, and the sealant 170 covers the outside of the through-hole 130c and is not filled in the through-hole 130c. That is, the through slot 130c is a recess without the sealant 170.

請再參照第2圖及第3圖，第2圖繪示第1圖之導線架130之俯視圖，第3圖繪示第1圖之第一晶片110、第二晶片120、導電凸塊140、第一銲線150、第二銲線160及導線架130的俯視圖(在第1圖中，導線架130之圖式 相當於沿第3圖之截面線3-3'之剖面圖)。如第2圖所示，由俯視的角度來看，第一銲墊131係位於導線架130之內側，第二銲墊132則位於導線架130之外側。實質上，第一銲墊131係沿著一第一矩形框線L1排列，第二銲墊132則沿著一第二矩形框線L2排列。並且第一銲墊131及第二銲墊132交錯排列。如第3圖所示，第一銲線150及第二銲線160亦交錯排列。所以如第1圖所示，封裝結構100透過第一銲墊131及第二銲墊132之設計，使得第一銲線150之高度均可低於第二銲線160之高度，可有效避免短路的現象的發生。Referring to FIG. 2 and FIG. 3 again, FIG. 2 is a plan view of the lead frame 130 of FIG. 1 , and FIG. 3 is a first wafer 110 , a second wafer 120 , and a conductive bump 140 of FIG . Top view of the first bonding wire 150, the second bonding wire 160 and the lead frame 130 (in the first figure, the drawing of the lead frame 130) Corresponding to the section along the section line 3-3' of Fig. 3). As shown in FIG. 2, the first pad 131 is located inside the lead frame 130 from the top view, and the second pad 132 is located on the outer side of the lead frame 130. In essence, the first pads 131 are arranged along a first rectangular frame line L1, and the second pads 132 are arranged along a second rectangular frame line L2. And the first pad 131 and the second pad 132 are staggered. As shown in FIG. 3, the first bonding wire 150 and the second bonding wire 160 are also alternately arranged. Therefore, as shown in FIG. 1, the package structure 100 is designed to pass through the first pad 131 and the second pad 132, so that the height of the first bonding wire 150 can be lower than the height of the second bonding wire 160, thereby effectively avoiding short circuit. The occurrence of the phenomenon.

並且，第一銲墊131及第二銲墊132於導線架130之內側與外側交錯排列的設計，亦使得導線架130可容納之銲墊數量大幅增加。Moreover, the design of the first pad 131 and the second pad 132 staggered on the inner side and the outer side of the lead frame 130 also greatly increases the number of pads that the lead frame 130 can accommodate.

再者，採用覆晶接合技術之第一晶片110及採用銲線接合技術之第二晶片120係承載並電性連接於同一導線架130。如此一來，封裝結構100之更符合「輕、薄、短、小」之趨勢。Furthermore, the first wafer 110 using flip chip bonding technology and the second wafer 120 using wire bonding technology are carried and electrically connected to the same lead frame 130. As a result, the package structure 100 is more in line with the trend of "light, thin, short, and small".

以下更以一流程圖及數張示意圖清楚說明本實施例之封裝結構100之製造方法。Hereinafter, the manufacturing method of the package structure 100 of the present embodiment will be clearly described in a flowchart and a plurality of schematic diagrams.

請同時參照第4圖及第5A~5F圖，第4圖繪示本發明第一實施例之封裝結構100之製造方法的流程圖，第5A~5F圖繪示第4圖各步驟之示意圖。首先，如第5A圖所示，在步驟S101中，提供導線架130。如上所述本實施例之導線架130具有數個第一銲墊131及數個第二銲墊 132。而此時之第一銲墊131及第二銲墊132尚未被分離，故第一銲墊131及第二銲墊132仍然相互連接。其中，導線架130具有凹槽133，凹槽133係位於導線架130之第二表面130b且位於第一銲墊131及第二銲墊132之間。其中，本實施例之導線架130係為不具有抗氧化金屬層的銅導線架。Referring to FIG. 4 and FIG. 5A to FIG. 5F, FIG. 4 is a flow chart showing a manufacturing method of the package structure 100 according to the first embodiment of the present invention, and FIGS. 5A to 5F are diagrams showing the steps of the fourth embodiment. First, as shown in FIG. 5A, in step S101, the lead frame 130 is provided. The lead frame 130 of the embodiment has a plurality of first pads 131 and a plurality of second pads as described above. 132. At this time, the first pad 131 and the second pad 132 have not been separated, so the first pad 131 and the second pad 132 are still connected to each other. The lead frame 130 has a recess 133. The recess 133 is located on the second surface 130b of the lead frame 130 and between the first pad 131 and the second pad 132. The lead frame 130 of the embodiment is a copper lead frame that does not have an anti-oxidation metal layer.

接著，再如第5A圖所示，在步驟S102中，提供第一晶片110。第一晶片110之結構如上所述，在此不再重述。Next, as shown in FIG. 5A, in step S102, the first wafer 110 is provided. The structure of the first wafer 110 is as described above and will not be repeated here.

然後，再如第5A圖所示，在步驟S103中，設置導電凸塊140於第一晶片110之第一接墊111上。Then, as shown in FIG. 5A, in step S103, conductive bumps 140 are disposed on the first pads 111 of the first wafer 110.

接著，再如第5A圖所示，在步驟S104中，以導電凸塊140焊接第一接墊111及第一銲墊131。Next, as shown in FIG. 5A, in step S104, the first pads 111 and the first pads 131 are soldered by the conductive bumps 140.

然後，如第5B圖所示，在步驟S105中，設置第二晶片120於第一晶片110上。第二晶片120之結構如上所述，在此不再重述。Then, as shown in FIG. 5B, in step S105, the second wafer 120 is disposed on the first wafer 110. The structure of the second wafer 120 is as described above and will not be repeated here.

接著，如第5C圖所示，在步驟S106中，以第一銲線150焊接部分之第二接墊121及第一銲墊131。Next, as shown in FIG. 5C, in step S106, a portion of the second pads 121 and the first pads 131 are soldered to the first bonding wires 150.

然後，再如第5C圖所示，在步驟S107中，以第二銲線160焊接部分之第二接墊121及第二銲墊132。Then, as shown in FIG. 5C, in step S107, a portion of the second pads 121 and the second pads 132 are soldered to the second bonding wires 160.

接著，如第5D圖所示，在步驟S108中，以封膠170密封第一晶片110、第二晶片120、導電凸塊140、第一銲線150、第二銲線160及導線架130。Next, as shown in FIG. 5D, in step S108, the first wafer 110, the second wafer 120, the conductive bumps 140, the first bonding wires 150, the second bonding wires 160, and the lead frame 130 are sealed with a sealant 170.

然後，如第5E圖所示，在步驟S113中，電鍍抗氧化金屬層180(例如是錫(Sn)或錫-鉛合金(Sn-Pb))於凹 槽133以外之第二表面130b。Then, as shown in FIG. 5E, in step S113, the anti-oxidation metal layer 180 (for example, tin (Sn) or tin-lead alloy (Sn-Pb)) is plated in a concave shape. The second surface 130b other than the groove 133.

接著，如第5F圖所示，在步驟S114中，切割導線架130，以使第一銲墊131及二銲墊132完全分離。切割之後，則同時形成封裝結構100之槽孔170c及導線架130之貫穿槽孔130c。其中，此步驟之係可此用刀具或雷射之方式進行切割。至此即完成了本實施例之封裝結構100。Next, as shown in FIG. 5F, in step S114, the lead frame 130 is cut so that the first pad 131 and the second pad 132 are completely separated. After the cutting, the slot 170c of the package structure 100 and the through slot 130c of the lead frame 130 are simultaneously formed. Among them, this step can be cut by means of a cutter or a laser. Thus, the package structure 100 of the present embodiment is completed.

第二實施例Second embodiment

請同時參照第6圖及第7A~7E圖，第6圖繪示本發明第二實施例之封裝結構200之製造方法的流程圖，第7A~7E圖繪示第6圖之各步驟示意圖。本實施例與第一實施例不同之處在於步驟S201中，本實施例之導線架230係為預電鍍導線架(Pre-Plating Lead Frame，PPF Lead Frame)，此種導線架230已預先電鍍了抗氧化金屬層280，例如是鎳鈀金合金(Ni-Pd-Au)。所以，如第6圖所示，在步驟S108之後，即可直接執行步驟S114，而不需要進行電鍍之步驟，即可形成本實施例之封裝結構200。Please refer to FIG. 6 and FIG. 7A to FIG. 7E. FIG. 6 is a flow chart showing a manufacturing method of the package structure 200 according to the second embodiment of the present invention, and FIGS. 7A-7E are diagrams showing the steps of FIG. The difference between the embodiment and the first embodiment is that in step S201, the lead frame 230 of the embodiment is a Pre-Plating Lead Frame (PPF Lead Frame), and the lead frame 230 is pre-plated. The oxidation resistant metal layer 280 is, for example, a nickel palladium gold alloy (Ni-Pd-Au). Therefore, as shown in FIG. 6, after step S108, step S114 can be directly performed without the step of electroplating, so that the package structure 200 of the present embodiment can be formed.

第三實施例Third embodiment

請同時參照第8圖及第9A~9I圖，第8圖繪示本發明第三實施例之封裝結構300之製造方法的示意圖，第9A~9I圖繪示第8圖之各步驟之示意圖。本實施例與第一實施例不同之處在於步驟S301中，本實施例之導線架330不具有凹槽133，而在第一銲墊131及第二銲墊132之間 係為平整結構。所以，如第8圖所示，本實施例之步驟S309、步驟S310、步驟S311及步驟S312取代了第一實施例之步驟S113。Please refer to FIG. 8 and FIG. 9A to FIG. 9I. FIG. 8 is a schematic diagram showing a manufacturing method of the package structure 300 according to the third embodiment of the present invention, and FIGS. 9A-9I are schematic diagrams showing the steps of FIG. The difference between this embodiment and the first embodiment is that in step S301, the lead frame 330 of the embodiment does not have the recess 133, and is between the first pad 131 and the second pad 132. It is a flat structure. Therefore, as shown in Fig. 8, step S309, step S310, step S311, and step S312 of the present embodiment replace step S113 of the first embodiment.

首先，如9A~9D圖所示，在執行步驟S301～步驟S108之後，封膠170已密封了第一晶片110、第二晶片120、導電凸塊140、第一銲線150、第二銲線160及導線架330，並暴露出第二表面130b。First, as shown in FIG. 9A to FIG. 9D, after performing steps S301 to S108, the sealant 170 has sealed the first wafer 110, the second wafer 120, the conductive bumps 140, the first bonding wires 150, and the second bonding wires. 160 and lead frame 330, and expose the second surface 130b.

接著，如第9E圖所示，在步驟S309中，形成光阻層190於導線架330之第二表面130b。Next, as shown in FIG. 9E, in step S309, a photoresist layer 190 is formed on the second surface 130b of the lead frame 330.

然後，如第9F圖所示，在步驟S310中，圖案化光阻層190，以形成蝕刻開口190a，蝕刻開口190a位於第一銲墊131及第二銲墊132之間。Then, as shown in FIG. 9F, in step S310, the photoresist layer 190 is patterned to form an etch opening 190a, and the etch opening 190a is located between the first pad 131 and the second pad 132.

接著，如第9G圖所示，在步驟S311中，以已圖案化之光阻層190為遮罩，蝕刻導線架330，以形成凹槽133於第一銲墊131及第二銲墊132之間。Next, as shown in FIG. 9G, in step S311, the lead frame 330 is etched by using the patterned photoresist layer 190 as a mask to form the recess 133 in the first pad 131 and the second pad 132. between.

然後，如第9H圖所示，在步驟S312中，電鍍抗氧化金屬層180於凹槽133以外之第二表面130b。Then, as shown in FIG. 9H, in step S312, the oxidation resistant metal layer 180 is plated on the second surface 130b other than the recess 133.

接著，如第9I圖所示，在步驟S114中，切割導線架330，以使第一銲墊131及第二銲墊132完全分離。至此，即完成了本實施例之封裝結構300。Next, as shown in FIG. 9I, in step S114, the lead frame 330 is cut so that the first pad 131 and the second pad 132 are completely separated. So far, the package structure 300 of the present embodiment has been completed.

第四實施例Fourth embodiment

請同時參照第10圖及第11A~11E圖，第10圖繪示本發明第四實施例之封裝結構400之製造方法的流程圖， 第11A~11E圖繪示第10圖之各步驟示意圖。本實施例與第三實施例不同之處在於步驟S401中，本實施例之導線架430係為預電鍍導線架(Pre-Plating Lead Frame，PPF Lead Frame)。此種導線架430已預先電鍍了抗氧化金屬層480，例如是鎳鈀金合金(Ni-Pd-Au)。所以，如第10圖所示，在步驟S108之後，即可直接執行步驟S414，而不需要進行電鍍之步驟，即可完成本實施例之封裝結構400。其中，步驟S414係直接以抗氧化金屬層480為遮罩來蝕刻導線架430，以使第一銲墊131及第二銲墊132完全分離。Referring to FIG. 10 and FIGS. 11A-11E, FIG. 10 is a flow chart showing a method of manufacturing the package structure 400 according to the fourth embodiment of the present invention. 11A to 11E are diagrams showing the steps of the tenth figure. The difference between this embodiment and the third embodiment is that in step S401, the lead frame 430 of the embodiment is a Pre-Plating Lead Frame (PPF Lead Frame). Such a lead frame 430 has been previously electroplated with an oxidation resistant metal layer 480, such as a nickel palladium gold alloy (Ni-Pd-Au). Therefore, as shown in FIG. 10, after step S108, step S414 can be directly performed without performing the electroplating step, and the package structure 400 of the present embodiment can be completed. The step S414 directly etches the lead frame 430 with the anti-oxidation metal layer 480 as a mask to completely separate the first pad 131 and the second pad 132.

第五實施例Fifth embodiment

請參照第12圖，其繪示本發明第五實施例之封裝結構500之導線架530之俯視圖。本實施例與第一實施例不同之處在於導線架530之第一銲墊531與第二銲墊532之排列方式，其餘相同之處不再重述。Referring to FIG. 12, a top view of a lead frame 530 of a package structure 500 according to a fifth embodiment of the present invention is shown. The difference between this embodiment and the first embodiment lies in the arrangement of the first pad 531 and the second pad 532 of the lead frame 530, and the rest of the same points are not repeated.

如第12圖所示，第一銲墊531及第二銲墊532均為長條狀且均由導線架530之邊緣向內延伸。此外，各個第一銲墊係531由導線架530之邊緣向內延伸一第一距離D1，各個第二銲墊532係由導線架530之邊緣向內延伸一第二距離D2，第一距離D1大於第二距離D2。也就是說，第一銲墊531向內延伸至導線架530內側之區域，而第二銲墊532僅延伸至導線架530外側之區域。所以導線架530在封裝的過程中，第一銲墊531及第二銲墊532在封膠170 (繪示於第14E圖中)的範圍內就是完全分離的狀態。As shown in FIG. 12, the first pad 531 and the second pad 532 are both elongated and extend inwardly from the edge of the lead frame 530. In addition, each of the first pads 531 extends inwardly from the edge of the lead frame 530 by a first distance D1, and each of the second pads 532 extends inwardly from the edge of the lead frame 530 by a second distance D2, the first distance D1. Greater than the second distance D2. That is, the first pad 531 extends inwardly to the area inside the lead frame 530, and the second pad 532 extends only to the area outside the lead frame 530. Therefore, in the process of packaging the lead frame 530, the first pad 531 and the second pad 532 are in the sealant 170. The range (shown in Figure 14E) is in a completely separated state.

請同時參照第13圖及第14A~14E圖，第13圖繪示本發明第五實施例之封裝結構500之製造方法的流程圖，第14A~14E圖繪示第13圖之各步驟示意圖。其中，第14A圖～14E圖之導線架530相當於沿第12圖截面線13-13'之剖面圖。如上所述，本實施例與第一實施例在製造方法上不同之處在於步驟S501所提供之導線架530。由於導線架530之第一銲墊531及第二銲墊532在步驟S501已經分離，因此在步驟113之後即可結束本流程，而不需要進行切割之步驟，即可完成本實施例之封裝結構500。Referring to FIG. 13 and FIG. 14A to FIG. 14E, FIG. 13 is a flow chart showing a method of manufacturing the package structure 500 according to the fifth embodiment of the present invention, and FIGS. 14A to 14E are diagrams showing the steps of FIG. Here, the lead frame 530 of Figs. 14A to 14E corresponds to a cross-sectional view taken along line 13-13' of Fig. 12. As described above, the present embodiment differs from the first embodiment in the manufacturing method in the lead frame 530 provided in step S501. Since the first pad 531 and the second pad 532 of the lead frame 530 have been separated in step S501, the process can be ended after step 113, and the package structure of the embodiment can be completed without performing the step of cutting. 500.

第六實施例Sixth embodiment

請同時參照第15圖及第16A~16D圖，第15圖繪示本發明第六實施例之封裝結構600之製造方法的流程圖，第16A~16D圖繪示第15圖之各步驟示意圖。本實施例與第五實施例不同之處在於步驟S601中，本實施例之導線架630係為預電鍍導線架(Pre-Plating Lead Frame，PPF Lead Frame)。此種導線架630已預先電鍍了抗氧化金屬層680，例如是鎳鈀金合金(Ni-Pd-Au)。所以，如第15圖所示，在步驟S108之後，即可直接結束本流程，而不需要進行電鍍之步驟，即可完成本實施例之封裝結構600。Referring to FIG. 15 and FIGS. 16A-16D, FIG. 15 is a flow chart showing a manufacturing method of the package structure 600 according to the sixth embodiment of the present invention, and FIGS. 16A to 16D are diagrams showing the steps of FIG. The difference between this embodiment and the fifth embodiment is that in step S601, the lead frame 630 of the embodiment is a Pre-Plating Lead Frame (PPF Lead Frame). Such lead frame 630 has been pre-plated with an oxidation resistant metal layer 680, such as a nickel palladium gold alloy (Ni-Pd-Au). Therefore, as shown in Fig. 15, after the step S108, the flow can be directly ended without performing the electroplating step, and the package structure 600 of the embodiment can be completed.

第七實施例Seventh embodiment

請參照第17圖，其繪示本發明第七實施例之封裝結 構700之示意圖。本實施例之封裝結構700與第一實施例之封裝結構100不同之處在於導電凸塊740之排列方式，其餘相同之處不再重述。雖然第一實施例之導電凸塊140係以環狀排列方式作說明，然而導電凸塊740亦可以陣列方式排列。所以，由第17圖之剖面可以看到數個導電凸塊740亦設置於第一晶片110之中央區域。導線架730更包括一晶片承座(Die Pad)733，係為於導線架730之中央區域。外圍之導電凸塊740係設置於第一銲墊131上，中央之導電凸塊740係設置於晶片承座733上，並與晶片承座733電性連接。Please refer to FIG. 17, which illustrates a package junction of a seventh embodiment of the present invention. A schematic diagram of the structure 700. The package structure 700 of the present embodiment is different from the package structure 100 of the first embodiment in the arrangement of the conductive bumps 740, and the rest of the same points are not repeated. Although the conductive bumps 140 of the first embodiment are illustrated in a ring-like arrangement, the conductive bumps 740 may also be arranged in an array. Therefore, it can be seen from the cross-section of FIG. 17 that a plurality of conductive bumps 740 are also disposed in the central region of the first wafer 110. The lead frame 730 further includes a die pad 733 which is a central portion of the lead frame 730. The peripheral conductive bumps 740 are disposed on the first pads 131, and the central conductive bumps 740 are disposed on the wafer holders 733 and electrically connected to the wafer holders 733.

本發明上述實施例所揭露之封裝結構及其製造方法具有多項優點，以下僅列舉部分優點說明如下：第一、第一銲墊係位於導線架之內側，第二銲墊則位於導線架之外側。實質上，第一銲墊係沿著一第一矩形框線排列，第二銲墊則沿著一第二矩形框線排列。並且第一銲墊及第二銲墊係交錯排列，第一銲線及第二銲線亦交錯排列。所以封裝結構透過第一銲墊及第二銲墊之設計，使得第一銲線之高度均可低於第二銲線之高度，可有效避免短路的現象的發生。The package structure and the manufacturing method thereof disclosed in the above embodiments of the present invention have a plurality of advantages. The following only some of the advantages are described as follows: first, the first pad is located inside the lead frame, and the second pad is located outside the lead frame . In essence, the first pads are arranged along a first rectangular frame line, and the second pads are arranged along a second rectangular frame line. And the first pad and the second pad are staggered, and the first bonding wire and the second bonding wire are also staggered. Therefore, the design of the package structure through the first pad and the second pad enables the height of the first bonding wire to be lower than the height of the second bonding wire, thereby effectively preventing the occurrence of a short circuit.

第二、第一銲墊及第二銲墊於導線架之內側與外側交錯排列的設計，亦使得導線架可容納之銲墊數量亦可大幅增加。The second, first and second pads are staggered on the inner side and the outer side of the lead frame, and the number of pads that can be accommodated in the lead frame can also be greatly increased.

第三、採用覆晶接合技術之第一晶片及採用銲線接合 之第二晶片係承載並電性連接於同一導線架。如此一來，封裝結構之更符合「輕、薄、短、小」之趨勢。Third, the first wafer using flip chip bonding technology and bonding using wire bonding The second wafer is carried and electrically connected to the same lead frame. As a result, the package structure is more in line with the trend of “light, thin, short, and small”.

綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100、200、300、400、500、600、700‧‧‧封裝結構100, 200, 300, 400, 500, 600, 700‧‧‧ package structure

110‧‧‧第一晶片110‧‧‧First chip

111‧‧‧第一接墊111‧‧‧First mat

120‧‧‧第二晶片120‧‧‧second chip

121‧‧‧第二接墊121‧‧‧second mat

130、230、330、430、530、630、730‧‧‧導線架130, 230, 330, 430, 530, 630, 730‧‧ ‧ lead frame

130a‧‧‧第一表面130a‧‧‧ first surface

130b‧‧‧第二表面130b‧‧‧second surface

130c‧‧‧貫穿槽孔130c‧‧‧through slot

131、531‧‧‧第一銲墊131, 531‧‧‧First pad

132、532‧‧‧第二銲墊132, 532‧‧‧second solder pad

133‧‧‧凹槽133‧‧‧ Groove

140、740‧‧‧導電凸塊140, 740‧‧‧ conductive bumps

150‧‧‧第一銲線150‧‧‧First wire bond

160‧‧‧第二銲線160‧‧‧second welding line

170‧‧‧封膠170‧‧‧Packing

170c‧‧‧槽孔170c‧‧‧ slots

180、280、480、680‧‧‧抗氧化金屬層180, 280, 480, 680‧‧ ‧ anti-oxidation metal layer

190‧‧‧光阻層190‧‧‧ photoresist layer

190a‧‧‧蝕刻開口190a‧‧‧ etching opening

733‧‧‧晶片承座733‧‧‧ wafer holder

L1‧‧‧第一矩形框線L1‧‧‧ first rectangular frame line

L2‧‧‧第二矩形框線L2‧‧‧ second rectangular frame line

第1圖繪示本發明第一實施例之封裝結構之示意圖；第2圖繪示第1圖之導線架之俯視圖；第3圖繪示第1圖之第一晶片、第二晶片、導電凸塊、第一銲線、第二銲線及導線架的俯視圖；第4圖繪示本發明第一實施例之封裝結構之製造方法的流程圖；第5A~5F圖繪示第4圖各步驟之示意圖；第6圖繪示本發明第二實施例之封裝結構之製造方法的流程圖；第7A~7E圖繪示第6圖之各步驟示意圖；第8圖繪示本發明第三實施例之封裝結構之製造方法的流程圖；第9A~9I圖繪示第8圖之各步驟之示意圖；第10圖繪示本發明第四實施例之封裝結構之製造方法的流程圖；第11A~11E圖繪示第10圖之各步驟示意圖；第12圖繪示本發明第五實施例之封裝結構之導線架之俯視圖；第13圖繪示本發明第五實施例之封裝結構之製造方法的流程圖；第14A~14E圖繪示第13圖之各步驟示意圖；第15圖繪示本發明第六實施例之封裝結構之製造方法的流程圖； 第16A~16D圖繪示第15圖之各步驟示意圖；以及第17圖繪示本發明第七實施例之封裝結構之示意圖。1 is a schematic view of a package structure according to a first embodiment of the present invention; FIG. 2 is a plan view of the lead frame of FIG. 1; and FIG. 3 is a first wafer, a second wafer, and a conductive bump of FIG. A top view of the block, the first bonding wire, the second bonding wire and the lead frame; FIG. 4 is a flow chart showing a manufacturing method of the package structure according to the first embodiment of the present invention; and FIGS. 5A-5F illustrate the steps of FIG. FIG. 6 is a flow chart showing a manufacturing method of a package structure according to a second embodiment of the present invention; FIGS. 7A to 7E are diagrams showing steps of FIG. 6; and FIG. 8 is a third embodiment of the present invention; FIG. 9A to FIG. 9I are schematic diagrams showing the steps of the eighth embodiment; and FIG. 10 is a flow chart showing the manufacturing method of the package structure according to the fourth embodiment of the present invention; 11E is a schematic view showing the steps of the 10th embodiment; FIG. 12 is a plan view showing the lead frame of the package structure according to the fifth embodiment of the present invention; and FIG. 13 is a view showing the manufacturing method of the package structure according to the fifth embodiment of the present invention. Flowchart; 14A-14E shows a schematic diagram of each step of FIG. 13; FIG. 15 shows the present invention A flowchart of a method of manufacturing a package structure of a sixth embodiment; 16A to 16D are diagrams showing the steps of the 15th figure; and FIG. 17 is a schematic view showing the package structure of the seventh embodiment of the present invention.

100‧‧‧封裝結構100‧‧‧Package structure

110‧‧‧第一晶片110‧‧‧First chip

111‧‧‧第一接墊111‧‧‧First mat

120‧‧‧第二晶片120‧‧‧second chip

121‧‧‧第二接墊121‧‧‧second mat

130‧‧‧導線架130‧‧‧ lead frame

130a‧‧‧第一表面130a‧‧‧ first surface

130b‧‧‧第二表面130b‧‧‧second surface

130c‧‧‧貫穿槽孔130c‧‧‧through slot

131、531‧‧‧第一銲墊131, 531‧‧‧First pad

132、532‧‧‧第二銲墊132, 532‧‧‧second solder pad

140‧‧‧導電凸塊140‧‧‧Electrical bumps

150‧‧‧第一銲線150‧‧‧First wire bond

160‧‧‧第二銲線160‧‧‧second welding line

170‧‧‧封膠170‧‧‧Packing

170c‧‧‧槽孔170c‧‧‧ slots

180‧‧‧抗氧化金屬層180‧‧‧Antioxidant metal layer

Claims (18)

一種封裝結構，包括：一導線架(Lead Frame)，具有複數個第一銲墊及複數個第二銲墊，該些第一銲墊及該些第二銲墊係完全分離；一第一晶片，設置於該導線架之一第一表面上，該第一晶片具有複數個第一接墊；複數個導電凸塊，電性連接該些第一接墊及該些第一銲墊；一第二晶片，設置於該第一晶片之上，該第二晶片具有複數個第二接墊；複數條第二銲線，電性連接部分之該些第二接墊及該些第二銲墊；以及一封膠，密封該第一晶片、該第二晶片、該些導電凸塊、該些第二銲線及該導線架，並裸露該導線架之一第二表面；其中該封裝結構更具有一槽孔形成於該封裝結構之下表面，該槽孔係位於該些第一焊墊及該些第二焊墊之間，且該槽孔係為未填入該封膠之中空結構。 A package structure includes: a lead frame having a plurality of first pads and a plurality of second pads, the first pads and the second pads being completely separated; a first chip The first wafer has a plurality of first pads; the plurality of conductive bumps are electrically connected to the first pads and the first pads; a second wafer disposed on the first wafer, the second wafer having a plurality of second pads; a plurality of second bonding wires, the second pads of the electrical connection portion and the second pads; And a glue sealing the first wafer, the second wafer, the conductive bumps, the second bonding wires and the lead frame, and exposing a second surface of the lead frame; wherein the package structure further has A slot is formed in a lower surface of the package structure, the slot is located between the first pad and the second pad, and the slot is a hollow structure not filled with the sealant. 如申請專利範圍第1項所述之封裝結構，更包括：複數條第一銲線，電性連接部分之該些第二接墊及該些第一銲墊。 The package structure of claim 1, further comprising: a plurality of first bonding wires, the second pads of the electrical connection portion, and the first pads. 如申請專利範圍第1項所述之封裝結構，其中該些第一銲墊係位於該導線架之內側，該些第二銲墊係位於 該導線架之外側。 The package structure of claim 1, wherein the first pads are located inside the lead frame, and the second pads are located The outside of the lead frame. 如申請專利範圍第1項所述之封裝結構，其中該些第一銲墊及該些第二銲墊均由該導線架之邊緣向內延伸。 The package structure of claim 1, wherein the first pads and the second pads each extend inwardly from an edge of the lead frame. 如申請專利範圍第4項所述之封裝結構，其中各該第一銲墊係由該導線架之邊緣向內延伸一第一距離，各該第二銲墊係由該導線架之邊緣向內延伸一第二距離，該第一距離大於該第二距離。 The package structure of claim 4, wherein each of the first pads extends inwardly from the edge of the lead frame by a first distance, each of the second pads being inwardly from an edge of the lead frame Extending a second distance, the first distance being greater than the second distance. 如申請專利範圍第1項所述之封裝結構，其中該些第一銲墊及該些第二銲墊係交錯排列。 The package structure of claim 1, wherein the first pads and the second pads are staggered. 如申請專利範圍第1項所述之封裝結構，其中該導線架係為一銅導線架。 The package structure of claim 1, wherein the lead frame is a copper lead frame. 如申請專利範圍第1項所述之封裝結構，其中該導線架係為一預電鍍導線架(Pre-Plating Lead Frame，PPF Lead Frame)。 The package structure of claim 1, wherein the lead frame is a Pre-Plating Lead Frame (PPF Lead Frame). 如申請專利範圍第1項所述之封裝結構，其中該導線架更包括：一晶片承座(Die Pad)，該晶片承座與該第一晶片係電性連接。 The package structure of claim 1, wherein the lead frame further comprises: a die pad (Die Pad), the wafer holder being electrically connected to the first chip. 一種封裝結構之製造方法，包括：提供一導線架(Lead Frame)，該導線架具有複數個第一銲墊及複數個第二銲墊，該些第一銲墊及該些第二銲墊係相互連接；提供一第一晶片，該第一晶片具有複數個第一接墊； 設置複數個導電凸塊於該些第一接墊上；以該些導電凸塊電性連接該些第一接墊及該些第一銲墊；設置一第二晶片於該第一晶片上，該第二晶片具有複數個第二接墊；以複數個第二銲線電性連接部分之該些第二接墊及該些第二銲墊；以一封膠密封該第一晶片、該第二晶片、該些導電凸塊、該些第二銲線及該導線架，並裸露該導線架之一第二表面；以及分離該些第一銲墊及該些第二銲墊。 A manufacturing method of a package structure includes: providing a lead frame having a plurality of first pads and a plurality of second pads, the first pads and the second pads Connected to each other; providing a first wafer, the first wafer having a plurality of first pads; a plurality of conductive bumps are disposed on the first pads; the conductive bumps are electrically connected to the first pads and the first pads; and a second wafer is disposed on the first pads, The second wafer has a plurality of second pads; the second pads and the second pads are electrically connected to the plurality of second bonding wires; the first wafer and the second are sealed with a glue a first surface of the lead frame, and the first conductive pad and the second bonding pads are separated from the second conductive surface of the lead frame and the second conductive wire and the second conductive wire. 如申請專利範圍第10項所述之封裝結構之製造方法，更包括：以複數個第一銲線電性連接部分之該些第二接墊及該些第一銲墊。 The method for manufacturing a package structure according to claim 10, further comprising: electrically connecting the plurality of first bonding wires to the second pads and the first pads. 如申請專利範圍第10項所述之封裝結構之製造方法，其中在提供該導線架之步驟中，該導線架具有一凹槽，該凹槽係位於該導線架之該第二表面且位於該些第一銲墊及該些第二銲墊之間。 The method of manufacturing a package structure according to claim 10, wherein in the step of providing the lead frame, the lead frame has a recess, the recess being located on the second surface of the lead frame and located at the Between the first pads and the second pads. 如申請專利範圍第12項所述之封裝結構之製造方法，其中在以該封膠密封該導線架之步驟中，該封膠更密封該凹槽。 The method of manufacturing a package structure according to claim 12, wherein in the step of sealing the lead frame with the sealant, the sealant seals the groove more. 如申請專利範圍第13項所述之封裝結構之製造方法，其中在提供該導線架之步驟中，該導線架係為銅導 線架，在以該封膠密封該導線架之步驟之後，該封裝結構之製造方法更包括：電鍍一抗氧化金屬層於該第二表面。 The manufacturing method of the package structure according to claim 13, wherein in the step of providing the lead frame, the lead frame is a copper guide The wire rack, after the step of sealing the lead frame with the sealant, the manufacturing method of the package structure further comprises: plating an anti-oxidation metal layer on the second surface. 如申請專利範圍第10項所述之封裝結構之製造方法，其中在提供該導線架之步驟中，該第一銲墊及該第二銲墊之間係為平整的結構。 The method of manufacturing a package structure according to claim 10, wherein in the step of providing the lead frame, the first pad and the second pad are formed in a flat structure. 如申請專利範圍第15項所述之封裝結構之製造方法，其中在以該封膠密封該導線架之步驟之後，該封裝結構之製造方法更包括：形成一光阻層於該導線架之該第二表面；圖案化該光阻層，以形成一蝕刻開口，該蝕刻開口位於該第一銲墊及該第二銲墊之間；以已圖案化之該光阻層為遮罩，蝕刻該導線架，以形成一凹槽於該些第一銲墊及該些第二銲墊之間；以及電鍍一抗氧化金屬層於該第二表面。 The manufacturing method of the package structure of claim 15, wherein after the step of sealing the lead frame with the sealant, the method of manufacturing the package structure further comprises: forming a photoresist layer on the lead frame a second surface; patterning the photoresist layer to form an etch opening between the first pad and the second pad; masking the patterned photoresist layer, etching the a lead frame to form a recess between the first pads and the second pads; and plating an anti-oxidation metal layer on the second surface. 如申請專利範圍第10項所述之封裝結構之製造方法，其中在提供該導線架之步驟中，該導線架係為一預電鍍導線架(Pre-Plating Lead Frame，PPF Lead Frame)。 The manufacturing method of the package structure according to claim 10, wherein in the step of providing the lead frame, the lead frame is a Pre-Plating Lead Frame (PPF Lead Frame). 如申請專利範圍第10項所述之封裝結構之製造方法，其中分離該些第一銲墊及該些第二銲墊之步驟係利用一刀具進行切割。 The manufacturing method of the package structure according to claim 10, wherein the step of separating the first pads and the second pads is performed by using a cutter.
TW097117483A 2008-05-12 2008-05-12 Package structure and method for manufacturing the same TWI384601B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH053284A (en) * 1991-06-25 1993-01-08 Sony Corp Resin-sealed semiconductor device
TW495945B (en) * 2001-10-18 2002-07-21 Chipmos Technologies Inc Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame
JP2004200683A (en) * 2002-12-16 2004-07-15 Samsung Electronics Co Ltd Multi-chip package
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH053284A (en) * 1991-06-25 1993-01-08 Sony Corp Resin-sealed semiconductor device
TW495945B (en) * 2001-10-18 2002-07-21 Chipmos Technologies Inc Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame
JP2004200683A (en) * 2002-12-16 2004-07-15 Samsung Electronics Co Ltd Multi-chip package
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof

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