TW495945B - Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame - Google Patents
Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame Download PDFInfo
- Publication number
- TW495945B TW495945B TW90125994A TW90125994A TW495945B TW 495945 B TW495945 B TW 495945B TW 90125994 A TW90125994 A TW 90125994A TW 90125994 A TW90125994 A TW 90125994A TW 495945 B TW495945 B TW 495945B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- semiconductor packaging
- patent application
- scope
- lead
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
495945 五、發明說明（1) 【發明領域】 本發明係有關於一種半導 有關於-種防止導線架外5丨腳方f ㈣ 導體封裝方法。 \生彡貞日日（Whisker )之半 【先前技術】 在半導體封裝過程中，羽 片，導線架之材料常 1以導線架承載半導體晶 合金及合金42，電^夕卜電性之金屬’如銅、銅 錫、錄、把或金…等，其中其材料係可為 的焊接潤濕性，且豆材料成1 =錫合金的金屬具有較佳 m 錫或錫合金，但由於錫之電鑛層會 時間產生皁晶針狀之鬚晶（whisker)，常造成電性 曰故丄 喊右在錫中加入部份鉛量，即可防止鬚 日日發生，然而鉛是一種具毒性金 媢 M a l α 隻屬 雖錫錯合金可解決 :::發生之問題，但不符合在將來半導體封 化電鍍之趨勢。 Υ…鈍 人:^美國專利案第6,087,71 2號「增進潤濕性之鍍錫 柯夕道说如/ , 揭不一種此增進潤濕 »·生之導線条（lead frame)，其係在導線架之外引腳鍍上 一層錫合金’使該導線架具有抗高溫及高潤濕性 (wettability )等特性，而該導線架之電鍍過程依序如 下：一、提供一導線架，該導線架之金屬材料係為銅、銅 合金或錄合金’其係具有複數個晶墊、内引腳及外引腳， 二、將該導線架之晶墊及内引腳鍍上一層銀，以增進其導495945 V. Description of the invention (1) [Field of the invention] The present invention relates to a semiconducting method and a method for preventing a lead frame outside a lead frame from forming a conductor. \ Secret half of Whisker [Previous technology] In the semiconductor packaging process, the material of the feather and the lead frame is often used to carry the semiconductor crystal alloy and alloy 42 with the lead frame, which is an electrical metal. Such as copper, copper-tin, copper, gold, etc., where the material is a solderable wettability, and the soybean material is 1 = a tin alloy. The metal has a better m tin or tin alloy, but due to the electrical properties of tin The mineral layer will produce soap crystal needle-like whiskers (whisker) over time, often causing electrical failures. If you add some lead to tin, you can prevent it from happening every day. However, lead is a toxic gold tincture. M al α is only a problem that tin alloy can solve :::, but it does not meet the trend of semiconductor encapsulation and plating in the future. Υ ... blunt people: ^ US Patent No. 6,087,71 2 "Tin plating Ke Xidao that promotes wettability says / /, does not reveal a lead frame that promotes wettability." Plating a layer of tin alloy on the lead outside the lead frame makes the lead frame resistant to high temperature and high wettability, and the plating process of the lead frame is as follows: 1. Provide a lead frame, the The metal material of the lead frame is copper, copper alloy or recording alloy. It has a plurality of crystal pads, inner pins and outer pins. 2. The crystal pads and inner pins of the lead frame are plated with silver to Improve its guidance
495945 五、發明說明（2) 電性，三、將該導線架之外引腳鑛上一層耐壓模高溫之錫 合金，如錫銻合金及錫銻鉛合金，使該導線架具有抗高 溫、防氧化或侵触及高焊接潤濕性（sο 1 de r we 11 ab i 1 i t y 等特性，四、將晶片黏固於晶墊上，並電性連接晶片^ 内引腳，五、以封膠體密封晶片、晶墊及内引腳。Μ 發 曰曰 在上述之導線架電鍍過程所使用之錫銻合金，其具有 抗高溫、防氧化或侵蝕及高潤濕性等特性，使其易於^面 接合（surface mounting)至印刷電路板（print circuit board，PCB)上，但仍未能述及如何解決鬚 生之問題。 、 【發明目的及概要】 為了解決上述問題，本發明之主要目的在於提供一種 半導體封裝方法，其係以通有非活性氣體之迴焊爐加熱一 含錫金屬層之導線架，以防止在導線架外引腳發生鬚晶。 該半導體封裝方法係適用於QFP、S〇p…等封裝結構， 其係在一導線架上封裝複數個半導體晶片後，再將該導線 架之外引腳表面電鍍金屬層，如錫或錫合金，然後以通有 非活性氣體之迴焊爐加熱該金屬層，以消除該金屬層與外 引腳之，，金屬應力，最後切割導線架，該金屬層係具有 杈佳的抗氧化及焊接潤濕性，故本發明能提供良好的抗氣 化、易於表面接合並具有防止鬚晶之發生等功效。 【發明詳細說明】 "月參閱所附圖式，本發明將列舉以下之實施例說明： 本發明之防止導線架外引腳發生鬚晶（whisker )之 495945 五、發明說明（3) ίΠΤ法’如第1圖所示，該半導體封裝方法依序 為&供—導線架110、執行半導體封裝12G、電鑛導線架 130、加熱導線架140及切割導線架15〇，而在本發明之一 具體實施例中，第2a圖至第2e圖係為該半導體封Χ裝方法之 過程示意圖。 首先如第1及2a圖所示，首先進行「提供一導線架」 110，該導線架240之材料係為具高導電性之金屬，如銅、 銅合金、+金42及其它合金···等，其係具有複數個内引腳 241 (inner lead)、外引腳242 (〇uter lead)及支撐條 243 (dam bar )，其中該内引腳241係供内部電性連接至 晶片21 0，該外引腳242係供外部電性連接至印刷電路板 (圖未繪出），而該支撐條243係在封裝時用以定位外引 腳242。 再如第1及2b圖所示，「執行半導體封裝」120，其係 以導線架2 4 0作為複數個晶片21 〇封裝之承載體，晶片2 1 〇 之上表面係以黏性膠f230黏固於内引腳241之下表面，以 开> 成L 0 C ( 1 e a d ο n c h i p )之内部構襄型態，然後以習知 之打線（wire bonding )技術，將金屬導線25〇電性連接 晶片210與内引腳241，再利用習知之壓模（m〇lding )或 其他方法構成複數個封膠體2 2 0，以密封晶片2 1 〇 '内引腳 241及金屬導線2 5 0。 之後’如第1及2c圖所示，進行「電鍍導線架」13〇， 將裸露於封膠體220外之導線架240之外引腳242表面電鍍 一層金屬層260，該金屬層260之材料係為錫或錫合金，其495945 V. Description of the invention (2) Electrical properties. 3. Put a layer of high-temperature-resistant tin alloy such as tin-antimony alloy and tin-antimony-lead alloy on the lead ore outside the lead frame to make the lead frame resistant to high temperature, Anti-oxidation or interference with high solder wettability (sο 1 de r we 11 ab i 1 ity, etc.) Fourth, the chip is fixed on the crystal pad, and the chip is electrically connected to the inner lead of the chip ^ 5. Sealed with a sealing compound Wafers, wafer pads and inner pins. M hair said that the tin-antimony alloy used in the above-mentioned lead frame electroplating process has the characteristics of high temperature resistance, oxidation resistance or erosion, and high wettability, making it easy to bond. (Surface mounting) to a printed circuit board (print circuit board, PCB), but it still fails to describe how to solve the problem. [Objective and Summary of the Invention] In order to solve the above problems, the main object of the present invention is to provide a Semiconductor packaging method, which uses a reflow furnace with inert gas to heat a lead frame containing a tin metal layer to prevent whiskers from occurring outside the lead frame. This semiconductor packaging method is applicable to QFP, Soop … And so on After a plurality of semiconductor wafers are packaged on a lead frame, a metal layer, such as tin or a tin alloy, is plated on the surface of the leads outside the lead frame, and then the metal layer is heated in a reflow furnace with inert gas. In order to eliminate the metal layer and the outer pins, metal stress, and finally cut the lead frame, the metal layer has good oxidation resistance and welding wettability, so the invention can provide good anti-gasification and easy surface Bonding and has the effect of preventing the occurrence of whiskers. [Detailed description of the invention] " Refer to the attached drawings, the present invention will enumerate the following embodiments to explain: The present invention prevents whiskers from occurring on the outer leads of the lead frame. 495945 V. Description of the invention (3) As shown in Fig. 1, the semiconductor packaging method is in order: & supply-lead frame 110, performing semiconductor package 12G, electric mine lead frame 130, heating lead frame 140 and The lead frame 15 is cut, and in a specific embodiment of the present invention, FIGS. 2a to 2e are schematic diagrams of the process of the semiconductor packaging and packaging method. As shown in FIGS. 1 and 2a, first, “provide A lead frame 110, the material of the lead frame 240 is a highly conductive metal, such as copper, copper alloy, + gold 42 and other alloys, etc., which has a plurality of inner leads 241 (inner lead ), An outer pin 242 (〇uter lead) and a support bar 243 (dam bar), wherein the inner pin 241 is used for internal electrical connection to the chip 210, and the outer pin 242 is used for external electrical connection to the printing Circuit board (not shown), and the support bar 243 is used to position the outer pins 242 during packaging. As shown in Figures 1 and 2b, the "executive semiconductor package" 120 is a lead frame 2 4 0 is a carrier of a plurality of wafers 21 〇 package, the upper surface of the wafer 2 1 〇 is fixed to the lower surface of the inner pin 241 with an adhesive f230 to open L 0 C (1 ead ο nchip) The internal structure is used, and then the metal wire 25 is electrically connected to the chip 210 and the inner pin 241 by the conventional wire bonding technology, and then the conventional mold (molding) or other methods are used to form a plurality. Each sealant 2 2 0 is used to seal the inner lead 241 and the metal wire 2 5 0 of the chip 2 1 0 ′. Afterwards, as shown in Figures 1 and 2c, a "plating lead frame" 13 is performed, and a metal layer 260 is plated on the surface of the lead 242 exposed on the lead frame 240 outside the sealing compound 220. The material of the metal layer 260 is Is tin or tin alloy, which
第7頁 495945Page 7 495945
係用以保護導線架240之外引腳242免因外界環境因素（如 濕氣…等）而產生氧化或腐蝕，同時亦提供半導體封裝姓 構200在上板（mounting)時，對印刷電路板上之焊膏、'° 〔solder paste〕有良好之焊接溼潤性（s〇lder 月 wettability) 〇It is used to protect the lead 242 outside the lead frame 240 from oxidation or corrosion due to external environmental factors (such as moisture ...), and also provides the semiconductor package structure 200 to the printed circuit board during mounting. The solder paste and '° [solder paste] have good solder wettability.
然後，如第1及2d圖所示，進行「加熱導線架」14〇， 將封裝在一導線架240上之複數個半導體封裝結構2〇〇放 於具有供氣裝置310之迴焊爐内’該供氣裝置31〇係供岸非 活性氣體（mert gas )至該迴焊爐内，該非活性氣體係 為氮氣，亦可為氬氣、氖氣或氬氖混合氣…等，再以該迴 焊爐之加熱裝置300對該金屬層260進行熱處理，其加=、、w 度係為18(TC至220 °C左右，可維持30秒至5分名童，此時^ 引腳242之材料金屬（如銅…等）與金屬層26〇之材料金屬 (如錫…等）之間會產生金屬擴散，即可使該金屬層26() 與外引腳242金屬界面處形成鋼錫合金，該經加埶迴焊 (ref low )後之金屬層260係可消除其與外引腳242之間的 金屬應力’而能防止鬚晶（whisker)發生。 接著，如第1及2e圖所示，進行「切割導線架」丨5〇， 其係包含單離（singular izing )、修剪（trimming )及Then, as shown in Figs. 1 and 2d, "heating the lead frame" 14 is performed, and a plurality of semiconductor packaging structures 200 packaged on a lead frame 240 are placed in a reflow furnace with a gas supply device 310 ' The gas supply device 31 is a shore supply inert gas (mert gas) into the reflow furnace. The inert gas system is nitrogen, argon, neon or argon-neon mixed gas, etc. The heating device 300 of the welding furnace performs heat treatment on the metal layer 260, and the temperature of the metal layer 260 is 18 (TC to 220 ° C, which can be maintained for 30 seconds to 5 minutes. At this time, the material of pin 242 Metal (such as copper ...) and metal material of the metal layer 26 (such as tin ...) will cause metal diffusion, so that the metal layer 26 () and the outer lead 242 metal interface to form a steel-tin alloy, The refractory metal layer 260 can eliminate the metal stress between the metal layer 260 and the outer pin 242 and prevent whiskers from occurring. Then, as shown in Figs. 1 and 2e ， "Cutting the lead frame" 丨 50, which includes singular izing, trimming, and
彎折（bending)…等步驟，其中單離係將封裝在—導線 架240上之複數個半導體封裝結構2 00切割成單一的封裝單 元’然後去除導線架240之支撐條243，再把裸露於封膠體 220外之外引腳242彎折成I型腳（i-lead )、】型腳 / (J-lead)或搞翼腳（gUu Wing)，使該半導體封裝結Bending ... and other steps, in which the single separation system cuts the plurality of semiconductor packaging structures 2000 on the lead frame 240 into a single packaging unit ', and then removes the support bar 243 of the lead frame 240, and then exposes it to The pins 242 outside the sealing compound 220 are bent into an I-lead, a J-lead or a gUu Wing, so that the semiconductor package is bonded.
495945 五、發明說明（5) 構2 0 0可藉由外引腳242表面接合至印刷電路板（圖未繪出 )…等。 本發明係可運用於引腳在晶片上（lead 〇n chip, LOC)、晶片在引腳上〔chip on lead, COL〕、四方扁平 (quad flat package，QFP)、四方扁平i型外引腳 (quad flat I-leaded，QFI)、四方扁平j型外引腳 (quad flat J - leaded，QF J )、小型化構裝（smal i outline package, SOP ) 、 _ out 1 ine I-leaded，SOI )、小型化構裝j型外引腳 (small outline J - leaded，S0J)或超薄小型化構裝 (thin small outline package, TSOP ) ···等具外弓丨腳式 之封裝結構’甚至亦可適用於四方扁平無外引腳式Uuad flat non - leaded，QFN)或小型化無外引腳式（smaU outline non-leaded，SON)等封裝結構無外引腳之封裝 結構，在一導線架上封裝複數個半導體晶片後，將該導線 架之外引腳表面電鍍金屬層，然後以通有非活性氣體（如 氮氣…等）之迴焊爐加熱該金屬層30秒至5分鐘（溫度係 為180°C至22(TC左右時）’使該金屬層與外弓…金皿屬又界面 處形成銅錫合金，故在該金屬層之間已有效降低其盥引 腳間的金属應力，而能防止鬚晶發生，且該金屬声^ 係為錫或錫合I (因錫的金屬材料成本最低且純：易於電 鍍）’其具有較佳的抗氧化及焊接潤濕性， 提供良好的抗氧化、易於表面接合並具晶。： 等功效。 須日日I心生495945 V. Description of the invention (5) The structure 200 can be bonded to the printed circuit board through the surface of the outer pin 242 (not shown in the figure) ... and so on. The present invention is applicable to lead on chip (LOC), chip on lead (COL), quad flat package (QFP), and quad flat i-type outer pins (quad flat I-leaded (QFI)), quad flat J-lead (QF J), smal i outline package (SOP), _ out 1 ine I-leaded, SOI ), Small outline J-lead (S0J) or ultra-thin small outline package (TSOP), etc .... It can also be applied to packaging structures without external pins such as quadruple flat non-lead (QFN) or smaU outline non-leaded (SON). After a plurality of semiconductor wafers are packaged on the rack, a metal layer is electroplated on the surface of the leads outside the lead frame, and then the metal layer is heated in a reflow furnace with inert gas (such as nitrogen ...) for 30 seconds to 5 minutes (temperature The temperature is 180 ° C to 22 (at about TC) 'Make the metal layer and the outer bow ... the place where the gold plate belongs It becomes a copper-tin alloy, so the metal stress between the toilet pins has been effectively reduced between the metal layers, and whiskers can be prevented from occurring, and the metal sound is tin or tin I (due to the cost of metal materials of tin) Lowest and pure: easy to electroplating) 'It has better oxidation resistance and welding wettability, provides good oxidation resistance, easy surface bonding and crystalline .: Efficacy.
495945 五、發明說明（6) 故本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍0495945 V. Description of the invention (6) Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. Any person skilled in the art may make any changes and modifications without departing from the spirit and scope of the present invention. Modifications belong to the protection scope of the present invention. 0
第10頁 495945 圖式簡單說明 【圖 式 說 明 ] 第1 圖 依 本發 明 之防 止導線架 外 引腳發 生 鬚 晶 之 半 導 體 封 裝方 法 之流 程圖， 第2a 圖 • 依 本發 明 之一 具體實施 例 ，所提 供 導 線 架 之 頂 面 圖 第2b 圖 依 本發 明 之一 具體實施 例 5 Γ執 行 半 導 體 封 裝 j 後 之截 面 圖； 第2c 圖 依 本發 明 之一 具體實施 例 ，「電 鍍 導 線 架 j 後 之 截 面圖 ， 第2d 圖 • 依 本發 明 之一 具體實施 例 ’ Γ加 熱 導 線 架 j 後 之 截 面圖 ； 及 第2e 圖 ； 依 本發 明 之一 具體實施 例 ，Γ切 割 導 線 架 j 後 之 截 面圖 〇 【圖 號 說 明 ] 110 提 供 一 導線 架 120 執行 半 導 體 封 裝 130 電 鍍 導 線架 140 加 熱 導 線 架 150 切 割 導 線架 200 半 導 體 封裝 結 構 210 晶 片 220 封膠體 230 黏 性 膠 帶 240 引 腳 241 内 引 腳 242 外引腳 243 支撐 條 250 金 屬 導 線 260 金屬層 300 加 教 $ 裝 置 310 供氣裝置Page 10 495945 Brief description of the drawings [Explanation of the drawings] Figure 1 is a flowchart of a method for semiconductor packaging of whiskers outside the lead frame in accordance with the present invention. Figure 2a • According to a specific embodiment of the present invention, The top view of the provided lead frame. FIG. 2b is a cross-sectional view of a semiconductor package j according to a specific embodiment 5 of the present invention. FIG. 2c is a cross-sectional view of a lead frame j according to a specific embodiment of the present invention. Figure, Figure 2d • Sectional view after heating lead frame j according to a specific embodiment of the present invention; and Figure 2e; Sectional view after cutting lead frame j according to a specific embodiment of the present invention. [Illustration of drawing number] 110 Provide a lead frame 120 Carry out semiconductor package 130 Plating lead frame 140 Heating lead frame 150 Cut lead frame 200 Semiconductor seal Mounting structure 210 wafer 220 sealing gel 230 adhesive tape 240 lead pin 241 inner pin 242 outer pin 243 support bar 250 metal guide wire 260 metal layer 300 plus teaching $ installation 310 gas supply device
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW90125994A TW495945B (en) | 2001-10-18 | 2001-10-18 | Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW90125994A TW495945B (en) | 2001-10-18 | 2001-10-18 | Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW495945B true TW495945B (en) | 2002-07-21 |
Family
ID=21679554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW90125994A TW495945B (en) | 2001-10-18 | 2001-10-18 | Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW495945B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7316064B2 (en) | 2005-08-26 | 2008-01-08 | Tyco Electronics Corporation | Induction reflow apparatus and method of using the same |
| TWI384601B (en) * | 2008-05-12 | 2013-02-01 | Advanced Semiconductor Eng | Package structure and method for manufacturing the same |
-
2001
- 2001-10-18 TW TW90125994A patent/TW495945B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7316064B2 (en) | 2005-08-26 | 2008-01-08 | Tyco Electronics Corporation | Induction reflow apparatus and method of using the same |
| TWI384601B (en) * | 2008-05-12 | 2013-02-01 | Advanced Semiconductor Eng | Package structure and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI291756B (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
| CN104103603B (en) | Semiconductor device and semiconductor module | |
| US6506625B1 (en) | Semiconductor package having stacked dice and leadframes and method of fabrication | |
| US8836101B2 (en) | Multi-chip semiconductor packages and assembly thereof | |
| TWI295846B (en) | Semiconductor device having post-mold nickel/palladium/gold plated leads | |
| US9666501B2 (en) | Semiconductor device including a lead frame | |
| US9059185B2 (en) | Copper leadframe finish for copper wire bonding | |
| TWI405274B (en) | Clipless and wireless semiconductor die package and method for making the same | |
| US7462926B2 (en) | Leadframe comprising tin plating or an intermetallic layer formed therefrom | |
| US7309909B2 (en) | Leadframes for improved moisture reliability of semiconductor devices | |
| KR20040008827A (en) | Method for manufacturing dual die package | |
| US20080014757A1 (en) | Leadframes for Improved Moisture Reliability and Enhanced Solderability of Semiconductor Devices | |
| US20090189261A1 (en) | Ultra-Thin Semiconductor Package | |
| JP2009526381A (en) | Aluminum lead frame for semiconductor QFN / SON devices | |
| US20080012101A1 (en) | Semiconductor Package Having Improved Adhesion and Solderability | |
| JPH04115558A (en) | Lead frame for semiconductor device | |
| JP3470111B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| US9553068B2 (en) | Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer | |
| JP2023030046A (en) | Semiconductor device and method for manufacturing the same | |
| US10325838B2 (en) | Semiconductor device fabricated by flux-free soldering | |
| TW495945B (en) | Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame | |
| US20040183166A1 (en) | Preplated leadframe without precious metal | |
| JP3716101B2 (en) | Lead frame, semiconductor device manufacturing method using the same, and semiconductor device | |
| JP3680812B2 (en) | Manufacturing method of resin-encapsulated semiconductor device | |
| JPH03278451A (en) | Resin-sealed type semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |