JP2019021815A - Semiconductor element mounting substrate and manufacturing method thereof - Google Patents
Semiconductor element mounting substrate and manufacturing method thereof Download PDFInfo
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- JP2019021815A JP2019021815A JP2017140273A JP2017140273A JP2019021815A JP 2019021815 A JP2019021815 A JP 2019021815A JP 2017140273 A JP2017140273 A JP 2017140273A JP 2017140273 A JP2017140273 A JP 2017140273A JP 2019021815 A JP2019021815 A JP 2019021815A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 402
- 239000000758 substrate Substances 0.000 title claims abstract description 142
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 123
- 239000002184 metal Substances 0.000 claims abstract description 123
- 238000007747 plating Methods 0.000 claims abstract description 116
- 238000005530 etching Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 26
- 239000011347 resin Substances 0.000 abstract description 83
- 229920005989 resin Polymers 0.000 abstract description 83
- 238000007789 sealing Methods 0.000 abstract description 75
- 229910000679 solder Inorganic materials 0.000 description 100
- 238000005520 cutting process Methods 0.000 description 17
- 230000000052 comparative effect Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 12
- 238000003892 spreading Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 238000011179 visual inspection Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000012800 visualization Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本発明は、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板及びその製造方法に関する。 The present invention provides an external connection terminal made of a plating layer that is manufactured by removing a metal plate from a resin sealing body in which a region where a semiconductor element is mounted is sealed with a sealing resin, and is exposed on the back side. The present invention relates to a semiconductor element mounting substrate used for manufacturing a semiconductor package of a type connected to an external device such as the above and a manufacturing method thereof.
半導体装置の電子関連機器への組み込みに際し、半導体装置の外部接続用端子と、外部の電子関連機器との半田接続状態の良・不良を目視で検査できるように、半田接続部分の可視化が求められている。 When incorporating a semiconductor device into electronic equipment, visualization of the solder connection is required so that the external connection terminals of the semiconductor device and the external electronic equipment can be visually inspected for good / bad solder connection. ing.
しかるに、従来、外周部に外部接続用端子が突出しないタイプの半導体パッケージは、裏面側に露出した状態に配列されている複数の外部接続用端子をプリント基板等の外部機器と接続する構造となっていたため、正常に半田接続されているか否かを目視検査することが困難であった。 However, conventionally, the type of semiconductor package in which the external connection terminals do not protrude from the outer peripheral portion has a structure in which a plurality of external connection terminals arranged on the back surface side are connected to an external device such as a printed circuit board. Therefore, it was difficult to visually inspect whether or not the solder connection is normally performed.
しかし、半田接続部分の目視検査ができないと、半田接続作業時に内在する接続不良が見逃され、その後の通電検査等で接続不良が発見されるまでの作業コストが余計にかかってしまう。また、半田接続部分は、Ｘ線装置を用いて透視検査することは可能ではあるが、それでは、Ｘ線装置の設備コストが増大してしまう。 However, if visual inspection of the solder connection portion is not possible, the inherent connection failure at the time of solder connection work is overlooked, and the work cost until connection failure is discovered by subsequent energization inspection or the like is excessive. Further, although it is possible to perform a fluoroscopic inspection on the solder connection portion using an X-ray apparatus, this increases the equipment cost of the X-ray apparatus.
そこで、従来、半導体パッケージの半田接続部分における半田接続状態の良・不良を目視検査できるようにするための技術として、例えば、次の特許文献１には、リードフレームにおけるリードの裏面側の外部接続用端子となる端子部の切断位置にリードを横断する溝を形成することで、個々に切断されたときの半導体パッケージの裏面に露出する外部接続用端子に、端縁部にかけて空間部を設け、空間部に半田を介在させるようにして、半導体パッケージの側面に露出した外部接続用端子の端縁部から半田接続部分を目視可能にすることが提案されている。 Therefore, conventionally, as a technique for enabling visual inspection of the solder connection state of the solder connection portion of the semiconductor package, for example, the following Patent Document 1 discloses external connection on the back side of the lead in the lead frame. By forming a groove that crosses the lead at the cutting position of the terminal portion that becomes the terminal for use, an external connection terminal exposed on the back surface of the semiconductor package when individually cut is provided with a space portion over the edge portion, It has been proposed that solder is interposed in the space so that the solder connection portion is visible from the end edge portion of the external connection terminal exposed on the side surface of the semiconductor package.
また、例えば、次の特許文献２には、リードフレームの裏面に凹部を設け、表面側を樹脂封止後に、凹部を含む所定領域を封止樹脂側からハーフカット加工を施すことで、凹部を設けていた部位にスルーホールを形成し、次に、ハーフカット加工の幅より狭い幅でフルカット加工を施すことで、外部接続用端子を側方に突出させ、側方の突出部に、半田接続部分を目視可能にするためのスルーホールやスリットを設けることが記載されている。 In addition, for example, in the following Patent Document 2, a recess is provided on the back surface of the lead frame, and a predetermined region including the recess is subjected to half-cut processing from the sealing resin side after resin sealing the front surface side. A through hole is formed in the part that was provided, and then a full cut is performed with a width narrower than the width of the half cut, so that the external connection terminal protrudes to the side, and solder is applied to the side protrusion. It is described that a through hole or a slit is provided to make the connecting portion visible.
近年、携帯電話に代表されるように、電子機器の小型・軽量化が急速に進み、それら電子機器に用いられる半導体装置も小型・軽量化・高機能化が要求され、特に、半導体装置の厚みについて、薄型化が要求され、金属板を加工したリードフレームを用いた半導体装置に代わり、金属板を最終的に除去するタイプの半導体パッケージが開発されてきている。 In recent years, as represented by mobile phones, electronic devices are rapidly becoming smaller and lighter, and semiconductor devices used in these electronic devices are also required to be smaller, lighter, and more functional. Therefore, a semiconductor package of a type in which the metal plate is finally removed has been developed instead of a semiconductor device using a lead frame obtained by processing the metal plate.
例えば、金属板の一方の側の面に所定のパターニングを施したレジストマスクを形成し、レジストマスクから露出した金属板にめっき加工を施し、半導体素子搭載用のパッド部と、半導体素子と接続する内部接続用端子及び外部機器と接続するための外部接続用端子となる端子部とを形成した後、レジストマスクを除去することにより、半導体素子搭載用基板を製造する。そして、製造された半導体素子搭載用基板に半導体素子を搭載し、ワイヤボンディング又はフリップチップ接続した後に樹脂封止を行い、樹脂封止後に金属板を除去して封止樹脂の裏面にめっき層からなるパッド部や端子部を露出させ、薄型の半導体パッケージを完成させる。
この種の半導体パッケージによれば、パッド部や端子部が金属板よりも薄肉のめっき層で形成され、しかも、金属板が除去されているため、半導体パッケージの厚みをより一層薄くすることができる。
For example, a resist mask subjected to predetermined patterning is formed on one surface of the metal plate, the metal plate exposed from the resist mask is plated, and the pad portion for mounting the semiconductor element is connected to the semiconductor element. After forming an internal connection terminal and a terminal portion to be an external connection terminal for connecting to an external device, the resist mask is removed to manufacture a semiconductor element mounting substrate. Then, the semiconductor element is mounted on the manufactured semiconductor element mounting substrate, and after resin bonding, resin sealing is performed. After the resin sealing, the metal plate is removed and the back surface of the sealing resin is coated with a plating layer. The pad portion and terminal portion to be exposed are exposed to complete a thin semiconductor package.
According to this type of semiconductor package, the pad portion and the terminal portion are formed of a thinner plating layer than the metal plate, and the metal plate is removed, so that the thickness of the semiconductor package can be further reduced. .
しかし、特許文献１、２に記載の半導体パッケージの半田接続部分における半田接続状態の良・不良を目視検査できるようにするための技術は、金属板を除去して裏面に露出しためっき層が外部接続用端子となる端子部を構成するタイプの半導体装置を製造するための半導体素子搭載用基板には適用できない。
即ち、特許文献１、２に記載の技術では、半田接続部分を目視可能にするための溝やスルーホールやスリットを形成する前段階の凹部を、金属板からなるリードフレームに対してエッチング加工やプレス加工を施すことにより行っている。しかし、金属板を除去して裏面に露出しためっき層が外部接続用端子となる端子部を構成するタイプの半導体装置を製造するための半導体素子搭載用基板の場合、めっき層に対して特許文献１、２に記載の技術のようなエッチング加工やプレス加工を施すことにより、溝や凹部を形成することは非常に難しい。
However, the technology for enabling visual inspection of the solder connection state of the solder connection portion of the semiconductor package described in Patent Documents 1 and 2 is that the plating layer exposed on the back surface after removing the metal plate is external The present invention is not applicable to a semiconductor element mounting substrate for manufacturing a semiconductor device of a type that constitutes a terminal portion that becomes a connection terminal.
That is, in the techniques described in Patent Documents 1 and 2, a recess for forming a groove, a through hole, or a slit for making a solder connection portion visible can be etched on a lead frame made of a metal plate. This is done by pressing. However, in the case of a semiconductor element mounting substrate for manufacturing a semiconductor device of a type in which the plating layer exposed on the back surface after removing the metal plate constitutes a terminal portion that serves as an external connection terminal, the patent document is applied to the plating layer. It is very difficult to form grooves and recesses by performing etching or pressing as in the techniques described in 1 and 2.
しかも、特許文献１に記載のリードフレームにおけるリードの裏面側の外部接続用端子となる端子部の切断位置にリードを横断する溝を形成する技術では、樹脂封止の際に、端子部の溝に樹脂が入り込み、半田接続部分を目視可能にするための空間部が形成されず、半導体パッケージ製品の歩留まりが悪くなる虞がある。 In addition, in the technique of forming a groove that crosses the lead at the cutting position of the terminal portion that becomes the external connection terminal on the back surface side of the lead in the lead frame described in Patent Document 1, the groove of the terminal portion is used during resin sealing. There is a possibility that the resin enters the space, and the space for making the solder connection portion visible is not formed, so that the yield of the semiconductor package product is deteriorated.
また、特許文献２に記載の技術では、樹脂封止後に、ブレードを用いたハーフカットとフルカットの２回の切断工程が必要となり、生産効率が悪く、コストが増大してしまう。また、外部接続用端子が側方へ突出するため、半導体パッケージ製品を小型化し難い。 Further, the technique described in Patent Document 2 requires two cutting steps of half-cutting and full-cutting using a blade after resin sealing, resulting in poor production efficiency and increased cost. In addition, since the external connection terminal protrudes laterally, it is difficult to reduce the size of the semiconductor package product.
このように、裏面側に露出している複数の外部接続用端子をプリント基板等の外部機器と接続するタイプの半導体パッケージにおける、半田接続部分を目視可能とするための従来技術には、半導体パッケージ製品の歩留まりや、生産効率、製品の小型化の点で問題があり、しかも、裏面側に露出する外部接続用端子となる端子部がめっき層からなるタイプの半導体パッケージには、上記従来技術を用いること自体が困難であった。 As described above, the semiconductor package of the type in which a plurality of external connection terminals exposed on the back surface side are connected to an external device such as a printed circuit board in order to make the solder connection portion visible is a semiconductor package. There is a problem in terms of product yield, production efficiency, and product miniaturization, and the above conventional technology is applied to the type of semiconductor package in which the terminal part that is the external connection terminal exposed on the back side is a plating layer. It was difficult to use itself.
本発明は、上記従来の課題を鑑みてなされたものであり、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板において、半導体パッケージ製品の歩留まりや、生産効率が向上し、小型化にも対応でき、しかも、半田接続部分を目視可能な半導体素子搭載用基板及びその製造方法を提供することを目的としている。 The present invention has been made in view of the above-described conventional problems, and is manufactured by removing a metal plate from a resin sealing body in which a region where a semiconductor element is mounted is sealed with a sealing resin. In semiconductor device mounting boards used for manufacturing semiconductor packages of the type where external connection terminals consisting of exposed plating layers are connected to external devices such as printed circuit boards, the yield and production efficiency of semiconductor package products are improved and the size is reduced. In addition, an object of the present invention is to provide a semiconductor element mounting substrate and a method for manufacturing the same, in which a solder connection portion can be visually observed.
上記目的を達成するため、本発明の一態様による半導体素子搭載用基板は、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、前記凹部の底面から側面および該凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有することを特徴としている。 In order to achieve the above object, a semiconductor element mounting substrate according to one embodiment of the present invention is smaller than the bottom size of a semiconductor package formed on one surface of a metal plate and larger than the bottom size of a semiconductor element. It has a concave portion and a plurality of terminal portions made of a plating layer formed with steps at predetermined positions from the bottom surface to the side surface of the concave portion and the outer surface of the concave portion.
また、本発明の他の態様による半導体素子搭載用基板は、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、前記凹部の底面の中央部にめっき層で形成されたパッド部と、前記パッド部の周辺であって前記凹部の前記底面から側面および該凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有することを特徴としている。 According to another aspect of the present invention, there is provided a semiconductor element mounting substrate having a recess formed on one surface of a metal plate that is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element, A pad portion formed of a plating layer at the center of the bottom surface of the recess, and a step formed around the pad portion at predetermined positions extending from the bottom surface of the recess to the side surface and the outer surface of the recess. And having a plurality of terminal portions made of a plating layer.
また、本発明の半導体素子搭載用基板においては、前記凹部の深さが、０．００５ｍｍ〜０．１１ｍｍであるのが好ましい。 In the semiconductor element mounting substrate of the present invention, it is preferable that the depth of the recess is 0.005 mm to 0.11 mm.
また、本発明による半導体素子搭載用基板の製造方法は、金属板の一方の側の面上に、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい開口部を有するエッチング用レジストマスクを形成するとともに、前記金属板の他方の側の面上に、全面を覆うエッチング用レジストマスクを形成する工程と、前記金属板の一方の側からハーフエッチング加工を施し、凹部を形成する工程と、前記金属板の一方の側の面上に形成した前記エッチング用レジストマスクを除去する工程と、前記金属板の一方の側の面上に、前記凹部の底面から側面および該凹部の外側の面にわたる所定位置に対応する領域に複数の開口部を有するめっき用レジストマスクを形成する工程と、前記めっき用レジストマスクの開口部にめっき加工を施し、段差のついた複数の端子部を形成する工程と、前記金属板の両面上に形成したレジストマスクを除去する工程と、を有することを特徴としている。 Also, the method for manufacturing a substrate for mounting a semiconductor element according to the present invention includes an etching resist having an opening smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element on one side of the metal plate. Forming a mask, forming a resist mask for etching on the other side of the metal plate, and forming a recess by half-etching from one side of the metal plate Removing the etching resist mask formed on the one side surface of the metal plate, and on the one side surface of the metal plate, from the bottom surface of the concave portion to the side surface and the outer side of the concave portion. Forming a plating resist mask having a plurality of openings in a region corresponding to a predetermined position over the surface, and applying plating to the openings of the plating resist mask. Alms, is characterized by comprising a step of forming a plurality of terminal portions with a stepped, and a step of removing a resist mask formed on both surfaces of the metal plate.
本発明によれば、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板において、半導体パッケージ製品の歩留まりや、生産効率が向上し、小型化にも対応でき、しかも、半田接続部分を目視可能な半導体素子搭載用基板及びその製造方法が得られる。 According to the present invention, an external connection terminal made of a plating layer that is manufactured by removing a metal plate from a resin sealing body in which a region where a semiconductor element is mounted is sealed with a sealing resin is exposed. For semiconductor device mounting boards used in the manufacture of semiconductor packages that are connected to external devices such as printed circuit boards, the yield of semiconductor package products, production efficiency can be improved, and miniaturization can be supported. Can be obtained, and a method for manufacturing the same.
実施形態の説明に先立ち、本発明を導出するに至った経緯及び本発明の作用効果について説明する。
まず、本件発明者は、半導体パッケージの半田接続部分を目視可能にするための従来技術である特許文献１に記載の技術について検討・考察した。
特許文献１に記載の技術について図７を用いて説明する。図７中、(a)は半導体パッケージに用いるリードフレームの外部機器と接続する側からみた図、(b)は(a)のリードフレームを用いて組み立てた半導体パッケージにおける(a)のＡ−Ａ断面図、(c)は(b)の半導体パッケージの外部接続用端子を外部機器に半田接続した状態を示す図、(d)は(a)のリードフレームにおける外部接続用端子となる端子部を示すＢ−Ｂ断面図である。
Prior to the description of the embodiments, the background of deriving the present invention and the effects of the present invention will be described.
First, the present inventor examined and considered the technique described in Patent Document 1, which is a conventional technique for making a solder connection portion of a semiconductor package visible.
The technique described in Patent Document 1 will be described with reference to FIG. 7A is a view of the lead frame used in the semiconductor package as viewed from the side connected to the external device, and FIG. 7B is a cross-sectional view taken along line AA in the semiconductor package assembled using the lead frame of FIG. Sectional view, (c) is a diagram showing a state in which the external connection terminals of the semiconductor package of (b) are solder-connected to an external device, and (d) is a terminal portion to be an external connection terminal in the lead frame of (a). It is a BB sectional view shown.
図７(a)に示す半導体パッケージに用いるリードフレームは、リードフレームにおけるリードの裏面側の外部接続用端子となる端子部５１の切断位置（図７(a)における一点鎖線上の位置）に、リードを横断する溝５１ｂがＦｅ−Ｎｉ合金やＣｕ合金等の金属板からなるリードフレームに対してエッチング加工やプレス加工を施すことによって形成されている。なお、図７(a)中、５２は半導体素子を搭載するパッド部、６０は半導体素子である。
そして、リードフレームのパッド部５２に半導体素子６０を搭載し、リードにおける半導体素子６０搭載側の内部接続端子となる端子部と半導体素子６０とをボンディングワイヤ６１で接続し、半導体素子搭載側を封止樹脂７０で封止した状態の半導体パッケージを切断位置に沿って切断することによって、図７(b)に示すように、個々に切断された半導体パッケージの裏面に露出するリードの外部接続用端子５１に、端縁部にかけて空間部５１ａが設けられる。
このように形成された半導体パッケージは、図７(c)に示すように、外部機器８０の端子８１に半田接続した状態では、半田９０は外部接続用端子５１の裏面から端縁部にかけて形成されている空間部５１ａに介在する。このため、半導体パッケージの側面に露出した外部接続用端子５１の半田接続部分を目視確認でき、半導体パッケージの外部機器８０との半田接続状態の良・不良を目視検査できる。
The lead frame used in the semiconductor package shown in FIG. 7A is located at the cutting position of the terminal portion 51 serving as the external connection terminal on the back side of the lead in the lead frame (position on the alternate long and short dash line in FIG. 7A). A groove 51b crossing the lead is formed by etching or pressing a lead frame made of a metal plate such as an Fe-Ni alloy or a Cu alloy. In FIG. 7A, reference numeral 52 denotes a pad portion for mounting a semiconductor element, and reference numeral 60 denotes a semiconductor element.
Then, the semiconductor element 60 is mounted on the pad portion 52 of the lead frame, the terminal portion serving as the internal connection terminal of the lead on the semiconductor element 60 mounting side and the semiconductor element 60 are connected by the bonding wire 61, and the semiconductor element mounting side is sealed. By cutting the semiconductor package sealed with the stop resin 70 along the cutting position, as shown in FIG. 7B, external connection terminals for leads exposed on the back surface of the individually cut semiconductor package 51 is provided with a space 51a over the edge.
In the semiconductor package formed in this way, as shown in FIG. 7C, the solder 90 is formed from the back surface to the edge of the external connection terminal 51 in a state where it is solder-connected to the terminal 81 of the external device 80. Interposed in the space 51a. For this reason, the solder connection portion of the external connection terminal 51 exposed on the side surface of the semiconductor package can be visually confirmed, and whether the solder connection state of the semiconductor package with the external device 80 can be visually inspected.
ところで、特許文献１に記載の技術では、半田接続部分を目視可能にするためのリードを横断する溝５１ｂをＦｅ−Ｎｉ合金やＣｕ合金等の金属板からなるリードフレームに対してエッチング加工やプレス加工を施すことにより形成している。
しかし、金属板を除去して裏面に露出しためっき層が外部接続用端子として機能する端子部を構成するタイプの半導体パッケージを製造するための半導体素子搭載用基板の場合、めっき層に対してエッチング加工やプレス加工を施すことにより、溝を形成することは非常に難しい。
また、特許文献１に記載の技術のように、リードフレームにおけるリードの裏面側の外部接続用端子５１となる端子部の切断位置に、リードを横断する溝５１ｂを形成すると、半導体パッケージの組立てにおける樹脂封止の際に、端子部の溝５１ｂに樹脂が入り込み、半田接続部分を目視可能にするための空間部５１ａが形成されない虞がある。
即ち、リードフレームにおけるリードの裏面側の外部接続用端子となる端子部５１にリードを横断する溝５１ｂを形成すると、外部接続用端子となる端子部５１は、切断位置において、図７(d)に示すようにリードの幅方向が全体にわたり薄肉状に形成される。一般に、リードフレームの半導体素子搭載側を樹脂封止する際には、リードフレームの裏面の溝に樹脂が入り込まないようにするためにリードフレームの裏面には、シート状のテープを貼り付ける。しかし、リードの幅方向に沿う溝５１ｂの外側部分にはシート状のテープと密着する面が存在しないため、リードの幅方向に沿う溝５１ｂの外側部分はシート状のテープから離れてしまう。ここで、シート状のテープを溝５１ｂの面に密着させようとしても、シート状のテープが大きく変形することになり、溝５１ｂに完全に密着させることが難しく、シート状のテープと溝５１ｂの面とに隙間が生じ易い。その結果、樹脂封止する際にシート状のテープと溝５１ｂの面との隙間から樹脂が回り込んで、端子部５１の溝５１ｂに樹脂が入り込み、半田接続部分を目視検査可能にするための空間部が形成されず、半導体パッケージ製品の歩留まりが悪くなる虞がある。
By the way, in the technique described in Patent Document 1, the groove 51b that crosses the lead for making the solder connection portion visible can be etched or pressed against a lead frame made of a metal plate such as an Fe-Ni alloy or Cu alloy. It is formed by processing.
However, in the case of a semiconductor element mounting substrate for manufacturing a semiconductor package of a type in which a metal layer is removed and a plating layer exposed on the back surface constitutes a terminal portion functioning as an external connection terminal, etching is performed on the plating layer. It is very difficult to form a groove by processing or pressing.
Further, as in the technique described in Patent Document 1, when the groove 51b that crosses the lead is formed at the cutting position of the terminal portion that becomes the external connection terminal 51 on the back surface side of the lead in the lead frame, the semiconductor package is assembled. At the time of resin sealing, there is a possibility that the resin enters the groove 51b of the terminal portion and the space portion 51a for making the solder connection portion visible is not formed.
That is, when the groove 51b that crosses the lead is formed in the terminal portion 51 that is the external connection terminal on the back side of the lead in the lead frame, the terminal portion 51 that is the external connection terminal is in the cutting position in FIG. As shown in FIG. 3, the entire width direction of the lead is formed thin. In general, when the semiconductor element mounting side of the lead frame is resin-sealed, a sheet-like tape is attached to the back surface of the lead frame so that the resin does not enter the groove on the back surface of the lead frame. However, since there is no surface in close contact with the sheet-like tape in the outer portion of the groove 51b along the lead width direction, the outer portion of the groove 51b along the lead width direction is separated from the sheet-like tape. Here, even if the sheet-like tape is brought into close contact with the surface of the groove 51b, the sheet-like tape is greatly deformed, and it is difficult to make the sheet-like tape completely adhere to the groove 51b. A gap is likely to occur between the surface and the surface. As a result, when the resin is sealed, the resin wraps around from the gap between the sheet-like tape and the surface of the groove 51b, the resin enters the groove 51b of the terminal portion 51, and the solder connection portion can be visually inspected. There is a possibility that the space portion is not formed and the yield of the semiconductor package product is deteriorated.
次に、特許文献２に記載の技術も、パターン形成された金属板からなるリードフレームに対してプレス加工を施すことにより、半田接続部分を目視可能にするためスルーホールやスリットを形成する前段階の凹部を形成しているが、金属板を除去して裏面側に露出しためっき層が外部接続用端子となる端子部を構成するタイプの半導体装置を製造するための半導体素子搭載用基板の場合、めっき層に対してプレス加工を施すことにより、凹部を形成することは非常に難しい。
また、樹脂封止後に、ブレードを用いてハーフカットとフルカットの２回の切断工程が必要となり、生産効率が悪く、コストが増大してしまう。しかも、外部接続用端子が横方向へ突出するため、半導体パッケージ製品を小型化し難い。
Next, the technique described in Patent Document 2 is also a pre-stage for forming a through hole or a slit in order to make the solder connection portion visible by performing press processing on a lead frame made of a patterned metal plate. In the case of a semiconductor element mounting substrate for manufacturing a semiconductor device of a type in which a metal layer is removed and a plating layer exposed on the back surface side constitutes a terminal portion serving as an external connection terminal It is very difficult to form a recess by pressing the plating layer.
Moreover, after resin sealing, the cutting process of a half cut and a full cut is required using a braid | blade, production efficiency is bad, and cost will increase. In addition, since the external connection terminals protrude in the lateral direction, it is difficult to reduce the size of the semiconductor package product.
そこで、本件発明者は、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板において、半導体パッケージ製品の歩留まりや、生産効率が向上し、小型化にも対応でき、しかも、半田接続部分を目視可能とするために、試行錯誤を重ね、本発明の半導体素子搭載用基板及びその製造方法を導出するに至った。 Therefore, the present inventor has manufactured an external connection terminal made of a plating layer that is manufactured by removing a metal plate from a resin sealing body in which a region where a semiconductor element is mounted is sealed with a sealing resin, and is exposed on the back surface side. In semiconductor device mounting boards used for manufacturing semiconductor packages of the type that are connected to external devices such as printed circuit boards, the yield of semiconductor package products, production efficiency can be improved, miniaturization can be supported, and solder connection In order to make the portion visible, trial and error were repeated and the semiconductor element mounting substrate of the present invention and a method for manufacturing the same were derived.
本発明の一態様による半導体素子搭載用基板は、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、凹部の底面から側面および凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有する。
また、本発明の他の態様による半導体素子搭載用基板は、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、凹部の底面の中央部にめっき層で形成されたパッド部と、パッド部の周辺であって凹部の底面から側面および凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有する。
A substrate for mounting a semiconductor element according to one aspect of the present invention includes a recess formed on one surface of a metal plate that is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element, and a bottom surface of the recess. It has a plurality of terminal portions made of a plating layer formed with steps at predetermined positions over the side surface and the outer surface of the recess.
According to another aspect of the present invention, there is provided a semiconductor element mounting substrate including a recess formed on one surface of a metal plate that is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element. A pad portion formed of a plating layer at the center of the bottom surface of the substrate, and a plating layer formed around the pad portion and having a step at a predetermined position extending from the bottom surface of the recess to the side surface and the outer surface of the recess. It has a plurality of terminal portions.
本発明の半導体素子搭載用基板のように、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、凹部の底面から側面および凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有して構成すれば、本発明の半導体素子搭載用基板を用いて半導体パッケージを製造した場合、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって露出するめっき層からなる端子部の裏面の外部接続用端子部が、半導体パッケージの底面から側面に向かって段差を有した形状に形成され、側面側の段差部分に空間部が設けられる。このため、半導体パッケージを外部基板に半田ボールを介して接続するときに、リフローにより溶けた半田が、外部接続用端子部の段差が形成されることによって設けられた空間部に濡れ広がる。その結果、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板であっても、半導体パッケージを、半田ボールを介して外部基板に接続したときの半田の接続状態を、半導体パッケージの側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視確認することができる。 As in the semiconductor element mounting substrate of the present invention, a recess formed on one surface of the metal plate that is smaller than the bottom surface size of the semiconductor package and larger than the bottom surface size of the semiconductor element, and a side surface from the bottom surface of the recess A semiconductor package is manufactured using the semiconductor element mounting substrate of the present invention if it is configured to have a plurality of terminal portions made of a plating layer formed with steps at predetermined positions over the outer surface of the recess. In this case, the external connection terminal portion on the back surface of the terminal portion made of the plating layer exposed by removing the metal plate from the resin sealing body in which the region where the semiconductor element is mounted is sealed with the sealing resin is formed on the semiconductor package. It is formed in a shape having a step from the bottom surface to the side surface, and a space is provided in the step portion on the side surface side. For this reason, when the semiconductor package is connected to the external substrate via the solder ball, the solder melted by reflow spreads out in the space portion provided by forming the step of the external connection terminal portion. As a result, it is manufactured by removing the metal plate from the resin sealing body in which the region where the semiconductor element is mounted is sealed with the sealing resin, and the external connection terminal including the plating layer exposed on the back side is a printed circuit board or the like. Even when a semiconductor device mounting board is used for manufacturing a semiconductor package of a type connected to an external device, the connection state of the solder when the semiconductor package is connected to the external board via a solder ball is It can be visually confirmed from the side of the edge of the external connection terminal made of a plating layer exposed on the side surface.
また、本発明の半導体素子搭載用基板のように構成すれば、段差をつけて形成されためっき層からなる複数の端子部は、金属板の凹部の底面から側面および凹部の外側の面にわたって隙間のない状態で密着する。このため、特許文献１に記載の技術における溝部とは異なり、樹脂封止の際に、端子部の溝に樹脂が入り込んで半導体パッケージ製品の歩留まりが悪くなるような虞がない。 Further, when configured as the semiconductor element mounting substrate of the present invention, the plurality of terminal portions made of a plating layer formed with a step are spaced from the bottom surface of the concave portion of the metal plate to the side surface and the outer surface of the concave portion. Adhere closely. For this reason, unlike the groove part in the technique described in Patent Document 1, there is no possibility that the resin enters the groove of the terminal part and the yield of the semiconductor package product deteriorates during resin sealing.
また、本発明の半導体素子搭載用基板のように構成すれば、特許文献２に記載の技術とは異なり、樹脂封止後に、ブレードを用いたハーフカットとフルカットの２回の切断工程が不要であり、生産効率が良く、コストを低減できる。また、外部接続用端子が側方へ突出しないため、半導体パッケージ製品を小型化し易くなる。 Further, when configured as the semiconductor element mounting substrate of the present invention, unlike the technique described in Patent Document 2, two cutting steps of half-cutting and full-cutting using a blade are unnecessary after resin sealing. Therefore, the production efficiency is good and the cost can be reduced. In addition, since the external connection terminals do not protrude laterally, the semiconductor package product can be easily downsized.
なお、本発明の半導体素子搭載用基板において、段差をつけて形成されためっき層からなる夫々の端子部の半導体素子搭載側の面は、半導体素子の電極と接続する内部接続用端子部となるが、段差のついためっき層からなる夫々の端子部の上段と下段のいずれの領域も、半導体素子の電極と接続することが可能である。
例えば、段差のついためっき層からなる夫々の端子部の下段と上段のいずれの面にも、半導体素子をフリップチップ実装することができる。
段差のついためっき層からなる夫々の端子部の下段の面に半導体素子をフリップチップ実装すると、半導体パッケージの厚みをめっき層の段差分薄くすることができる。
また、段差のついためっき層からなる夫々の端子部の上段の面に半導体素子をフリップチップ実装すると、封止樹脂で封止したときに、半導体素子の裏面側に回り込む封止樹脂の層を厚く形成でき、封止樹脂とめっき層との密着面積も広く確保できるため、封止樹脂と端子部との接続強度を高く保つことができる。また、パッド部の面と半導体素子との間の空間を十分に確保でき、絶縁性が向上してノイズを拾い難くなる。
また、本発明の半導体素子搭載用基板は、例えば、凹部の底面の中央部にめっき層で形成されたパッド部を設け、パッド部の周辺であって凹部の底面から側面および凹部の外側の面にわたる所定位置に、段差をつけて形成されためっき層からなる複数の端子部を設け、パッド部の面に半導体素子を搭載し、半導体素子の電極と夫々の端子部の上段の面とをワイヤボンディングにより接続することができるようにしても良い。
In the semiconductor element mounting substrate of the present invention, the surface on the semiconductor element mounting side of each terminal portion made of a plating layer formed with a step becomes an internal connection terminal portion connected to the electrode of the semiconductor element. However, it is possible to connect the upper and lower regions of each terminal portion made of a stepped plating layer to the electrode of the semiconductor element.
For example, the semiconductor element can be flip-chip mounted on either the lower or upper surface of each terminal portion made of a plated layer having a step.
When the semiconductor element is flip-chip mounted on the lower surface of each terminal portion made of a plated layer with a step, the thickness of the semiconductor package can be reduced by the step of the plated layer.
In addition, when a semiconductor element is flip-chip mounted on the upper surface of each terminal portion made of a plated layer with a step, a sealing resin layer that goes around to the back side of the semiconductor element when sealed with sealing resin. Since it can be formed thick and a large contact area between the sealing resin and the plating layer can be secured, the connection strength between the sealing resin and the terminal portion can be kept high. In addition, a sufficient space between the surface of the pad portion and the semiconductor element can be secured, and the insulation is improved, making it difficult to pick up noise.
Further, the semiconductor element mounting substrate of the present invention is provided with, for example, a pad portion formed of a plating layer at the center of the bottom surface of the recess, and the periphery of the pad portion from the bottom surface of the recess to the side surface and the outer surface of the recess. A plurality of terminal portions made of plated layers formed with steps are provided at predetermined positions over the surface, a semiconductor element is mounted on the surface of the pad portion, and the electrodes of the semiconductor element and the upper surface of each terminal portion are wired You may enable it to connect by bonding.
また、本発明の半導体素子搭載用基板においては、好ましくは、凹部の深さが、０．００５ｍｍ〜０．１１ｍｍである。
例えば、凹部の深さを０．００５ｍｍ〜０．０２５ｍｍ程度となるように形成すれば、凹部に形成された端子部等となるめっき層が半導体パッケージの裏面から大きくは突出しないため、半導体パッケージの製造において、封止樹脂体から金属板を引き剥がし除去する際における、凹部に形成されためっき層の金属板への引っ掛かりを防止でき、金属板を引き剥がし易くなる。
また、例えば、凹部の深さを０．０３ｍｍ〜０．０６ｍｍ程度となるように形成すれば、半導体素子搭載後の半導体素子の裏面側のパッド部等の面との空間を、ノイズ対策（絶縁性を向上させてノイズを拾い難くする）や半田ブリード対策（半導体素子を凹部の底面に形成された端子部等となるめっき層に半田接続したときにおける、めっき層表面と半導体素子との結合点以外のめっき層全域への半田の濡れ広がりを食い止め、めっき層表面と封止樹脂との密着性が阻害されることを防止し、また、半導体パッケージを外部機器へ半田接続したときにおける、隣接する端子側への半田の濡れ広がりを食い止め、電気的なショートを防止する）を講じることが可能な程度確保できる。
また、例えば、凹部の深さを０．０８ｍｍ〜０．１１ｍｍ程度となるように形成すれば、段差を有する端子部の裏面の外部接続用端子において半導体パッケージの側面側の段差部分に設けられる、半田を介在させうる空間部の領域が半導体パッケージの厚さ方向に増えることになる。その結果、半導体パッケージを製造後の外部接続用端子と外部機器との半田接続状態をより観察し易くなる。
また、凹部の深さを０．０８ｍｍ〜０．１１ｍｍ程度となるように形成すれば、半導体素子を搭載し、封止樹脂で封止後に、基材をなす金属板の除去を薬液の溶解により行う場合に、凹部の深さを深くした分、溶解させる金属板の体積がより少なくなる。その結果、薬液中に溶解される金属板成分の濃度の上昇を抑え、安定した溶解状態を保つことができ、薬液調整（金属板成分の濃度が高くなった溶液の汲み出し及び新しい溶液の補充）を軽減することができる。
In the semiconductor element mounting substrate of the present invention, the depth of the recess is preferably 0.005 mm to 0.11 mm.
For example, if the depth of the recess is formed to be about 0.005 mm to 0.025 mm, the plating layer that becomes the terminal portion or the like formed in the recess does not protrude greatly from the back surface of the semiconductor package. In manufacturing, when the metal plate is peeled and removed from the sealing resin body, the plating layer formed in the recess can be prevented from being caught on the metal plate, and the metal plate can be easily peeled off.
Further, for example, if the depth of the recess is formed to be about 0.03 mm to 0.06 mm, the space with the pad portion or the like on the back side of the semiconductor element after mounting the semiconductor element is reduced against noise (insulation). To prevent noise from picking up) and solder bleed countermeasures (bonding points between the surface of the plating layer and the semiconductor element when the semiconductor element is solder-connected to the plating layer, such as the terminal formed on the bottom of the recess) Prevents the spread of solder from spreading over the entire plating layer, prevents the adhesion between the plating layer surface and the sealing resin from being disturbed, and adjoins when the semiconductor package is soldered to an external device. This prevents the solder from spreading to the terminal side and prevents electrical shorting).
Further, for example, if the depth of the recess is formed to be about 0.08 mm to 0.11 mm, the external connection terminal on the back surface of the terminal portion having a step is provided at the step portion on the side surface side of the semiconductor package. The area of the space where solder can be interposed increases in the thickness direction of the semiconductor package. As a result, it becomes easier to observe the solder connection state between the external connection terminal and the external device after manufacturing the semiconductor package.
Moreover, if the depth of the recess is formed to be about 0.08 mm to 0.11 mm, the semiconductor element is mounted, and after sealing with a sealing resin, the metal plate forming the base material is removed by dissolving the chemical solution. When performing, the volume of the metal plate to melt | dissolves decreases by the part which deepened the depth of the recessed part. As a result, the rise in the concentration of the metal plate component dissolved in the chemical solution can be suppressed and a stable dissolution state can be maintained, and the chemical solution adjustment (pumping out the solution with a high concentration of the metal plate component and replenishment with a new solution) Can be reduced.
また、本発明の半導体素子搭載用基板においては、一つの半導体パッケージ領域において深さの異なる凹部を複数有しても良い。
また、本発明の半導体素子搭載用基板においては、凹部の底面が段差を有し、端子部が３つ以上の高さの異なる面を有しても良い。
端子部が３つ以上の高さの異なる面を有するようにすれば、半導体パッケージを外部機器へ半田接続したときに、複数の段差を有する面を介して半田を最も広い空間領域まで導き、最も広い空間領域で半田を介在させた状態に留め易くなる。その結果、半田ブリード対策（半導体素子を凹部の底面に形成された端子部等となるめっき層に半田接続したときにおける、めっき層表面と半導体素子との結合点以外のめっき層全域への半田の濡れ広がりを食い止め、めっき層表面と封止樹脂との密着性が阻害されることを防止し、また、半導体パッケージを外部機器へ半田接続したときにおける、隣接する端子側への半田の濡れ広がりを食い止め、電気的なショートを防止する）を講じ易くなる。
Further, the semiconductor element mounting substrate of the present invention may have a plurality of recesses having different depths in one semiconductor package region.
In the semiconductor element mounting substrate of the present invention, the bottom surface of the recess may have a step, and the terminal portion may have three or more surfaces with different heights.
If the terminal portion has three or more surfaces with different heights, when the semiconductor package is soldered to an external device, the solder is guided to the widest space area through the surface having a plurality of steps, It is easy to keep the solder in a wide space area. As a result, solder bleed countermeasures (when the semiconductor element is solder-connected to the plating layer to be the terminal portion formed on the bottom surface of the recess, the solder on the entire plating layer other than the bonding point between the plating layer surface and the semiconductor element) Prevents the spread of wetting, prevents the adhesion between the plating layer surface and the sealing resin from being disturbed, and prevents the solder from spreading to the adjacent terminals when the semiconductor package is soldered to an external device. It is easy to take hold and prevent electrical short circuit).
そして、このような本発明の半導体素子搭載用基板は、金属板の一方の側の面上に、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい開口部を有するエッチング用レジストマスクを形成するとともに、金属板の他方の側の面上に、全面を覆うエッチング用レジストマスクを形成する工程と、金属板の一方の側からハーフエッチング加工を施し、凹部を形成する工程と、金属板の一方の側の面上に形成したエッチング用レジストマスクを除去する工程と、金属板の一方の側の面上に、凹部の底面から側面および凹部の外側の面にわたる所定位置に対応する領域に複数の開口部を有するめっき用レジストマスクを形成する工程と、めっき用レジストマスクの開口部にめっき加工を施し、段差のついた複数の端子部を形成する工程と、金属板の両面上に形成したレジストマスクを除去する工程と、を有することによって製造できる。 Such a substrate for mounting a semiconductor element of the present invention is an etching resist having an opening on one side of the metal plate that is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element. Forming a mask, forming a resist mask for etching covering the entire surface on the other side of the metal plate, forming half-etching from one side of the metal plate, and forming a recess; A step of removing the resist mask for etching formed on the surface on one side of the metal plate, and a predetermined position extending from the bottom surface of the recess to the side surface and the outer surface of the recess on the surface on the one side of the metal plate. A step of forming a resist mask for plating having a plurality of openings in the region, and a plurality of terminals with steps by performing plating on the openings of the resist mask for plating Forming a, and removing the resist mask formed on both sides of the metal plate can be produced by having.
従って、本発明によれば、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板において、半導体パッケージ製品の歩留まりや、生産効率が向上し、小型化にも対応でき、しかも、半田接続部分を目視可能な半導体素子搭載用基板及びその製造方法が得られる。 Therefore, according to the present invention, it is manufactured by removing a metal plate from a resin sealing body in which a region on which a semiconductor element is mounted is sealed with a sealing resin, and is used for external connection including a plating layer exposed on the back side. For semiconductor device mounting boards used for manufacturing semiconductor packages of the type whose terminals are connected to external devices such as printed circuit boards, the yield of semiconductor package products, production efficiency can be improved, and miniaturization can be supported. A semiconductor element mounting substrate and a manufacturing method thereof can be obtained in which the connection portion can be visually observed.
以下、図面を参照して、本発明を実施するための形態の説明を行うこととする。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
図１は本発明の一実施形態に係る半導体素子搭載用基板の要部構成の一例を示す説明図で、(a)は端子部の構造を示す断面図、(b)は(a)の半導体素子搭載用基板が多列配列された多列型半導体素子搭載用基板の一例を示す上面図、(c)は(a)の半導体素子搭載用基板に半導体素子を搭載する一態様を示す説明図、(d)は(a)の半導体素子搭載用基板に半導体素子を搭載する他の態様を示す説明図、(e)は(a)の半導体素子搭載用基板の一変形例を示す説明図である。図２は図１(a)、図１(b)の半導体素子搭載用基板における隣り合う半導体パッケージ領域の端子部同士の配置態様の他の例を示す図で、(a)は断面図、(b)は(a)の半導体素子搭載用基板が多列配列された多列型半導体素子搭載用基板の上面図である。図３は本発明の他の実施形態に係る半導体素子搭載用基板の要部構成の一例を示す説明図で、(a)は端子部の構造を示す断面図、(b)は(a)の半導体素子搭載用基板が多列配列された多列型半導体素子搭載用基板の一例を示す上面図、(c)は(a)の半導体素子搭載用基板に半導体素子を搭載する一態様を示す説明図である。 1A and 1B are explanatory views showing an example of a configuration of a main part of a substrate for mounting a semiconductor element according to an embodiment of the present invention. FIG. 1A is a cross-sectional view showing a structure of a terminal part, and FIG. A top view showing an example of a multi-row type semiconductor element mounting substrate in which element mounting substrates are arranged in multiple rows, (c) is an explanatory view showing one mode of mounting semiconductor elements on the semiconductor element mounting substrate of (a) , (D) is an explanatory view showing another embodiment of mounting a semiconductor element on the semiconductor element mounting substrate of (a), and (e) is an explanatory view showing a modification of the semiconductor element mounting substrate of (a). is there. FIG. 2 is a diagram showing another example of the arrangement of the terminal portions of adjacent semiconductor package regions in the semiconductor element mounting substrate of FIGS. 1 (a) and 1 (b), (a) is a cross-sectional view, FIG. 5B is a top view of the multi-row semiconductor element mounting substrate in which the semiconductor element mounting substrates of FIG. FIG. 3 is an explanatory view showing an example of a configuration of a main part of a semiconductor element mounting substrate according to another embodiment of the present invention, in which (a) is a cross-sectional view showing a structure of a terminal portion, and (b) is a cross-sectional view of (a). A top view showing an example of a multi-row type semiconductor element mounting substrate in which semiconductor element mounting substrates are arranged in multiple rows, (c) is an explanation showing one mode of mounting a semiconductor element on the semiconductor element mounting substrate of (a) FIG.
本実施形態の半導体素子搭載用基板１は、例えば、図１(a)に示すように、凹部１１と、複数の端子部１２を有し、図１(b)に示すように、多列配列されている。
凹部１１は、金属板１０の一方の側の面１０ａに形成され、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きいサイズを有している。
端子部１２は、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面（即ち、金属板１０の一方の側の面１０ａ）にわたる所定位置に段差をつけて形成されためっき層で構成されている。
そして、複数の端子部１２は、図１(c)、図１(d)に示すように、半田ボール１５等の接続部材を介して、端子部１２の下段（図１(c)の例）又は端子部１２の上段（図１(d)の例）に、半導体素子２０をフリップチップ実装することができるようになっている。
なお、本実施形態の半導体素子搭載用基板１は、図１(a)、図１(b)の例では、隣り合う半導体パッケージ領域（不図示）の端子部同士が接続した態様に配置されているが、図２(a)、図２(b)に示すように、隣り合う半導体パッケージ領域（不図示）の端子部同士が離れた態様に配置されたものであってもよい。
また、本実施形態の半導体素子搭載用基板１は、図３(a)、図３(b)に示すように、凹部１１の底面１１ａの中央部にめっき層で形成されたパッド部１２−１と、パッド部１２−１の周辺であって凹部１１ａの底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる所定位置に、段差をつけて形成されためっき層で構成された複数の端子部１２−２を有し、図３(c)に示すように、パッド部１２−１に半導体素子２０を搭載するとともに、ボンディングワイヤ１６等の接続部材を介して、端子部１２−１の上段と、半導体素子２０とをワイヤボンディングすることができるように構成されたものであってもよい。
The semiconductor element mounting substrate 1 of the present embodiment has, for example, a recess 11 and a plurality of terminal portions 12 as shown in FIG. 1 (a), and a multi-row arrangement as shown in FIG. 1 (b). Has been.
The recess 11 is formed on the surface 10a on one side of the metal plate 10, and has a size smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element.
The terminal portion 12 is composed of a plating layer formed with a step at a predetermined position from the bottom surface 11a of the recess 11 to the side surface 11b and the outer surface of the recess 11 (that is, the surface 10a on one side of the metal plate 10). ing.
As shown in FIGS. 1 (c) and 1 (d), the plurality of terminal portions 12 are connected to the lower stage of the terminal portion 12 (example of FIG. 1 (c)) via connecting members such as solder balls 15. Alternatively, the semiconductor element 20 can be flip-chip mounted on the upper stage of the terminal portion 12 (example in FIG. 1D).
Note that the semiconductor element mounting substrate 1 of this embodiment is arranged in a manner in which terminal portions of adjacent semiconductor package regions (not shown) are connected in the example of FIGS. 1 (a) and 1 (b). However, as shown in FIGS. 2 (a) and 2 (b), the terminal portions of adjacent semiconductor package regions (not shown) may be arranged in a separated state.
Further, as shown in FIGS. 3A and 3B, the semiconductor element mounting substrate 1 of the present embodiment has a pad portion 12-1 formed of a plating layer at the center of the bottom surface 11a of the recess 11. And a plurality of terminal portions 12 composed of a plating layer formed with a step at a predetermined position around the pad portion 12-1 and extending from the bottom surface 11a of the recess 11a to the side surface 11b and the outer surface of the recess 11. 2, the semiconductor element 20 is mounted on the pad portion 12-1 as shown in FIG. 3C, and the upper stage of the terminal portion 12-1 is connected via a connecting member such as a bonding wire 16. The semiconductor element 20 may be configured to be wire-bonded.
その他、本実施形態の半導体素子搭載用基板１においては、凹部１１の深さは、０．００５〜０．１１ｍｍに形成されているのが好ましい。
また、本実施形態の半導体素子搭載用基板１においては、一つの半導体パッケージ領域において深さの異なる凹部１１を複数有しても良い。
また、本実施形態の半導体素子搭載用基板１においては、図１(e)に示すように、凹部１１の底面１１ａが段差を有し、端子部１２が３つ以上の高さの異なる面を有して構成されたものであっても良い。
In addition, in the semiconductor element mounting substrate 1 of the present embodiment, the depth of the recess 11 is preferably formed to be 0.005 to 0.11 mm.
Further, the semiconductor element mounting substrate 1 of the present embodiment may have a plurality of recesses 11 having different depths in one semiconductor package region.
Further, in the semiconductor element mounting substrate 1 of the present embodiment, as shown in FIG. 1 (e), the bottom surface 11a of the recess 11 has a step, and the terminal portion 12 has three or more surfaces having different heights. It may be configured to have.
次に、図１(a)、図１(b)のように構成される本実施形態の半導体素子搭載用基板１の製造工程の一例を、図４を用いて説明する。なお、製造の各工程において実施される、薬液洗浄や水洗洗浄を含む前処理・後処理等は、便宜上説明を省略する。
まず、銅または銅合金の金属板１０をリードフレーム材料として準備する（図４(a)参照）。
次に、金属板１０にハーフエッチング加工を施して凹部１１を形成する。詳しくは、金属板１０の両面にドライフィルムレジスト等の第１のレジスト層Ｒ１を形成する（図４(b)参照）。次いで、図１(a)、図１(b)に示した凹部１１に対応する所定のパターンが描画されたガラスマスクを用いて、金属板１０の一方の側の第１のレジスト層Ｒ１を露光するとともに、金属板１０の他方の側の第１のレジスト層Ｒ１を全面にわたって露光し、露光後に夫々の第１のレジスト層Ｒ１を現像する。そして、金属板１０の一方の側の面上に、半導体パッケージの外形よりも小さく、半導体素子の底面よりも大きいサイズの開口部を有するエッチング用レジストマスク３１を形成するとともに、金属板１０の他方の側の面上に、全面を覆うエッチング用レジストマスク３１を形成する（図４(c)参照）。次いで、金属板１０の一方の側からハーフエッチング加工を施し、凹部１１を形成する（図４(d)参照）。次いで、金属板１０の一方の側の面上に形成したエッチング用レジストマスク３１を除去する（図４(e)参照）。
次に、金属板１０の一方の側における、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる所定位置にめっき層からなる複数の端子部１２を形成する。詳しくは、金属板１０の一方の側の面に、ドライフィルムレジスト等の第２のレジスト層Ｒ２を形成する（図４(f)参照）。次いで、図１(a)、図１(b)に示した端子部１２に対応する所定のパターンが描画されたガラスマスクを用いて、金属板１０の一方の側の第２のレジスト層Ｒ２を露光し、露光後に第２のレジスト層Ｒ２を現像する。そして、金属板１０の一方の側の面上に、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる端子部１２に対応する領域に複数の開口部を有するめっき用レジストマスク３２を形成する（図４(g)参照）。次いで、めっき用レジストマスク３２の開口部に、例えば、Ａｕ、Ｐｄ、Ｎｉ、Ｐｄの順でめっき加工を施し、段差のついた複数の端子部１２を形成する（図４(h)参照）。
なお、めっき層の表面は、粗化処理を施すのが良い。めっき層の表面を粗化処理する場合、例えば、めっき層の形成をＮｉめっきで終えて、Ｎｉめっき層を粗化めっきで形成しても良い。また、例えば、平滑なＮｉめっき層を形成した後に、Ｎｉめっき層の表面をエッチングにて粗化処理しても良い。また、例えば、めっき層の形成をＣｕめっきで終えて、Ｃｕめっき層の表面を陽極酸化処理又はエッチングにて粗化処理してもよい。さらに、例えば、粗化めっき層形成後に、順に、Ｐｄ／Ａｕめっき層を積層してもよい。
次いで、金属板１０の両面上に形成したレジストマスク３１、３２を除去する（図４(i)参照）。
これにより、本実施形態の半導体素子搭載用基板１が出来上がる。
Next, an example of a manufacturing process of the semiconductor element mounting substrate 1 of the present embodiment configured as shown in FIGS. 1A and 1B will be described with reference to FIGS. Note that description of pre-processing and post-processing including chemical solution cleaning and water cleaning cleaning performed in each manufacturing process is omitted for the sake of convenience.
First, a copper or copper alloy metal plate 10 is prepared as a lead frame material (see FIG. 4A).
Next, the metal plate 10 is half-etched to form the recess 11. Specifically, a first resist layer R1 such as a dry film resist is formed on both surfaces of the metal plate 10 (see FIG. 4B). Next, the first resist layer R1 on one side of the metal plate 10 is exposed using a glass mask on which a predetermined pattern corresponding to the concave portion 11 shown in FIGS. 1 (a) and 1 (b) is drawn. At the same time, the first resist layer R1 on the other side of the metal plate 10 is exposed over the entire surface, and each first resist layer R1 is developed after the exposure. An etching resist mask 31 having an opening having a size smaller than the outer shape of the semiconductor package and larger than the bottom surface of the semiconductor element is formed on the surface on one side of the metal plate 10, and the other side of the metal plate 10. An etching resist mask 31 that covers the entire surface is formed on the surface on this side (see FIG. 4C). Next, half etching is performed from one side of the metal plate 10 to form the recess 11 (see FIG. 4D). Next, the resist mask 31 for etching formed on the surface on one side of the metal plate 10 is removed (see FIG. 4E).
Next, on one side of the metal plate 10, a plurality of terminal portions 12 made of a plating layer are formed at predetermined positions extending from the bottom surface 11 a of the recess 11 to the side surface 11 b and the outer surface of the recess 11. Specifically, a second resist layer R2 such as a dry film resist is formed on one surface of the metal plate 10 (see FIG. 4 (f)). Next, the second resist layer R2 on one side of the metal plate 10 is formed using a glass mask on which a predetermined pattern corresponding to the terminal portion 12 shown in FIGS. 1 (a) and 1 (b) is drawn. It exposes and develops 2nd resist layer R2 after exposure. Then, a plating resist mask 32 having a plurality of openings in a region corresponding to the terminal portion 12 extending from the bottom surface 11a of the recess 11 to the side surface 11b and the outer surface of the recess 11 is formed on one surface of the metal plate 10. It forms (refer FIG.4 (g)). Next, the openings of the plating resist mask 32 are plated in the order of, for example, Au, Pd, Ni, and Pd to form a plurality of terminal portions 12 having steps (see FIG. 4 (h)).
Note that the surface of the plating layer is preferably subjected to a roughening treatment. When roughening the surface of the plating layer, for example, the formation of the plating layer may be finished by Ni plating, and the Ni plating layer may be formed by roughening plating. For example, after forming a smooth Ni plating layer, the surface of the Ni plating layer may be roughened by etching. Further, for example, the formation of the plating layer may be finished by Cu plating, and the surface of the Cu plating layer may be roughened by anodic oxidation or etching. Furthermore, for example, a Pd / Au plating layer may be sequentially laminated after the rough plating layer is formed.
Next, the resist masks 31 and 32 formed on both surfaces of the metal plate 10 are removed (see FIG. 4 (i)).
Thereby, the semiconductor element mounting substrate 1 of this embodiment is completed.
次に、本実施形態の半導体素子搭載用基板１を用いた半導体パッケージの製造手順を、図５を用いて説明する。
まず、端子部１２の表面の内部端子接続部に半田ボール１５等を介して半導体素子２０をフリップチップ接続する（図５(a)参照）。
次に、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂２１で封止する（図５(b)参照）。
次に、金属板１０を除去し（図５(c)参照）、所定の半導体パッケージの寸法に切断する（図５(d)参照）。これにより、本実施形態の半導体素子搭載用基板１を用いた半導体パッケージ４０が完成する（図５(e)参照）。
Next, a manufacturing procedure of a semiconductor package using the semiconductor element mounting substrate 1 of the present embodiment will be described with reference to FIG.
First, the semiconductor element 20 is flip-chip connected to the internal terminal connection portion on the surface of the terminal portion 12 via the solder ball 15 or the like (see FIG. 5A).
Next, a mold die (not shown) is set, and the semiconductor element mounting side is sealed with a sealing resin 21 (see FIG. 5B).
Next, the metal plate 10 is removed (see FIG. 5C) and cut into a predetermined semiconductor package dimension (see FIG. 5D). Thereby, the semiconductor package 40 using the semiconductor element mounting substrate 1 of the present embodiment is completed (see FIG. 5E).
本実施形態の半導体素子搭載用基板１によれば、金属板１０の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部１１と、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる所定位置に段差をつけて形成されためっき層からなる複数の端子部１２を有して構成したので、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板１０を除去することによって露出するめっき層からなる端子部１２の裏面の外部接続用端子部が、半導体パッケージ４０の底面から側面に向かって段差を有した形状に形成され、側面側の段差部分に空間部が設けられる。このため、本実施形態の半導体素子搭載用基板１を用いて半導体パッケージ４０を製造した場合、例えば、図６(a)〜図６(c)に示すように、半導体パッケージ４０を外部機器（例えば、プリント基板８０）に半田ボール９０を介して接続するときに、リフローにより溶けた半田が、端子部１２の裏面の外部接続用端子部の段差が形成されることによって設けられた空間部に濡れ広がる。その結果、半導体素子２０が搭載された領域を封止樹脂２１で封止した樹脂封止体から金属板１０を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板であっても、半導体パッケージ４０を、半田ボール９０を介して外部基板８０に接続したときの半田の接続状態を、半導体パッケージ４０の側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視確認することができる。 According to the semiconductor element mounting substrate 1 of the present embodiment, the concave portion 11 formed on one surface of the metal plate 10 is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element, and the concave portion. 11 has a plurality of terminal portions 12 made of a plating layer formed with steps at predetermined positions from the bottom surface 11a to the side surface 11b and the outer surface of the recess 11, so that the region where the semiconductor element is mounted can be formed. The external connection terminal portion on the back surface of the terminal portion 12 made of the plating layer exposed by removing the metal plate 10 from the resin sealing body sealed with the sealing resin is stepped from the bottom surface of the semiconductor package 40 toward the side surface. And a space portion is provided in the step portion on the side surface side. For this reason, when the semiconductor package 40 is manufactured using the semiconductor element mounting substrate 1 of the present embodiment, for example, as shown in FIG. 6A to FIG. When the solder ball 90 is connected to the printed circuit board 80), the solder melted by reflow wets the space provided by forming the step of the external connection terminal portion on the back surface of the terminal portion 12. spread. As a result, an external connection terminal made of a plating layer that is manufactured by removing the metal plate 10 from the resin sealing body in which the region where the semiconductor element 20 is mounted is sealed with the sealing resin 21 is exposed. Even in the case of a semiconductor element mounting substrate used for manufacturing a semiconductor package of a type connected to an external device such as a printed circuit board, solder connection when the semiconductor package 40 is connected to the external substrate 80 via the solder balls 90 The state can be visually confirmed from the side of the end edge portion of the external connection terminal formed of the plating layer exposed on the side surface of the semiconductor package 40.
また、本実施形態の半導体素子搭載用基板１によれば、段差をつけて形成されためっき層からなる複数の端子部１２は、金属板１０の凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたって隙間のない状態で密着する。このため、特許文献１に記載の技術における溝部とは異なり、樹脂封止の際に、端子部の溝に封止樹脂が入り込んで半導体パッケージ製品の歩留まりが悪くなるような虞がない。 In addition, according to the semiconductor element mounting substrate 1 of the present embodiment, the plurality of terminal portions 12 made of a plating layer formed with steps are formed from the bottom surface 11 a of the concave portion 11 of the metal plate 10 to the side surface 11 b and the concave portion 11. Close contact with the outer surface without any gaps. For this reason, unlike the groove part in the technique described in Patent Document 1, there is no possibility that the sealing resin enters the groove of the terminal part and the yield of the semiconductor package product deteriorates during resin sealing.
また、本実施形態の半導体素子搭載用基板１によれば、特許文献２に記載の技術とは異なり、樹脂封止後に、ブレードを用いたハーフカットとフルカットの２回の切断工程が不要であり、生産効率が良く、コストを低減できる。また、外部接続用端子が側方へ突出しないため、半導体パッケージ製品を小型化し易くなる。 In addition, according to the semiconductor element mounting substrate 1 of the present embodiment, unlike the technique described in Patent Document 2, two cutting steps of half cutting and full cutting using a blade are unnecessary after resin sealing. Yes, production efficiency is good and costs can be reduced. In addition, since the external connection terminals do not protrude laterally, the semiconductor package product can be easily downsized.
また、本実施形態の半導体素子搭載用基板１において、図１(c)に示したように、段差のついためっき層からなる夫々の端子部１２の下段の面に半導体素子２０をフリップチップ実装すれば、半導体パッケージの厚みをめっき層の段差分薄くすることができる。 Further, in the semiconductor element mounting substrate 1 of this embodiment, as shown in FIG. 1C, the semiconductor element 20 is flip-chip mounted on the lower surface of each terminal portion 12 made of a plated layer having a step. By doing so, the thickness of the semiconductor package can be reduced by the level difference of the plating layer.
また、本実施形態の半導体素子搭載用基板１において、図１(d)に示したように、段差のついためっき層からなる夫々の端子部１２−２の上段の面に半導体素子２０をフリップチップ実装すれば、封止樹脂で封止したときに、半導体素子２０の裏面側に回り込む封止樹脂の層を厚く形成でき、封止樹脂とめっき層との密着面積も広く確保できるため、封止樹脂と端子部１２との接続強度を高く保つことができる。また、パッド部１２−１の面と半導体素子２０との間の空間を十分に確保でき、絶縁性が向上してノイズを拾い難くなる。 Further, in the semiconductor element mounting substrate 1 of the present embodiment, as shown in FIG. 1D, the semiconductor element 20 is flipped onto the upper surface of each terminal portion 12-2 made of a plated layer having a step. If the chip is mounted, the sealing resin layer that wraps around the back surface side of the semiconductor element 20 when sealed with the sealing resin can be formed thick, and a large contact area between the sealing resin and the plating layer can be secured. The connection strength between the stop resin and the terminal portion 12 can be kept high. In addition, a sufficient space between the surface of the pad portion 12-1 and the semiconductor element 20 can be secured, and the insulation is improved, making it difficult to pick up noise.
また、本実施形態の半導体素子搭載用基板１において、凹部１１の深さを０．００５ｍｍ〜０．０２５ｍｍ程度となるように形成すれば、凹部１１に形成された端子部１２等となるめっき層が半導体パッケージ４０の裏面から大きくは突出しないため、半導体パッケージ４０の製造において、封止樹脂体から金属板１０を引き剥がし除去する際における、凹部１１に形成されためっき層の金属板への引っ掛かりを防止でき、金属板１０を引き剥がし易くなる。 Further, in the semiconductor element mounting substrate 1 of the present embodiment, if the depth of the concave portion 11 is formed to be about 0.005 mm to 0.025 mm, a plating layer that becomes the terminal portion 12 or the like formed in the concave portion 11. However, when the semiconductor plate 40 is peeled and removed from the sealing resin body in manufacturing the semiconductor package 40, the plating layer formed in the recess 11 is caught on the metal plate. And the metal plate 10 can be easily peeled off.
また、本実施形態の半導体素子搭載用基板１において、凹部１１の深さを０．０３ｍｍ〜０．０６ｍｍ程度となるように形成すれば、半導体素子搭載後の半導体素子２０の裏面側のパッド部等の面との空間を、ノイズ対策（絶縁性を向上させてノイズを拾い難くする）や半田ブリード対策（半導体素子２０を凹部１１の底面に形成された端子部１２等となるめっき層に半田接続したときにおける、めっき層表面と半導体素子２０との結合点以外のめっき層全域への半田の濡れ広がりを食い止め、めっき層表面と封止樹脂との密着性が阻害されることを防止し、また、半導体パッケージを外部機器へ半田接続したときにおける、隣接する端子側への半田の濡れ広がりを食い止め、電気的なショートを防止する）を講じることが可能な程度確保できる。
また、本実施形態の図１(e)の半導体素子搭載用基板によれば、端子部１２が３つ以上の高さの異なる面を有するので、半導体パッケージを外部機器へ半田接続したときに、複数の段差を有する面を介して半田を最も広い空間領域まで導き、最も広い空間領域で半田を介在させた状態に留め易くなる。その結果、半田ブリード対策（半導体素子２０を凹部１１の底面に形成された端子部１２等となるめっき層に半田接続したときにおける、めっき層表面と半導体素子２０との結合点以外のめっき層全域への半田の濡れ広がりを食い止め、めっき層表面と封止樹脂との密着性が阻害されることを防止し、また、半導体パッケージを外部機器へ半田接続したときにおける、隣接する端子側への半田の濡れ広がりを食い止め、電気的なショートを防止する）を講じ易くなる。
Further, in the semiconductor element mounting substrate 1 of the present embodiment, if the recess 11 is formed to have a depth of about 0.03 mm to 0.06 mm, the pad portion on the back surface side of the semiconductor element 20 after the semiconductor element is mounted. For example, the space between the surface and the like is a noise countermeasure (improves insulation and makes it difficult to pick up noise) and a solder bleed countermeasure (the semiconductor element 20 is soldered to a plating layer to be the terminal portion 12 formed on the bottom surface of the concave portion 11. When connected, it prevents the solder from spreading over the entire plating layer other than the bonding point between the plating layer surface and the semiconductor element 20, and prevents the adhesion between the plating layer surface and the sealing resin from being hindered, In addition, when the semiconductor package is soldered to an external device, it prevents the solder from spreading to the adjacent terminals and prevents electrical shorting). That.
Further, according to the semiconductor element mounting substrate of FIG. 1 (e) of this embodiment, since the terminal portion 12 has three or more surfaces having different heights, when the semiconductor package is solder-connected to an external device, It is easy to guide the solder to the widest space area through the surface having a plurality of steps and to keep the solder interposed in the widest space area. As a result, solder bleed countermeasures (when the semiconductor element 20 is solder-connected to the plating layer to be the terminal portion 12 formed on the bottom surface of the concave portion 11, the entire plating layer other than the bonding point between the plating layer surface and the semiconductor element 20) Prevents the spread of solder from spreading to the surface, prevents the adhesion between the plating layer surface and the sealing resin from being obstructed, and solders to the adjacent terminals when the semiconductor package is soldered to an external device. To prevent the electrical short circuit).
また、本実施形態の半導体素子搭載用基板１において、凹部１１の深さを０．０８ｍｍ〜０．１１ｍｍ程度となるように形成すれば、段差を有する端子部１２の裏面の外部接続用端子において半導体パッケージ４０の側面側の段差部分に設けられる、半田を介在させうる空間部の領域が半導体パッケージ４０の厚さ方向に増えることになる。その結果、半導体パッケージを製造後の外部接続用端子と外部機器との半田接続状態をより観察し易くなる。
また、凹部１１の深さを０．０８ｍｍ〜０．１１ｍｍ程度となるように形成すれば、半導体素子２０を搭載し、封止樹脂で封止後に、基材をなす金属板１０の除去を薬液の溶解により行う場合に、凹部１１の深さを深くした分、溶解させる金属板１０の体積がより少なくなる。その結果、薬液中に溶解される金属板１０成分の濃度の上昇を抑え、安定した溶解状態を保つことができ、薬液調整（金属板成分の濃度が高くなった溶液の汲み出し及び新しい溶液の補充）を軽減することができる。
Further, in the semiconductor element mounting substrate 1 of the present embodiment, if the recess 11 is formed to have a depth of about 0.08 mm to 0.11 mm, the external connection terminal on the back surface of the terminal portion 12 having a step is provided. The region of the space portion where the solder can be interposed, which is provided in the step portion on the side surface side of the semiconductor package 40, increases in the thickness direction of the semiconductor package 40. As a result, it becomes easier to observe the solder connection state between the external connection terminal and the external device after manufacturing the semiconductor package.
Further, if the depth of the recess 11 is formed to be about 0.08 mm to 0.11 mm, the semiconductor element 20 is mounted, and after sealing with a sealing resin, the metal plate 10 that forms the base material is removed. When the melting is performed, the volume of the metal plate 10 to be melted is reduced by the depth of the recess 11. As a result, an increase in the concentration of the metal plate 10 component dissolved in the chemical solution can be suppressed and a stable dissolution state can be maintained, and the chemical solution adjustment (pumping out a solution with a high concentration of the metal plate component and replenishment of a new solution) ) Can be reduced.
従って、本実施形態によれば、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板において、半導体パッケージ製品の歩留まりや、生産効率が向上し、小型化にも対応でき、しかも、半田接続部分を目視可能な半導体素子搭載用基板及びその製造方法が得られる。 Therefore, according to the present embodiment, the external connection made of the plating layer that is manufactured by removing the metal plate from the resin sealing body in which the region where the semiconductor element is mounted is sealed with the sealing resin is exposed on the back surface side. In the semiconductor device mounting substrate used for manufacturing semiconductor packages of the type in which the terminal is connected to an external device such as a printed circuit board, the yield of semiconductor package products, the production efficiency is improved, and the size can be reduced. A semiconductor element mounting substrate and a method for manufacturing the same can be obtained in which the solder connection portion can be visually observed.
次に、本発明のリードフレームとその製造方法の実施例を説明する。
実施例１
まず、金属板１０として、厚さ０．２０ｍｍの銅系材料を準備し（図４(a)参照）、両面に、第１のレジスト層Ｒ１としてドライフィルムレジストをラミネートした（図４(b)参照）。
Next, embodiments of the lead frame and the manufacturing method thereof according to the present invention will be described.
Example 1
First, a copper-based material having a thickness of 0.20 mm was prepared as the metal plate 10 (see FIG. 4A), and a dry film resist as a first resist layer R1 was laminated on both surfaces (FIG. 4B). reference).
次に、図１(a)、図１(b)に示した凹部１１に対応する所定のパターンが描画されたガラスマスクを用いて金属板１０の一方の側の第１のレジスト層Ｒ１を露光するとともに、金属板１０の他方の側の第１のレジスト層Ｒ１を全面にわたって露光し、露光後に夫々の第１のレジスト層Ｒ１を現像して、金属板１０の一方の側の面上に、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい開口部を有するエッチング用レジストマスク３１を形成するとともに、金属板１０の他方の側の面上に、全面を覆うエッチング用レジストマスク３１を形成した（図４(c)参照）。
次に、金属板１０の一方の側から深さ０．０１５ｍｍのハーフエッチング加工を施し、金属板におけるハーフエッチング加工を施した深さにおいて凹部１１を形成した（図４(d)参照）。なお、エッチング液は、塩化第二鉄液を使用した。
次に、金属板１０の一方の側の面上に形成したエッチング用レジストマスク３１を剥離した（図４(e)参照）。
Next, the first resist layer R1 on one side of the metal plate 10 is exposed using a glass mask on which a predetermined pattern corresponding to the concave portion 11 shown in FIGS. 1 (a) and 1 (b) is drawn. In addition, the first resist layer R1 on the other side of the metal plate 10 is exposed over the entire surface, and after the exposure, each first resist layer R1 is developed, and on the surface on one side of the metal plate 10, An etching resist mask 31 having an opening smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element is formed, and the etching resist mask covering the entire surface is formed on the other side of the metal plate 10. 31 was formed (see FIG. 4C).
Next, a half etching process having a depth of 0.015 mm was performed from one side of the metal plate 10 to form a recess 11 at a depth at which the half etching process was performed on the metal plate (see FIG. 4D). Note that ferric chloride solution was used as the etching solution.
Next, the etching resist mask 31 formed on the surface on one side of the metal plate 10 was peeled off (see FIG. 4E).
次に、金属板１０の一方の側の面に、第２のレジスト層Ｒ２としてドライフィルムレジストをラミネートした（図４(f)参照）。
次に、図１(a)、図１(b)に示した端子部１２に対応する所定のパターンが描画されたガラスマスクを用いて、金属板１０の一方の側の第２のレジスト層Ｒ２を露光し、露光後に第２のレジスト層Ｒ２を現像して、金属板１０の一方の側の面上に、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる端子部１２に対応する領域に複数の開口部を有するめっき用レジストマスク３２を形成した（図４(g)参照）。
次に、めっき用レジストマスク３２の開口部に、Ａｕを０．０１μｍ、Ｐｄを０．０３μｍ、Ｎｉを３０．０μｍ、Ｐｄを０．０３μｍの厚さで順次めっき加工を施し、段差のついた複数の端子部１２を形成した（図４(h)参照）。
次に、金属板１０の両面上に形成したレジストマスク３１、３２を剥離し（図４(i)参照）、実施例１の半導体素子搭載用基板１を得た。
Next, a dry film resist was laminated as a second resist layer R2 on one surface of the metal plate 10 (see FIG. 4 (f)).
Next, the second resist layer R2 on one side of the metal plate 10 is used by using a glass mask on which a predetermined pattern corresponding to the terminal portion 12 shown in FIGS. 1A and 1B is drawn. And the second resist layer R2 is developed after the exposure to correspond to the terminal portion 12 extending from the bottom surface 11a of the recess 11 to the side surface 11b and the outer surface of the recess 11 on one surface of the metal plate 10. A plating resist mask 32 having a plurality of openings was formed in the region to be formed (see FIG. 4G).
Next, the opening of the resist mask 32 for plating was plated with a thickness of 0.01 μm Au, 0.03 μm Pd, 30.0 μm Ni, 0.03 μm Pd, and stepped. A plurality of terminal portions 12 were formed (see FIG. 4 (h)).
Next, the resist masks 31 and 32 formed on both surfaces of the metal plate 10 were peeled off (see FIG. 4 (i)), and the semiconductor element mounting substrate 1 of Example 1 was obtained.
次に、実施例１の半導体素子搭載用基板１における端子部１２の表面の内部端子接続部に半田ボール１５等を介して半導体素子２０をフリップチップ接続し（図５(a)参照）、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂２１で封止した（図５(b)参照）。
次に、金属板１０を除去した（図５(c)参照）。
Next, the semiconductor element 20 is flip-chip connected to the internal terminal connecting portion on the surface of the terminal portion 12 in the semiconductor element mounting substrate 1 of the first embodiment via the solder balls 15 (see FIG. 5A). The mold mold not to be set was set, and the semiconductor element mounting side was sealed with the sealing resin 21 (see FIG. 5B).
Next, the metal plate 10 was removed (see FIG. 5C).
このとき、金属板１０を除去した封止樹脂体における半導体素子搭載側とは反対側の面（裏面）が凸形状に形成され、凸形状に形成された封止樹脂体の面から外部接続用端子となる端子部１２を構成するめっき層が露出した状態に仕上がった。
次に、所定の半導体パッケージの寸法に切断した（図５(d)参照）。これにより、実施例１の半導体素子搭載用基板１を用いた半導体パッケージ４０を得た（図５(e)参照）。
次に、実施例１の半導体素子搭載用基板１を用いた半導体パッケージ４０の外部接続用端子を外部機器であるプリント基板８０の端子に半田接続して、プリント基板８０に装着した。このとき、リフローにより溶けた半田９０が、端子部１２の裏面の外部接続用端子部の段差が形成されることによって設けられた空間部に濡れ広がり、半導体パッケージ４０の側面に露出した外部接続用端子１２の半田接続部分を目視確認でき、半導体パッケージ４０の外部機器であるプリント基板８０との半田接続状態の良・不良を目視検査できる状態となった（図６(a)〜図６(c)参照）。
At this time, the surface (back surface) opposite to the semiconductor element mounting side in the sealing resin body from which the metal plate 10 has been removed is formed in a convex shape, and the surface of the sealing resin body formed in the convex shape is used for external connection. It finished in the state which the plating layer which comprises the terminal part 12 used as a terminal exposed.
Next, it was cut into a predetermined semiconductor package size (see FIG. 5D). Thus, a semiconductor package 40 using the semiconductor element mounting substrate 1 of Example 1 was obtained (see FIG. 5 (e)).
Next, the external connection terminals of the semiconductor package 40 using the semiconductor element mounting substrate 1 of Example 1 were solder-connected to the terminals of the printed circuit board 80 as an external device, and mounted on the printed circuit board 80. At this time, the solder 90 melted by reflow wets and spreads in the space provided by forming the step of the external connection terminal portion on the back surface of the terminal portion 12, and is exposed to the side surface of the semiconductor package 40. The solder connection portion of the terminal 12 can be visually confirmed, and it is possible to visually inspect whether the solder connection state with the printed circuit board 80 which is an external device of the semiconductor package 40 is good or bad (FIGS. 6A to 6C). )reference).
比較例１
比較例１では、実施例１におけるハーフエッチング加工による凹部１１の形成工程を省き、それ以外は、実施例１と略同様の条件及び手順で、半導体素子搭載用基板を製造した。
より詳しくは、金属板の両面に第１のレジスト層として、ドライフィルムレジストをラミネートし、図１(b)に示した端子部１２に対応する所定のパターンが描画されたガラスマスクを用いて、金属板の一方の側の第１のレジスト層を露光するとともに、金属板の他方の側の第１のレジスト層を全面にわたって露光し、露光後に夫々の第１のレジスト層を現像して、金属板の一方の側の面上に、図１(b)に示した端子部１２に対応する領域に複数の開口部を有するめっき用レジストマスクを形成するとともに、金属板の他方の側の面上に、全面を覆うめっき用レジストマスクを形成した。
次に、めっき用レジストマスクの開口部に、Ａｕを０．０１μｍ、Ｐｄを０．０３μｍ、Ｎｉを３０．０μｍ、Ｐｄを０．０３μｍの厚さで順次めっき加工を施し、複数の端子部を形成した。
次に、金属板の両面上に形成したレジストマスクを剥離し、比較例１の半導体素子搭載用基板を得た。
Comparative Example 1
In Comparative Example 1, a semiconductor element mounting substrate was manufactured under substantially the same conditions and procedures as in Example 1 except that the step of forming the recesses 11 by half-etching in Example 1 was omitted.
More specifically, a dry film resist is laminated as a first resist layer on both surfaces of the metal plate, and a glass mask on which a predetermined pattern corresponding to the terminal portion 12 shown in FIG. The first resist layer on one side of the metal plate is exposed, the first resist layer on the other side of the metal plate is exposed over the entire surface, and each first resist layer is developed after exposure to develop a metal On the surface on one side of the plate, a resist mask for plating having a plurality of openings is formed in a region corresponding to the terminal portion 12 shown in FIG. 1 (b), and on the surface on the other side of the metal plate Then, a resist mask for plating covering the entire surface was formed.
Next, the plating resist mask is subjected to plating at a thickness of 0.01 μm for Au, 0.03 μm for Pd, 30.0 μm for Ni, and 0.03 μm for Pd. Formed.
Next, the resist mask formed on both surfaces of the metal plate was peeled off to obtain a semiconductor element mounting substrate of Comparative Example 1.
次に、実施例１と同様、比較例１の半導体素子搭載用基板における端子部の表面の内部端子接続部に半田ボール等を介して半導体素子をフリップチップ接続し、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂で封止し、その後、金属板を除去した。
このとき、金属板を除去した封止樹脂体における半導体素子搭載側とは反対側の面が平坦に形成され、平坦に形成された封止樹脂体の面から外部接続用端子となる端子部を構成するめっき層が露出した状態に仕上がった。
次に、所定の半導体パッケージの寸法に切断した。これにより、比較例１の半導体素子搭載用基板を用いた半導体パッケージを得た。
次に、比較例１の半導体素子搭載用基板を用いた半導体パッケージの外部接続用端子を外部機器であるプリント基板の端子に半田接続して、プリント基板に装着した。
Next, as in Example 1, the semiconductor element is flip-chip connected to the internal terminal connection part on the surface of the terminal part in the semiconductor element mounting substrate of Comparative Example 1 via a solder ball or the like, and a mold die (not shown) is set. Then, the semiconductor element mounting side was sealed with a sealing resin, and then the metal plate was removed.
At this time, the surface opposite to the semiconductor element mounting side of the sealing resin body from which the metal plate has been removed is formed flat, and the terminal portion serving as the external connection terminal is formed from the flat surface of the sealing resin body. The finished plating layer was exposed.
Next, it was cut into dimensions of a predetermined semiconductor package. Thereby, a semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 was obtained.
Next, the external connection terminal of the semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 was solder-connected to the terminal of the printed circuit board which is an external device and mounted on the printed circuit board.
外部機器接続後の半田接続状態の外観観察のし易さの比較
実施例１及び比較例１の夫々の半導体素子搭載用基板を用いて製造した夫々の半導体パッケージを、半田ボールを介して外部機器であるプリント基板の端子へ接続後の半田接続状態の外観観察のし易さを比較した。
比較例１の半導体素子搭載用基板を用いて製造した半導体パッケージを外部機器であるプリント基板の端子へ接続した場合、半導体パッケージの側面からの半田のはみ出しが無く、外部接続用端子部と外部機器であるプリント基板の端子との半田接続状態を目視確認することが難しかった。
これに対し、実施例１の半導体素子搭載用基板１を用いて製造した半導体パッケージ４０を外部機器であるプリント基板８０の端子へ接続した場合、半導体パッケージ４０の側面に全ての端子部１２の外部機器側の面と外部機器であるプリント基板８０の端子との間に半田が充填されていることを、半導体パッケージ４０の側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視で確認することができた。
Ease of observing appearance of solder connection after connection to external device Comparative Example 1 and Comparative Example 1 manufactured using the respective semiconductor element mounting substrates are connected to external devices via solder balls. The ease of appearance observation of the solder connection state after connection to the terminal of the printed circuit board was compared.
When a semiconductor package manufactured using the semiconductor element mounting substrate of Comparative Example 1 is connected to a terminal of a printed circuit board, which is an external device, there is no protrusion of solder from the side surface of the semiconductor package, and the external connection terminal portion and the external device It was difficult to visually confirm the solder connection state with the terminal of the printed circuit board.
On the other hand, when the semiconductor package 40 manufactured using the semiconductor element mounting substrate 1 according to the first embodiment is connected to the terminals of the printed circuit board 80 which is an external device, all the terminal portions 12 are arranged on the side surfaces of the semiconductor package 40. The fact that the solder is filled between the device side surface and the terminal of the printed circuit board 80 which is an external device indicates from the end edge side of the external connection terminal made of a plating layer exposed on the side surface of the semiconductor package 40. It was confirmed visually.
以上、本発明の好ましい実施形態及び実施例について詳説したが、本発明は、上述した実施形態及び実施例に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施形態及び実施例に種々の変形及び置換を加えることができる。 The preferred embodiments and examples of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples can be made without departing from the scope of the present invention. Various modifications and substitutions can be made to the embodiments.
本発明の半導体素子搭載用基板及びその製造方法は、端子部がめっき層で形成され、裏面側に露出する端子部裏面の外部接続用端子がプリント基板等と接続されるタイプの半導体パッケージに用いられることが求められる分野に有用である。 INDUSTRIAL APPLICABILITY The substrate for mounting a semiconductor element and the method for manufacturing the same according to the present invention are used for a semiconductor package in which a terminal portion is formed of a plating layer and an external connection terminal on the back surface of the terminal portion exposed on the back surface side is connected to a printed circuit board or the like. It is useful in fields where it is required to be
１ 半導体素子搭載用基板
１０ 金属板
１０ａ 金属板の一方の側の面
１１ 凹部
１１ａ 底面
１１ｂ 側面
１２ 端子部
１５ 半田ボール
１６ ボンディングワイヤ
２０、６０ 半導体素子
２１、７０ 封止樹脂
３１ エッチング用レジストマスク
３２ めっき用レジストマスク
４０ 半導体パッケージ
５１ 端子部（外部接続用端子）
５１ａ 空間部
５１ｂ 溝
５２ パッド部
６１ ボンディングワイヤ
８０ 外部機器（プリント基板）
８１ 端子
９０ 半田（半田ボール）
Ｒ１ 第１のレジスト層
Ｒ２ 第２のレジスト層
DESCRIPTION OF SYMBOLS 1 Semiconductor device mounting substrate 10 Metal plate 10a One side surface of metal plate 11 Recessed portion 11a Bottom surface 11b Side surface 12 Terminal portion 15 Solder ball 16 Bonding wire 20, 60 Semiconductor device 21, 70 Sealing resin 31 Resist mask for etching 32 Resist mask for plating 40 Semiconductor package 51 Terminal (terminal for external connection)
51a Space 51b Groove 52 Pad 61 Bonding Wire 80 External Device (Printed Circuit Board)
81 Terminal 90 Solder (solder ball)
R1 first resist layer R2 second resist layer
本発明の半導体素子搭載用基板のように、金属板の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部と、凹部の底面から側面および凹部の外側の面にわたる所定位置に段差をつけて形成された、めっき層からなる複数の端子部を有して構成すれば、本発明の半導体素子搭載用基板を用いて半導体パッケージを製造した場合、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって露出するめっき層からなる端子部の裏面の外部接続用端子部が、半導体パッケージの底面から側面に向かって段差を有した形状に形成され、側面側の段差部分に空間部が設けられる。このため、半導体パッケージを外部基板に半田を介して接続するときに、リフローにより溶けた半田が、外部接続用端子部の段差が形成されることによって設けられた空間部に濡れ広がる。その結果、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板であっても、半導体パッケージを、半田を介して外部基板に接続したときの半田の接続状態を、半導体パッケージの側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視確認することができる。 As in the semiconductor element mounting substrate of the present invention, a recess formed on one surface of the metal plate that is smaller than the bottom surface size of the semiconductor package and larger than the bottom surface size of the semiconductor element, and a side surface from the bottom surface of the recess A semiconductor package is manufactured using the semiconductor element mounting substrate of the present invention if it is configured to have a plurality of terminal portions made of a plating layer formed with steps at predetermined positions over the outer surface of the recess. In this case, the external connection terminal portion on the back surface of the terminal portion made of the plating layer exposed by removing the metal plate from the resin sealing body in which the region where the semiconductor element is mounted is sealed with the sealing resin is formed on the semiconductor package. It is formed in a shape having a step from the bottom surface to the side surface, and a space is provided in the step portion on the side surface side. Therefore, when connecting via the solder a semiconductor package to an external substrate, the solder melted by reflow, spreads into a space portion provided by a step of the external connection terminal portions are formed. As a result, it is manufactured by removing the metal plate from the resin sealing body in which the region where the semiconductor element is mounted is sealed with the sealing resin, and the external connection terminal including the plating layer exposed on the back side is a printed circuit board or the like. Even when a semiconductor device mounting substrate is used for manufacturing a semiconductor package of a type that is connected to an external device, the connection state of the solder when the semiconductor package is connected to the external substrate via solder It can be visually confirmed from the side of the edge portion of the external connection terminal composed of the plating layer exposed to the surface.
本実施形態の半導体素子搭載用基板１は、例えば、図１(a)に示すように、凹部１１と、複数の端子部１２を有し、図１(b)に示すように、多列配列されている。
凹部１１は、金属板１０の一方の側の面１０ａに形成され、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きいサイズを有している。
端子部１２は、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面（即ち、金属板１０の一方の側の面１０ａ）にわたる所定位置に段差をつけて形成されためっき層で構成されている。
そして、複数の端子部１２は、図１(c)、図１(d)に示すように、半田１５等の接続部材を介して、端子部１２の下段（図１(c)の例）又は端子部１２の上段（図１(d)の例）に、半導体素子２０をフリップチップ実装することができるようになっている。
なお、本実施形態の半導体素子搭載用基板１は、図１(a)、図１(b)の例では、隣り合う半導体パッケージ領域（不図示）の端子部同士が接続した態様に配置されているが、図２(a)、図２(b)に示すように、隣り合う半導体パッケージ領域（不図示）の端子部同士が離れた態様に配置されたものであってもよい。
また、本実施形態の半導体素子搭載用基板１は、図３(a)、図３(b)に示すように、凹部１１の底面１１ａの中央部にめっき層で形成されたパッド部１２−１と、パッド部１２−１の周辺であって凹部１１ａの底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる所定位置に、段差をつけて形成されためっき層で構成された複数の端子部１２−２を有し、図３(c)に示すように、パッド部１２−１に半導体素子２０を搭載するとともに、ボンディングワイヤ１６等の接続部材を介して、端子部１２−１の上段と、半導体素子２０とをワイヤボンディングすることができるように構成されたものであってもよい。
The semiconductor element mounting substrate 1 of the present embodiment has, for example, a recess 11 and a plurality of terminal portions 12 as shown in FIG. 1 (a), and a multi-row arrangement as shown in FIG. 1 (b). Has been.
The recess 11 is formed on the surface 10a on one side of the metal plate 10, and has a size smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element.
The terminal portion 12 is composed of a plating layer formed with a step at a predetermined position from the bottom surface 11a of the recess 11 to the side surface 11b and the outer surface of the recess 11 (that is, the surface 10a on one side of the metal plate 10). ing.
As shown in FIGS. 1 (c) and 1 (d), the plurality of terminal portions 12 are connected to the lower stage of the terminal portion 12 (example of FIG. 1 (c)) or via a connecting member such as solder 15 or the like. The semiconductor element 20 can be flip-chip mounted on the upper stage of the terminal portion 12 (example in FIG. 1 (d)).
Note that the semiconductor element mounting substrate 1 of this embodiment is arranged in a manner in which terminal portions of adjacent semiconductor package regions (not shown) are connected in the example of FIGS. 1 (a) and 1 (b). However, as shown in FIGS. 2 (a) and 2 (b), the terminal portions of adjacent semiconductor package regions (not shown) may be arranged in a separated state.
Further, as shown in FIGS. 3A and 3B, the semiconductor element mounting substrate 1 of the present embodiment has a pad portion 12-1 formed of a plating layer at the center of the bottom surface 11a of the recess 11. And a plurality of terminal portions 12 composed of a plating layer formed with a step at a predetermined position around the pad portion 12-1 and extending from the bottom surface 11a of the recess 11a to the side surface 11b and the outer surface of the recess 11. 2, the semiconductor element 20 is mounted on the pad portion 12-1 as shown in FIG. 3C, and the upper stage of the terminal portion 12-1 is connected via a connecting member such as a bonding wire 16. The semiconductor element 20 may be configured to be wire-bonded.
次に、本実施形態の半導体素子搭載用基板１を用いた半導体パッケージの製造手順を、図５を用いて説明する。
まず、端子部１２の表面の内部端子接続部に半田１５等を介して半導体素子２０をフリップチップ接続する（図５(a)参照）。
次に、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂２１で封止する（図５(b)参照）。
次に、金属板１０を除去し（図５(c)参照）、所定の半導体パッケージの寸法に切断する（図５(d)参照）。これにより、本実施形態の半導体素子搭載用基板１を用いた半導体パッケージ４０が完成する（図５(e)参照）。
Next, a manufacturing procedure of a semiconductor package using the semiconductor element mounting substrate 1 of the present embodiment will be described with reference to FIG.
First, the semiconductor element 20 is flip-chip connected to the internal terminal connecting portion on the surface of the terminal portion 12 via the solder 15 or the like (see FIG. 5A).
Next, a mold die (not shown) is set, and the semiconductor element mounting side is sealed with a sealing resin 21 (see FIG. 5B).
Next, the metal plate 10 is removed (see FIG. 5C) and cut into a predetermined semiconductor package dimension (see FIG. 5D). Thereby, the semiconductor package 40 using the semiconductor element mounting substrate 1 of the present embodiment is completed (see FIG. 5E).
本実施形態の半導体素子搭載用基板１によれば、金属板１０の一方の側の面に形成された、半導体パッケージの底面サイズよりも小さく、半導体素子の底面サイズよりも大きい凹部１１と、凹部１１の底面１１ａから側面１１ｂおよび凹部１１の外側の面にわたる所定位置に段差をつけて形成されためっき層からなる複数の端子部１２を有して構成したので、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から金属板１０を除去することによって露出するめっき層からなる端子部１２の裏面の外部接続用端子部が、半導体パッケージ４０の底面から側面に向かって段差を有した形状に形成され、側面側の段差部分に空間部が設けられる。このため、本実施形態の半導体素子搭載用基板１を用いて半導体パッケージ４０を製造した場合、例えば、図６(a)〜図６(c)に示すように、半導体パッケージ４０を外部機器（例えば、プリント基板８０）に半田９０を介して接続するときに、リフローにより溶けた半田が、端子部１２の裏面の外部接続用端子部の段差が形成されることによって設けられた空間部に濡れ広がる。その結果、半導体素子２０が搭載された領域を封止樹脂２１で封止した樹脂封止体から金属板１０を除去することによって製造され、裏面側に露出するめっき層からなる外部接続用端子がプリント基板等の外部機器と接続されるタイプの半導体パッケージの製造に用いる半導体素子搭載用基板であっても、半導体パッケージ４０を、半田９０を介して外部基板８０に接続したときの半田の接続状態を、半導体パッケージ４０の側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視確認することができる。 According to the semiconductor element mounting substrate 1 of the present embodiment, the concave portion 11 formed on one surface of the metal plate 10 is smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element, and the concave portion. 11 has a plurality of terminal portions 12 made of a plating layer formed with steps at predetermined positions from the bottom surface 11a to the side surface 11b and the outer surface of the recess 11, so that the region where the semiconductor element is mounted can be formed. The external connection terminal portion on the back surface of the terminal portion 12 made of the plating layer exposed by removing the metal plate 10 from the resin sealing body sealed with the sealing resin is stepped from the bottom surface of the semiconductor package 40 toward the side surface. And a space portion is provided in the step portion on the side surface side. For this reason, when the semiconductor package 40 is manufactured using the semiconductor element mounting substrate 1 of the present embodiment, for example, as shown in FIG. 6A to FIG. When the solder is connected to the printed circuit board 80) via the solder 90 , the solder melted by reflow spreads out in the space provided by forming the step of the external connection terminal portion on the back surface of the terminal portion 12. . As a result, an external connection terminal made of a plating layer that is manufactured by removing the metal plate 10 from the resin sealing body in which the region where the semiconductor element 20 is mounted is sealed with the sealing resin 21 is exposed. Even in the case of a semiconductor element mounting substrate used for manufacturing a semiconductor package of a type connected to an external device such as a printed circuit board, the solder connection state when the semiconductor package 40 is connected to the external substrate 80 via the solder 90 Can be visually confirmed from the side of the edge portion of the external connection terminal made of a plating layer exposed on the side surface of the semiconductor package 40.
次に、実施例１の半導体素子搭載用基板１における端子部１２の表面の内部端子接続部に半田１５等を介して半導体素子２０をフリップチップ接続し（図５(a)参照）、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂２１で封止した（図５(b)参照）。
次に、金属板１０を除去した（図５(c)参照）。
Next, the semiconductor element 20 is flip-chip connected to the internal terminal connection portion on the surface of the terminal portion 12 in the semiconductor element mounting substrate 1 of the first embodiment via the solder 15 or the like (see FIG. 5A), not shown. A mold was set, and the semiconductor element mounting side was sealed with a sealing resin 21 (see FIG. 5B).
Next, the metal plate 10 was removed (see FIG. 5C).
次に、実施例１と同様、比較例１の半導体素子搭載用基板における端子部の表面の内部端子接続部に半田等を介して半導体素子をフリップチップ接続し、図示しないモールド金型をセットし、半導体素子搭載側を封止樹脂で封止し、その後、金属板を除去した。
このとき、金属板を除去した封止樹脂体における半導体素子搭載側とは反対側の面が平坦に形成され、平坦に形成された封止樹脂体の面から外部接続用端子となる端子部を構成するめっき層が露出した状態に仕上がった。
次に、所定の半導体パッケージの寸法に切断した。これにより、比較例１の半導体素子搭載用基板を用いた半導体パッケージを得た。
次に、比較例１の半導体素子搭載用基板を用いた半導体パッケージの外部接続用端子を外部機器であるプリント基板の端子に半田接続して、プリント基板に装着した。
Next, as in Example 1, the semiconductor element is flip-chip connected to the internal terminal connection part on the surface of the terminal part of the semiconductor element mounting substrate of Comparative Example 1 via solder or the like , and a mold die (not shown) is set. The semiconductor element mounting side was sealed with a sealing resin, and then the metal plate was removed.
At this time, the surface opposite to the semiconductor element mounting side of the sealing resin body from which the metal plate has been removed is formed flat, and the terminal portion serving as the external connection terminal is formed from the flat surface of the sealing resin body. The finished plating layer was exposed.
Next, it was cut into dimensions of a predetermined semiconductor package. Thereby, a semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 was obtained.
Next, the external connection terminal of the semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 was solder-connected to the terminal of the printed circuit board which is an external device and mounted on the printed circuit board.
外部機器接続後の半田接続状態の外観観察のし易さの比較
実施例１及び比較例１の夫々の半導体素子搭載用基板を用いて製造した夫々の半導体パッケージを、半田を介して外部機器であるプリント基板の端子へ接続後の半田接続状態の外観観察のし易さを比較した。
比較例１の半導体素子搭載用基板を用いて製造した半導体パッケージを外部機器であるプリント基板の端子へ接続した場合、半導体パッケージの側面からの半田のはみ出しが無く、外部接続用端子部と外部機器であるプリント基板の端子との半田接続状態を目視確認することが難しかった。
これに対し、実施例１の半導体素子搭載用基板１を用いて製造した半導体パッケージ４０を外部機器であるプリント基板８０の端子へ接続した場合、半導体パッケージ４０の側面に全ての端子部１２の外部機器側の面と外部機器であるプリント基板８０の端子との間に半田が充填されていることを、半導体パッケージ４０の側面に露出しためっき層からなる外部接続用端子の端縁部の側から目視で確認することができた。
Ease of observing appearance of solder connection after connection of external device Comparative Example 1 and Comparative Example 1 using each semiconductor element mounting substrate, each semiconductor package is connected to the external device via solder. The ease of visual observation of the solder connection state after connection to a terminal of a certain printed circuit board was compared.
When a semiconductor package manufactured using the semiconductor element mounting substrate of Comparative Example 1 is connected to a terminal of a printed circuit board, which is an external device, there is no protrusion of solder from the side surface of the semiconductor package, and the external connection terminal portion and the external device It was difficult to visually confirm the solder connection state with the terminal of the printed circuit board.
On the other hand, when the semiconductor package 40 manufactured using the semiconductor element mounting substrate 1 according to the first embodiment is connected to the terminals of the printed circuit board 80 which is an external device, all the terminal portions 12 are arranged on the side surfaces of the semiconductor package 40. The fact that the solder is filled between the device side surface and the terminal of the printed circuit board 80 which is an external device indicates from the end edge side of the external connection terminal made of a plating layer exposed on the side surface of the semiconductor package 40. It was confirmed visually.
１ 半導体素子搭載用基板
１０ 金属板
１０ａ 金属板の一方の側の面
１１ 凹部
１１ａ 底面
１１ｂ 側面
１２ 端子部
１５ 半田
１６ ボンディングワイヤ
２０、６０ 半導体素子
２１、７０ 封止樹脂
３１ エッチング用レジストマスク
３２ めっき用レジストマスク
４０ 半導体パッケージ
５１ 端子部（外部接続用端子）
５１ａ 空間部
５１ｂ 溝
５２ パッド部
６１ ボンディングワイヤ
８０ 外部機器（プリント基板）
８１ 端子
９０ 半田
Ｒ１ 第１のレジスト層
Ｒ２ 第２のレジスト層
DESCRIPTION OF SYMBOLS 1 Semiconductor device mounting substrate 10 Metal plate 10a One side surface of metal plate 11 Recess 11a Bottom surface 11b Side surface 12 Terminal portion 15 Solder 16 Bonding wire 20, 60 Semiconductor element 21, 70 Sealing resin 31 Resist mask for etching 32 Plating Resist mask 40 Semiconductor package 51 Terminal (External connection terminal)
51a Space 51b Groove 52 Pad 61 Bonding Wire 80 External Device (Printed Circuit Board)
81 terminal 90 solder R1 first resist layer R2 second resist layer
Claims (4)
前記金属板の一方の側からハーフエッチング加工を施し、凹部を形成する工程と、
前記金属板の一方の側の面上に形成した前記エッチング用レジストマスクを除去する工程と、
前記金属板の一方の側の面上に、前記凹部の底面から側面および該凹部の外側の面にわたる所定位置に対応する領域に複数の開口部を有するめっき用レジストマスクを形成する工程と、
前記めっき用レジストマスクの開口部にめっき加工を施し、段差のついた複数の端子部を形成する工程と、
前記金属板の両面上に形成したレジストマスクを除去する工程と、
を有することを特徴とする半導体素子搭載用基板の製造方法。 An etching resist mask having an opening smaller than the bottom size of the semiconductor package and larger than the bottom size of the semiconductor element is formed on one side of the metal plate, and the other side of the metal plate Forming a resist mask for etching covering the entire surface;
Applying half-etching from one side of the metal plate to form a recess;
Removing the etching resist mask formed on the surface on one side of the metal plate;
Forming a resist mask for plating having a plurality of openings in a region corresponding to a predetermined position from the bottom surface of the concave portion to the side surface and the outer surface of the concave portion on the surface of one side of the metal plate;
Plating the opening of the resist mask for plating, and forming a plurality of terminal portions with steps; and
Removing the resist mask formed on both surfaces of the metal plate;
A method for manufacturing a substrate for mounting a semiconductor element, comprising:
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| CN111924795B (en) * | 2020-07-17 | 2021-06-22 | 诺思(天津)微系统有限责任公司 | Device packaging module, packaging method and electronic device with module |
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