TW201919182A - Semiconductor element mounting substrate and manufacturing method thereof - Google Patents
Semiconductor element mounting substrate and manufacturing method thereof Download PDFInfo
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- TW201919182A TW201919182A TW107123802A TW107123802A TW201919182A TW 201919182 A TW201919182 A TW 201919182A TW 107123802 A TW107123802 A TW 107123802A TW 107123802 A TW107123802 A TW 107123802A TW 201919182 A TW201919182 A TW 201919182A
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- semiconductor element
- metal plate
- semiconductor package
- concave portion
- mounting substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 333
- 239000000758 substrate Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 238000007747 plating Methods 0.000 claims abstract description 107
- 238000005530 etching Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 12
- 239000011347 resin Substances 0.000 abstract description 68
- 229920005989 resin Polymers 0.000 abstract description 68
- 238000007789 sealing Methods 0.000 abstract description 60
- 229910000679 solder Inorganic materials 0.000 description 72
- 238000005520 cutting process Methods 0.000 description 20
- 239000000047 product Substances 0.000 description 16
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000000126 substance Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000009736 wetting Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000002594 fluoroscopy Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
- 238000012800 visualization Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明涉及用於製造如下類型的半導體封裝件的半導體元件搭載用基板以及其製造方法，即半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且將在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。The present invention relates to a semiconductor element mounting substrate for manufacturing a semiconductor package in which a metal sealing member is removed from a resin sealing body in which a region in which a semiconductor element is mounted is sealed with a sealing resin, and a method for manufacturing the same. A semiconductor package of a type in which an external connection terminal made of a plating layer exposed on the back side is connected to an external device such as a printed circuit board.
當向電子相關設備組裝半導體裝置時，需求焊料連接部分的視覺化，以便能夠目視來檢查半導體裝置的外部連接用端子與外部的電子相關設備之間的焊料連接狀態的合格、不合格。When assembling a semiconductor device to an electronic related device, visualization of the solder connection portion is required so that the pass or fail of the solder connection state between the external connection terminal of the semiconductor device and the external electronic related device can be visually checked.
然而，現今，對於外部連接用端子不在外周部突出的類型的半導體封裝件而言，由於成為將排列成在背面側露出的狀態的複數個外部連接用端子與印刷電路基板等外部設備連接的構造，因而難以正常地目視檢查是否進行了焊接連接。However, in the semiconductor package of the type in which the terminal for external connection does not protrude in the outer peripheral portion, the plurality of external connection terminals that are arranged to be exposed on the back side are connected to an external device such as a printed circuit board. Therefore, it is difficult to visually check whether a welded joint has been made.
但是，若無法進行焊料連接部分的目視檢查，則會看漏在焊接連接作業時內在的連接不合格，額外需要在之後的通電檢查等中直至發現連接不合格的作業成本。並且，雖然焊料連接部分能夠使用X射線裝置來透視檢查，但這樣的話，X射線裝置的設備成本增大。However, if the visual inspection of the solder joint portion is not possible, the internal connection failure at the time of the solder joint operation will be overlooked, and it is necessary to additionally find the operation cost of the connection failure in the subsequent power-on inspection or the like. Also, although the solder joint portion can be fluoroscopy using an X-ray device, in this case, the equipment cost of the X-ray device is increased.
因此，過去以來，作為用於能夠目視檢查半導體封裝件的焊料連接部分處的焊料連接狀態的合格、不合格的技術，例如在專利文獻1中提出了如下技術：通過在引線框中的引線的背面側的成為外部連接用端子的端子部的切斷位置形成橫切引線的槽，在分別切斷時的半導體封裝件的在背面露出的外部連接用端子且直至端緣部地設置空間部，使焊料介於空間部，能夠從在半導體封裝件的側面露出的外部連接用端子的端緣部目視焊料連接部分。Therefore, in the past, as a pass and fail technique for visually checking the solder joint state at the solder joint portion of the semiconductor package, for example, Patent Document 1 proposes a technique in which the lead wire is passed through the lead frame. The cutting position of the terminal portion that serves as the external connection terminal on the back side forms a groove that crosses the lead, and the external connection terminal that is exposed on the back surface of the semiconductor package at the time of the cutting is provided, and the space portion is provided at the edge portion. The solder is interposed between the space portions, and the solder connection portion can be visually observed from the end edge portion of the external connection terminal exposed on the side surface of the semiconductor package.
並且，例如，專利文獻2中記載了如下技術：在引線框的背面設置凹部，當對表面側進行了樹脂密封後，從密封樹脂側對包括凹部在內的既定區域實施半切加工，在設有凹部的部位形成通孔，接下來，以比半切加工的寬度窄的寬度來實施全切加工，從而使外部連接用端子向側方突出，並在側方的突出部設置用於能夠目視焊料連接部分的通孔、狹縫。 ［現有技術文獻］ ［專利文獻］Further, for example, Patent Document 2 discloses a technique in which a concave portion is provided on the back surface of the lead frame, and after the surface side is resin-sealed, a predetermined area including the concave portion is subjected to half-cut processing from the sealing resin side, and is provided. The through hole is formed in the portion of the recess, and then the full cutting process is performed at a width narrower than the width of the half-cut process, so that the external connection terminal protrudes laterally and is provided on the side protrusion for visually connecting the solder. Part of the through hole, slit. [Prior Art Document] [Patent Literature]
專利文獻1：日本特開2000-294715號公報 專利文獻2：日本特開2011-124284號公報Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-294715. Patent Document 2: JP-A-2011-124284
［發明所欲解決之問題］[The problem that the invention wants to solve]
近年來，以行動電話為代表，電子設備的小型、輕型化迅速發展，對於上述電子設備所使用的半導體裝置也要求小型、輕型化、高功能化，尤其對於半導體裝置的厚度，要求輕薄化，從而開發出最終除去金屬板的類型的半導體封裝件來代替使用了加工金屬板而成的引線框的半導體裝置。In recent years, the use of mobile phones has led to the development of small and lightweight electronic devices. The semiconductor devices used in the above-mentioned electronic devices are also required to be small, lightweight, and highly functional, and in particular, the thickness of semiconductor devices is required to be light and thin. Thus, a semiconductor package of a type that finally removes a metal plate was developed instead of a semiconductor device using a lead frame formed by processing a metal plate.
例如，在金屬板的一側的表面形成實施既定的圖案成形的抗蝕劑遮罩（Resist mask），對從抗蝕劑遮罩露出的金屬板實施電鍍加工，在形成有半導體元件搭載用的焊墊部以及成為用於與半導體元件連接的內部連接用端子和用於與外部設備連接的外部連接用端子的端子部後，除去抗蝕劑遮罩，由此製造半導體元件搭載用基板。而且，在製造出的半導體元件搭載用基板搭載半導體元件，在進行了引線接合或者倒裝片(Flip-Chip)連接後進行樹脂密封，並在進行了樹脂密封後除去金屬板，使由鍍層構成的焊墊部、端子部在密封樹脂的背面露出，完成薄型的半導體封裝件。 根據這種半導體封裝件，焊墊部、端子部由壁厚比金屬板的壁厚薄的鍍層形成，而且除去了金屬板，從而能夠進一步使半導體封裝件的厚度變薄。For example, a resist mask that performs predetermined pattern formation is formed on one surface of a metal plate, and a metal plate exposed from the resist mask is plated, and a semiconductor element is mounted. After the pad portion and the terminal portion for the internal connection terminal for connection to the semiconductor element and the external connection terminal for connection to the external device, the resist mask is removed, thereby manufacturing the semiconductor element mounting substrate. In addition, the semiconductor element mounting substrate is mounted with a semiconductor element, and after wire bonding or flip-chip bonding, resin sealing is performed, and after sealing with a resin, the metal plate is removed to form a plating layer. The pad portion and the terminal portion are exposed on the back surface of the sealing resin to complete a thin semiconductor package. According to such a semiconductor package, the pad portion and the terminal portion are formed of a plating layer having a thickness smaller than that of the metal plate, and the metal plate is removed, so that the thickness of the semiconductor package can be further reduced.
但是，專利文獻1、2所記載的用於能夠目視檢查半導體封裝件的焊料連接部分處的焊料連接狀態的合格、不合格的技術無法在用於製造如下類型的半導體裝置的半導體元件搭載用基板中應用，即：半導體裝置是除去金屬板而在背面露出的鍍層構成成為外部連接用端子的端子部的類型的半導體裝置。 即，在專利文獻1、2所記載的技術中，通過對由金屬板構成的引線框實施蝕刻加工、衝壓加工來形成前階段的凹部，該前階段的凹部形成用於使焊料連接部分能夠目視的槽、通孔、狹縫。但是，在用於製造「除去金屬板而在背面露出的鍍層構成成為外部連接用端子的端子部的類型」的半導體裝置的半導體元件搭載用基板的情況下，對鍍層實施專利文獻1、2所記載的技術的蝕刻加工、衝壓加工來形成槽、凹部是非常困難。However, the technique of failing to pass the solder connection state in the solder joint portion of the semiconductor package, which is described in the patent documents 1 and 2, is not acceptable for the semiconductor element mounting substrate for manufacturing a semiconductor device of the following type. In a semiconductor device, a semiconductor device is a type of semiconductor device in which a plating layer exposed on a back surface is removed and a terminal portion of an external connection terminal is formed. In other words, in the techniques described in Patent Documents 1 and 2, the lead frame formed of a metal plate is subjected to etching processing and press working to form a concave portion in the previous stage, and the concave portion in the previous stage is formed to allow the solder connection portion to be visually observed. Slots, through holes, slits. However, in the case of a semiconductor element mounting substrate of a semiconductor device for manufacturing a semiconductor device in which a metal plate is removed and a plating layer formed on the back surface is formed as a terminal portion for external connection terminals, Patent Documents 1 and 2 are applied to the plating layer. It is extremely difficult to form grooves and recesses by etching or press working of the described technique.
而且，在專利文獻1所記載的引線框中的引線的背面側的成為外部連接用端子的端子部的切斷位置形成橫切引線的槽的技術中，在進行樹脂密封時，樹脂進入端子部的槽，不能形成用於使焊料連接部分能夠目視的空間部，從而有半導體封裝產品的良率變差的擔憂。Further, in the technique of forming a groove transverse to the lead at the cutting position of the terminal portion serving as the external connection terminal on the back side of the lead wire in the lead frame described in Patent Document 1, the resin enters the terminal portion during resin sealing. The groove does not form a space portion for allowing the solder joint portion to be visually observed, and there is a concern that the yield of the semiconductor package product is deteriorated.
並且，在專利文獻2所記載的技術中，在進行了樹脂密封後，需要使用刀片的半切和全切的兩次切斷步驟，從而生產效率較差，且成本增大。而且，由於外部連接用端子向側方突出，所以難以使半導體封裝產品變得小型。Further, in the technique described in Patent Document 2, after the resin sealing, it is necessary to use the half-cutting and the full-cutting cutting steps of the blade, which results in poor production efficiency and an increase in cost. Further, since the external connection terminals protrude laterally, it is difficult to make the semiconductor package product small.
這樣，對於將在背面側露出的複數個外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件中的、用於使焊料連接部分能夠目視的現有技術中，在半導體封裝產品的良率、生產效率、產品的小型化的方面存在問題，而且，對於在背面側露出的成為外部連接用端子的端子部由鍍層構成的類型的半導體封裝件中應用上述現有技術本身是困難的。In the prior art, in a semiconductor package of a type in which a plurality of external connection terminals exposed on the back side are connected to an external device such as a printed circuit board, the solder connection portion can be visually observed, in a semiconductor package product. There is a problem in terms of the yield, the production efficiency, and the miniaturization of the product, and it is difficult to apply the above-described prior art to the semiconductor package of the type in which the terminal portion which is the terminal for external connection exposed on the back side is made of a plating layer. .
本發明是鑒於上述現有的課題而完成的，其目的在於在用於製造如下類型的半導體封裝件的半導體元件搭載用基板中，提供能夠提高半導體封裝產品的良率、生產效率，也能夠對應於小型化，而且使焊料連接部分能夠目視的半導體元件搭載用基板以及其製造方法，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。［解決問題之技術手段］The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor device mounting substrate for manufacturing a semiconductor package of the following type, which can improve the yield and production efficiency of a semiconductor packaged product, and can also correspond to The semiconductor element mounting substrate which is obtained by removing a metal plate from a resin sealing body in which a region in which a semiconductor element is mounted is sealed with a sealing resin, and a method for producing a semiconductor element mounting portion which can be visually observed. A semiconductor package of a type in which an external connection terminal made of a plating layer which is exposed on the back side is connected to an external device such as a printed circuit board. [Technical means to solve the problem]
為了實現上述目的，本發明的一個方案的半導體元件搭載用基板的特徵在於，具有：凹部，其形成於金屬板的一側的表面並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大；和複數個端子部，由鍍層構成，並且在從上述凹部的底面至側面以及該凹部的外側的表面的既定位置帶有段差地形成。In order to achieve the above object, a semiconductor element mounting substrate according to an aspect of the present invention includes: a concave portion formed on a surface of one side of a metal plate and having a size smaller than a bottom surface of the semiconductor package and a bottom surface of the semiconductor element The size is large; and the plurality of terminal portions are formed of a plating layer, and are formed with a step difference at a predetermined position from the bottom surface to the side surface of the concave portion and the outer surface of the concave portion.
並且，本發明的其它方案的半導體元件搭載用基板的特徵在於，具有：凹部，其形成於金屬板的一側的表面，並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大；焊墊部，其由鍍層形成在上述凹部的底面的中央部；以及複數個端子部，由鍍層構成，並且在上述焊墊部的周邊且在從上述凹部的上述底面至側面以及該凹部的外側的表面的既定位置帶有段差地形成。Further, a substrate for mounting a semiconductor element according to another aspect of the present invention includes: a recess formed on a surface of one side of the metal plate, and having a size smaller than a size of a bottom surface of the semiconductor package and larger than a size of a bottom surface of the semiconductor element a pad portion formed in a central portion of a bottom surface of the recessed portion by a plating layer; and a plurality of terminal portions formed of a plating layer, and at a periphery of the pad portion and from the bottom surface to the side surface of the recess portion and the recess portion The predetermined position of the outer surface is formed with a step difference.
並且，在本發明的半導體元件搭載用基板中，上述凹部的深度較佳為0.005mm~0.11mm。Further, in the semiconductor element mounting substrate of the present invention, the depth of the concave portion is preferably 0.005 mm to 0.11 mm.
並且，本發明的半導體元件搭載用基板的製造方法的特徵在於，具有：在金屬板的一側的表面上形成具有尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的開口部的蝕刻用抗蝕劑遮罩，並且在上述金屬板的另一側的表面上形成覆蓋整個面的蝕刻用抗蝕劑遮罩的步驟；從上述金屬板的一側實施半蝕刻加工來形成凹部的步驟；將形成於上述金屬板的一側的表面上的上述蝕刻用抗蝕劑遮罩除去的步驟；在上述金屬板的一側的表面上形成有在與從上述凹部的底面至側面以及該凹部的外側的表面的既定位置對應的區域具有複數個開口部的電鍍用抗蝕劑遮罩的步驟；對上述電鍍用抗蝕劑遮罩的開口部實施電鍍加工來形成帶有段差的複數個端子部的步驟；以及將形成於上述金屬板的兩面上的抗蝕劑遮罩除去的步驟。 ［發明之功效］Further, in the method of manufacturing a substrate for mounting a semiconductor element of the present invention, an opening having a size smaller than a size of a bottom surface of the semiconductor package and larger than a size of a bottom surface of the semiconductor element is formed on one surface of the metal plate. The etching is covered with a resist, and a step of masking the entire surface of the etching resist is formed on the surface of the other side of the metal plate; and a half etching process is performed from one side of the metal plate to form a concave portion a step of removing the etching resist formed on a surface of one side of the metal plate; forming a surface on one side of the metal plate and a surface from the bottom surface to the side surface of the concave portion a region corresponding to a predetermined position of the outer surface of the concave portion has a step of masking a plating resist for a plurality of openings; and the opening portion of the resist mask for plating is plated to form a plurality of steps with a step a step of the terminal portion; and a step of removing the resist mask formed on both surfaces of the metal plate. [Effects of the invention]
根據本發明，在用於製造如下類型的半導體封裝件的半導體元件搭載用基板中，可得到能夠提高半導體封裝產品的良率、生產效率，也能夠對應於小型化，而且使焊料連接部分能夠目視的半導體元件搭載用基板以及其製造方法，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。According to the present invention, in the semiconductor element mounting substrate for manufacturing a semiconductor package of the following type, it is possible to improve the yield and production efficiency of the semiconductor package product, and it is also possible to reduce the size and make the solder connection portion visually compatible. The semiconductor element mounting substrate which is produced by removing a metal plate from a resin sealing body in which a region in which a semiconductor element is mounted is sealed with a sealing resin, and which is exposed on the back side, is formed of a plating layer, and a method for producing the same. The external connection terminal is a semiconductor package of a type in which a terminal is connected to an external device such as a printed circuit board.
在說明實施方式之前，對導出本發明的經過以及本發明的作用效果進行說明。 首先，本件發明人對用於使半導體封裝件的焊料連接部分能夠目視的現有技術的專利文獻1所記載的技術進行了研究、考察。 使用圖7對專利文獻1所記載的技術進行說明。圖7的（a）是從用於半導體封裝件的引線框的與外部設備連接的一側觀察的圖，（b）是使用（a）的引線框組裝成的半導體封裝件的（a）的A-A剖視圖，（c）是示出將（b）的半導體封裝件的外部連接用端子焊接連接於外部設備的狀態的圖，（d）是示出（a）的引線框的成為外部連接用端子的端子部的B-B剖視圖。Before explaining the embodiment, the process of deriving the invention and the effects of the invention will be described. First, the inventors of the present invention have studied and examined the technique described in the prior art Patent Document 1 for allowing the solder joint portion of the semiconductor package to be visually observed. The technique described in Patent Document 1 will be described with reference to Fig. 7 . (a) of FIG. 7 is a view seen from a side of a lead frame for a semiconductor package connected to an external device, and (b) is a (a) of the semiconductor package assembled using the lead frame of (a) (A) is a view showing a state in which the external connection terminal of the semiconductor package of (b) is soldered to an external device, and (d) is a terminal for external connection of the lead frame of (a). BB cross-sectional view of the terminal portion.
就圖7的（a）所示的用於半導體封裝件的引線框而言，在引線框中的引線的背面側的成為外部連接用端子的端子部51的切斷位置（圖7的（a）中的點劃線上的位置），對由Fe-Ni合金、Cu合金等金屬板構成的引線框實施蝕刻加工、衝壓加工來形成橫切引線的槽51b。此外，圖7的（a）中，52是用於搭載半導體元件的焊墊部，60是半導體元件。 而且，在引線框的焊墊部52搭載半導體元件60，用接合線61來連接引線的半導體元件60搭載側的作為內部連接端子的端子部和半導體元件60，並且沿切斷位置將用密封樹脂70密封了半導體元件搭載側的狀態下的半導體封裝件切斷，由此如圖7的（b）所示，在分別切斷後的半導體封裝件的在背面露出的引線的外部連接用端子51處且直至端緣部地設置空間部51a。 如圖7的（c）所示，這樣形成的半導體封裝件在與外部設備80的端子81焊接連接後的狀態下，焊料90介於從外部連接用端子51的背面直至端緣部地形成的空間部51a。因此，能夠目視確認在半導體封裝件的側面露出的外部連接用端子51的焊料連接部分，能夠目視檢查半導體封裝件與外部設備80的焊料連接狀態的合格、不合格。In the lead frame for a semiconductor package shown in (a) of FIG. 7, the cutting position of the terminal portion 51 serving as the external connection terminal on the back side of the lead wire in the lead frame ((a of FIG. 7) In the position of the dotted line in the ), the lead frame made of a metal plate such as an Fe-Ni alloy or a Cu alloy is subjected to etching processing or press working to form a groove 51b that crosses the lead. In addition, in (a) of FIG. 7, 52 is a pad part for mounting a semiconductor element, and 60 is a semiconductor element. In addition, the semiconductor element 60 is mounted on the pad portion 52 of the lead frame, and the terminal portion as the internal connection terminal and the semiconductor element 60 on the side on which the semiconductor element 60 on the semiconductor element 60 of the lead is mounted is connected by the bonding wire 61, and the sealing resin is used along the cutting position. When the semiconductor package is cut in the state in which the semiconductor element mounting side is sealed, as shown in FIG. 7( b ), the external connection terminal 51 of the lead exposed on the back surface of the semiconductor package after the cutting is respectively cut. The space portion 51a is provided up to the end edge portion. As shown in FIG. 7(c), in a state in which the semiconductor package thus formed is soldered to the terminal 81 of the external device 80, the solder 90 is formed from the back surface of the external connection terminal 51 to the edge portion. Space portion 51a. Therefore, the solder connection portion of the external connection terminal 51 exposed on the side surface of the semiconductor package can be visually confirmed, and the solder connection state of the semiconductor package and the external device 80 can be visually inspected for failure or failure.
然而，在專利文獻1所記載的技術中，通過對由Fe-Ni合金、Cu合金等金屬板構成的引線框實施蝕刻加工、衝壓加工，來形成用於使焊料連接部分能夠目視的橫切引線的槽51b。 但是，在用於製造「除去金屬板而在背面露出的鍍層構成作為外部連接用端子發揮功能的端子部的類型」的半導體封裝件的半導體元件搭載用基板的情況下，通過對鍍層實施蝕刻加工、衝壓加工來形成槽是非常困難的。 並且，若如專利文獻1所記載的技術那樣，在引線框中的引線的背面側的成為外部連接用端子51的端子部的切斷位置形成橫切引線的槽51b，則在半導體封裝件的組裝中的樹脂密封時，樹脂進入端子部的槽51b，從而有不能形成用於使焊料連接部分能夠目視的空間部51a的擔憂。 即，若在引線框中的引線的背面側的成為外部連接用端子的端子部51形成橫切引線的槽51b，則成為外部連接用端子的端子部51在切斷位置處如圖7的（d）所示，引線的寬度方向整體形成為薄壁狀。一般而言，在對引線框的半導體元件搭載側進行樹脂密封時，為使樹脂不會進入引線框的背面的槽，在引線框的背面黏貼片狀的帶體。但是，由於在沿引線的寬度方向的槽51b的外側部分不存在與片狀的帶體緊貼的表面，所以沿引線的寬度方向的槽51b的外側部分從片狀的帶體分離。此處，由於片狀的帶體會較大地變形，所以即使使片狀的帶體緊貼於槽51b的表面，片狀的帶體也難以完全緊貼於槽51b，從而在片狀的帶體與槽51b的表面之間容易產生縫隙。其結果，在進行樹脂密封時，樹脂從片狀的帶體與槽51b的表面之間的縫隙蔓延，樹脂進入端子部51的槽51b，不能形成用於使焊料連接部分能夠目視檢查的空間部，因此有半導體封裝產品的良率變差的擔憂。However, in the technique described in Patent Document 1, a lead frame made of a metal plate such as an Fe-Ni alloy or a Cu alloy is subjected to an etching process or a press process to form a cross-cut wire for allowing the solder connection portion to be visually observed. Slot 51b. However, in the case of a semiconductor element mounting substrate for a semiconductor package in which a type of a terminal portion that functions as a terminal for external connection is formed by a plating layer having a metal plate removed and a metal plate is used as the external connection terminal, the plating layer is etched. It is very difficult to form a groove by stamping. In the semiconductor package, the groove 51b that crosses the lead is formed at the cutting position of the terminal portion of the external connection terminal 51 on the back side of the lead wire in the lead frame, as in the technique described in Patent Document 1. When the resin during assembly is sealed, the resin enters the groove 51b of the terminal portion, and there is a concern that the space portion 51a for allowing the solder connection portion to be visually observed cannot be formed. In other words, when the terminal portion 51 serving as the external connection terminal on the back side of the lead wire in the lead frame forms the groove 51b that crosses the lead, the terminal portion 51 serving as the external connection terminal is at the cutting position as shown in FIG. 7 ( As shown in d), the entire width direction of the lead wire is formed into a thin wall shape. In general, when the semiconductor element mounting side of the lead frame is resin-sealed, a sheet-like tape body is adhered to the back surface of the lead frame so that the resin does not enter the groove on the back surface of the lead frame. However, since the outer surface of the groove 51b in the width direction of the lead wire does not have a surface in contact with the sheet-like tape body, the outer portion of the groove 51b in the width direction of the lead wire is separated from the sheet-like tape body. Here, since the sheet-like belt body is largely deformed, even if the sheet-like belt body is brought into close contact with the surface of the groove 51b, it is difficult for the sheet-like belt body to completely abut against the groove 51b, so that the sheet-like belt body is in the sheet-like belt body. A gap is easily generated between the surface of the groove 51b. As a result, when the resin sealing is performed, the resin spreads from the gap between the sheet-like strip and the surface of the groove 51b, and the resin enters the groove 51b of the terminal portion 51, and the space portion for allowing the solder connecting portion to be visually inspected cannot be formed. Therefore, there is concern that the yield of semiconductor package products is deteriorating.
接下來，專利文獻2所記載的技術也是通過對由形成有圖案的金屬板構成的引線框實施衝壓加工，來形成前階段的凹部，該前階段的凹部形成通孔、狹縫以此來使焊料連接部分能夠目視，但是，在用於製造「除去金屬板而在背面側露出的鍍層構成成為外部連接用端子的端子部的類型」的半導體裝置的半導體元件搭載用基板的情況下，通過對鍍層實施衝壓加工來形成凹部是非常困難的。 並且，在進行了樹脂密封後，需要使用刀片來進行半切和全切的兩次切斷步驟，從而生產效率較差，且成本增大。而且，由於外部連接用端子朝向橫向突出，所以難以使半導體封裝產品變得小型。Next, in the technique described in Patent Document 2, the lead frame formed of the metal plate on which the pattern is formed is subjected to press working to form the concave portion in the previous stage, and the concave portion in the previous stage is formed with a through hole and a slit. In the case of a semiconductor element mounting substrate of a semiconductor device for manufacturing a semiconductor device in which a metal plate is removed and the plating layer exposed on the back side is formed as a terminal portion of the external connection terminal, the semiconductor device mounting substrate is used. It is very difficult to perform a stamping process on the plating to form a recess. Further, after the resin sealing is performed, it is necessary to use a blade to perform the half-cutting and full-cutting two cutting steps, resulting in poor production efficiency and increased cost. Moreover, since the external connection terminal protrudes in the lateral direction, it is difficult to make the semiconductor package product small.
因此，本件發明人在用於製造如下類型的半導體封裝件的半導體元件搭載用基板中為了提高半導體封裝產品的良率、生產效率，也能夠對應於小型化，而且使焊料連接部分能夠目視，反復嘗試，直至導出本發明的半導體元件搭載用基板以及其製造方法，的半導體元件搭載用基板以及其製造方法，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。Therefore, in order to improve the yield and production efficiency of the semiconductor packaged product, the inventors of the present invention can also reduce the size and the production efficiency of the semiconductor packaged product, and the solder connection portion can be visually observed and repeated. In the semiconductor element mounting substrate and the method of manufacturing the semiconductor device mounting substrate of the present invention, the semiconductor package is obtained by sealing a region in which a semiconductor element is mounted with a sealing resin. A resin package of a type in which a resin sealing body is manufactured by removing a metal plate and is connected to an external device such as a printed circuit board, and a terminal for external connection formed of a plating layer exposed on the back side.
本發明的一個方案的半導體元件搭載用基板具有：凹部，其形成於金屬板的一側的表面，並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大；和複數個端子部，由鍍層構成，並且在從凹部的底面至側面以及凹部的外側的表面的既定位置帶有段差地形成。 並且，本發明的其它方案的半導體元件搭載用基板具有：凹部，其形成於金屬板的一側的表面，並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大；焊墊部，其由鍍層形成在凹部的底面的中央部；以及複數個端子部，由鍍層構成，並且在焊墊部的周邊且在從凹部的底面至側面以及凹部的外側的表面的既定位置帶有段差地形成。A substrate for mounting a semiconductor element according to an aspect of the present invention includes: a recess formed on a surface of one side of the metal plate, and having a size smaller than a bottom surface of the semiconductor package and larger than a bottom surface of the semiconductor element; and a plurality of terminal portions It is formed of a plating layer and is formed with a step at a predetermined position from the bottom surface to the side surface of the concave portion and the outer surface of the concave portion. Further, the substrate for mounting a semiconductor element according to another aspect of the present invention includes: a recess formed on a surface of one side of the metal plate, and having a size smaller than a size of a bottom surface of the semiconductor package and larger than a size of a bottom surface of the semiconductor element; a pad portion The plating layer is formed at a central portion of the bottom surface of the concave portion; and the plurality of terminal portions are formed of a plating layer, and have a step at a predetermined position from the bottom surface to the side surface of the concave portion and the outer surface of the concave portion at the periphery of the pad portion. Ground formation.
如本發明的半導體元件搭載用基板所述，若構成為具有：形成於金屬板的一側的表面並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的凹部；以及在從凹部的底面至側面以及凹部的外側的表面的既定位置具帶段差地形成且由鍍層構成的複數個端子部，則在使用本發明的半導體元件搭載用基板來製造半導體封裝件的情況下，對於通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板而露出的由鍍層構成的端子部的背面的外部連接用端子部而言，其形成為從半導體封裝件的底面朝向側面具有段差的形狀，並在側面側的段差部分設置空間部。因此，當將半導體封裝件經由焊料與外部基板連接時，因回流而熔融了的焊料潤濕擴展到通過形成外部連接用端子部的段差而設置的空間部。其結果，即使在用於製造如下類型的半導體封裝件的半導體元件搭載用基板，也能夠從在半導體封裝件的側面露出的由鍍層構成的外部連接用端子的端緣部的一側目視確認：經由焊料將半導體封裝件連接至外部基板時的焊料的連接狀態，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。The semiconductor element mounting substrate according to the present invention is configured to have a recess formed on a surface of one side of the metal plate and having a size smaller than a bottom surface of the semiconductor package and larger than a bottom surface of the semiconductor element; In the case where the semiconductor package is manufactured using the semiconductor element mounting substrate of the present invention, a plurality of terminal portions formed of a plating layer are formed at a predetermined position on the surface of the concave portion from the bottom surface to the side surface and the outer surface of the concave portion. The external connection terminal portion of the rear surface of the terminal portion formed of the plating layer exposed by removing the metal plate from the resin sealing body in which the semiconductor element is mounted by the sealing resin is formed to be formed from the bottom surface of the semiconductor package The shape has a stepped shape toward the side surface, and a space portion is provided in the step portion on the side surface side. Therefore, when the semiconductor package is connected to the external substrate via the solder, the solder melted by the reflow is spread to the space portion provided by forming the step of the external connection terminal portion. As a result, even in the semiconductor element mounting substrate for manufacturing a semiconductor package of the following type, it can be visually confirmed from the side of the edge portion of the external connection terminal formed of the plating layer exposed on the side surface of the semiconductor package: The connection state of the solder when the semiconductor package is connected to the external substrate via the solder, wherein the semiconductor package is manufactured by removing the metal plate from the resin sealing body in which the region in which the semiconductor element is mounted is sealed with the sealing resin, and is on the back side. A semiconductor package of a type in which an external connection terminal made of a plating layer is connected to an external device such as a printed circuit board.
並且，若如本發明的半導體元件搭載用基板那樣構成，則帶有段差地形成且由鍍層構成的複數個端子部從金屬板的凹部的底面至側面以及凹部的外側的表面以無縫隙的狀態緊貼。因此，與專利文獻1所記載的技術中的槽部不同，在樹脂密封時，沒有樹脂進入端子部的槽而使半導體封裝產品的良率變差的擔憂。Further, in the case of the semiconductor element mounting substrate of the present invention, the plurality of terminal portions which are formed with a step and which are formed of a plating layer are provided in a seamless state from the bottom surface of the concave portion of the metal plate to the side surface and the outer surface of the concave portion. Close to. Therefore, unlike the groove portion in the technique described in Patent Document 1, when the resin is sealed, there is no possibility that the resin enters the groove of the terminal portion and the yield of the semiconductor package product is deteriorated.
並且，若如本發明的半導體元件搭載用基板那樣構成，則與專利文獻2所記載的技術不同，在樹脂密封後，不需要使用刀片的半切和全切的兩次切斷步驟，從而生產效率良好，且能夠減少成本。並且，由於外部連接用端子不向側方突出，所以容易使半導體封裝產品變得小型。Further, in the case of the semiconductor element mounting substrate of the present invention, unlike the technique described in Patent Document 2, it is not necessary to use the half-cutting and the full-cutting two cutting steps of the blade after the resin sealing, thereby achieving production efficiency. Good and able to reduce costs. Further, since the external connection terminals do not protrude to the side, it is easy to make the semiconductor package product small.
此外，在本發明的半導體元件搭載用基板中，帶有段差地形成且由鍍層構成的各個端子部的半導體元件搭載側的表面成為與半導體元件的電極連接的內部連接用端子部，但帶有段差的由鍍層構成的各個端子部的上層和下層的任一區域均能夠與半導體元件的電極連接。 例如，在帶有段差的由鍍層構成的各個端子部的下層和上層的任一面都能夠以倒裝片的方式安裝半導體元件。 若在具有段差且由鍍層構成的各個端子部的下層的表面以倒裝片的方式安裝半導體元件，則能夠將半導體封裝件的厚度減薄相當於鍍層的段差的量。 並且，若在帶有段差且由鍍層構成的各個端子部的上層的表面以倒裝片的方式安裝半導體元件，則在用密封樹脂進行了密封後，能夠較厚地形成蔓延至半導體元件的背面側的密封樹脂的層，也能夠確保密封樹脂與鍍層的緊貼面積寬廣，能夠確保密封樹脂與端子部的連接強度較高。並且，能夠充分確保焊墊部的表面與半導體元件之間的空間，提高絕緣性，難以拾起雜訊。 並且，本發明的半導體元件搭載用基板例如也可以構成為，在凹部的底面的中央部設置由鍍層形成的焊墊部，在焊墊部的周邊且在從凹部的底面至側面以及凹部的外側的表面的既定位置設置帶有段差地形成且由鍍層構成的複數個端子部，能夠在焊墊部的表面搭載半導體元件，並且能夠通過引線接合來連接半導體元件的電極和各個端子部的上層的表面。Further, in the semiconductor element mounting substrate of the present invention, the surface on the semiconductor element mounting side of each terminal portion which is formed with a step and which is formed of a plating layer is an internal connection terminal portion which is connected to the electrode of the semiconductor element, but Any of the upper layer and the lower layer of each terminal portion composed of the plating layer having a step can be connected to the electrode of the semiconductor element. For example, the semiconductor element can be flip-chip mounted on either of the lower layer and the upper layer of each of the terminal portions formed of the plating layer having a step. When the semiconductor element is flip-chip mounted on the surface of the lower layer of each terminal portion having a step and formed of a plating layer, the thickness of the semiconductor package can be reduced by the amount corresponding to the step of the plating layer. Further, when the semiconductor element is flip-chip mounted on the surface of the upper layer of each of the terminal portions having the step and the plating layer is formed, it can be formed to be thickly spread to the back side of the semiconductor element after being sealed with the sealing resin. The layer of the sealing resin can also ensure a wide contact area between the sealing resin and the plating layer, and can secure a high connection strength between the sealing resin and the terminal portion. Further, the space between the surface of the pad portion and the semiconductor element can be sufficiently ensured, the insulation property can be improved, and it is difficult to pick up noise. Further, the semiconductor element mounting substrate of the present invention may be configured such that a pad portion formed of a plating layer is provided at a central portion of the bottom surface of the concave portion, and is formed from the bottom surface of the concave portion to the side surface and the outer side of the concave portion at the periphery of the pad portion. The predetermined position of the surface is provided with a plurality of terminal portions formed of a stepped layer and formed of a plating layer, and the semiconductor element can be mounted on the surface of the pad portion, and the electrode of the semiconductor element and the upper layer of each terminal portion can be connected by wire bonding. surface.
並且，在本發明的半導體元件搭載用基板中，凹部的深度較佳是0.005mm~0.11mm。 例如，若使凹部的深度形成為0.005mm~0.025mm左右，則由於形成於凹部的成為端子部等的鍍層不會從半導體封裝件的背面較大地突出，因而在半導體封裝件的製造中，當從密封樹脂體剝下除去金屬板時，能夠防止形成於凹部的鍍層向金屬板的勾掛，容易剝離金屬板。 並且，例如若使凹部的深度形成為0.03mm~0.06mm左右，則能夠將搭載半導體元件後的半導體元件的背面側與焊墊部等的表面之間的空間確保為可以採取雜訊對策（提高絕緣性，難以拾起雜訊）、焊料洩漏對策（阻止在將半導體元件焊接連接至形成於凹部的底面的成為端子部等的鍍層時的、焊料向鍍層表面與半導體元件的耦合點以外的鍍層整個區域的潤濕擴展，防止阻礙鍍層表面與密封樹脂的緊貼性，並且阻止在將半導體封裝件焊接連接至外部設備時的、焊料向鄰接的端子側的潤濕擴展，從而防止電氣短路）的程度。 並且，例如，若使凹部的深度形成為0.08mm~0.11mm左右，則在具有段差的端子部的背面的外部連接用端子處設置於半導體封裝件的側面側的段差部分的、可介入焊料的空間部的區域在半導體封裝件的厚度方向上增加。其結果，變得更加容易觀察製造半導體封裝件後的外部連接用端子與外部設備的焊料連接狀態。 並且，若使凹部的深度形成為0.08mm~0.11mm左右，則在搭載半導體元件且用密封樹脂進行密封後，在通過藥液的溶化來進行作為基材的金屬板的除去的情況下，能夠以加深凹部的深度的量使熔解的金屬板的體積更少。其結果，能夠抑制在藥液中溶化的金屬板成分的濃度的上升，能夠確保穩定的溶解狀態，能夠減少藥液調整（金屬板成分的濃度變高後的溶液的汲取以及新溶液的補充）。Further, in the semiconductor element mounting substrate of the present invention, the depth of the concave portion is preferably 0.005 mm to 0.11 mm. For example, when the depth of the concave portion is formed to be about 0.005 mm to 0.025 mm, the plating layer serving as the terminal portion or the like formed in the concave portion does not largely protrude from the back surface of the semiconductor package, and thus, in the manufacture of the semiconductor package, When the metal plate is peeled off from the sealing resin body, the plating layer formed in the concave portion can be prevented from being caught on the metal plate, and the metal plate can be easily peeled off. In addition, for example, when the depth of the concave portion is set to be about 0.03 mm to 0.06 mm, the space between the back surface side of the semiconductor element on which the semiconductor element is mounted and the surface of the pad portion or the like can be secured so that noise countermeasures can be taken. (Insulation, it is difficult to pick up noise), and solder leakage measures (preventing the plating of the solder to the surface of the plating layer and the semiconductor element when the semiconductor element is soldered to the plating layer formed on the bottom surface of the concave portion. The wetting spread of the entire region prevents the adhesion of the plating surface to the sealing resin from being impeded, and prevents the solder from spreading to the adjacent terminal side when the semiconductor package is soldered to the external device, thereby preventing electrical short circuit. Degree. In addition, for example, when the depth of the concave portion is formed to be about 0.08 mm to 0.11 mm, the external connection terminal on the back surface of the terminal portion having the step is provided in the step portion on the side surface side of the semiconductor package, and the solder can be interposed. The area of the space portion increases in the thickness direction of the semiconductor package. As a result, it becomes easier to observe the solder connection state of the external connection terminal and the external device after the semiconductor package is manufactured. In addition, when the depth of the concave portion is set to about 0.08 mm to 0.11 mm, the semiconductor element can be mounted and sealed with a sealing resin, and then the metal plate as the substrate can be removed by melting the chemical solution. The volume of the molten metal plate is made smaller by increasing the depth of the recess. As a result, it is possible to suppress an increase in the concentration of the metal plate component dissolved in the chemical solution, and it is possible to ensure a stable dissolved state, and it is possible to reduce the adjustment of the chemical solution (the extraction of the solution after the concentration of the metal plate component is increased and the replenishment of the new solution). .
並且，在本發明的半導體元件搭載用基板中，也可以在一個半導體封裝區域內具有複數個深度不同的凹部。 並且，在本發明的半導體元件搭載用基板中，也可以構成為，凹部的底面具有段差，並且端子部具有三個以上的高度不同的表面。 若端子部具有三個以上的高度不同的表面，則當將半導體封裝件向外部設備進行焊接連接時，經由具有複數個段差的表面將焊料引導至最寬廣的空間區域，容易停留在以最寬廣的空間區域介入焊料的狀態。其結果，容易採取焊料洩漏對策（阻止在將半導體元件焊接連接至形成於凹部的底面的成為端子部等的鍍層時的、焊料向鍍層表面與半導體元件的耦合點以外的鍍層整個區域的潤濕擴展，防止阻礙鍍層表面與密封樹脂的緊貼性，並且阻止在將半導體封裝件焊接連接至外部設備時的、焊料向鄰接的端子側的潤濕擴展，防止電氣短路）。Further, in the semiconductor element mounting substrate of the present invention, a plurality of recesses having different depths may be provided in one semiconductor package region. Further, in the semiconductor element mounting substrate of the present invention, the bottom surface of the concave portion may have a step, and the terminal portion may have three or more surfaces having different heights. If the terminal portion has three or more surfaces having different heights, when the semiconductor package is soldered to an external device, the solder is guided to the widest space region via a surface having a plurality of steps, and it is easy to stay at the widest The space area is involved in the state of the solder. As a result, it is easy to take measures against solder leakage (preventing the wetting of the solder to the entire region of the plating layer other than the coupling point between the surface of the plating layer and the semiconductor element when the semiconductor element is soldered to the plating layer formed as the terminal portion or the like formed on the bottom surface of the concave portion. The expansion prevents the adhesion of the plating surface to the sealing resin from being impeded, and prevents the wetting spread of the solder to the adjacent terminal side when the semiconductor package is soldered to the external device to prevent electrical shorting.
而且，這樣的本發明的半導體元件搭載用基板能夠通過具有如下步驟來製造：在金屬板的一側的表面上形成具有尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的開口部的蝕刻用抗蝕劑遮罩，並且在金屬板的另一側的表面上形成覆蓋整個面的蝕刻用抗蝕劑遮罩的步驟；從金屬板的一側實施半蝕刻加工來形成凹部的步驟；將形成於金屬板的一側的表面上的蝕刻用抗蝕劑遮罩除去的步驟；在金屬板的一側的表面上形成有在從凹部的底面至側面以及凹部的外側的表面的既定位置對應的區域具有複數個開口部的電鍍用抗蝕劑遮罩的步驟；對電鍍用抗蝕劑遮罩的開口部實施電鍍加工來形成帶有段差的複數個端子部的步驟；以及將形成於金屬板的兩面上的抗蝕劑遮罩除去的步驟。Further, the substrate for mounting a semiconductor element of the present invention can be manufactured by forming an opening having a size smaller than the size of the bottom surface of the semiconductor package and larger than the size of the bottom surface of the semiconductor element on the surface of one side of the metal plate. The etching of the portion is masked with a resist, and a step of etching the entire surface of the etching mask is formed on the surface of the other side of the metal plate; and a half etching process is performed from one side of the metal plate to form the concave portion. a step of removing the etching resist formed on the surface of one side of the metal plate; forming a surface on one side of the metal plate from the bottom surface to the side surface of the concave portion and the outer surface of the concave portion a step of masking a plating with a plurality of openings in a region corresponding to a predetermined position; a step of plating a portion of the resist mask for plating to form a plurality of terminal portions having a step; and A step of removing the resist mask formed on both sides of the metal plate.
因此，根據本發明，在用於製造如下類型的半導體封裝件的半導體元件搭載用基板中，可得到能夠提高半導體封裝產品的良率、生產效率，也能夠對應於小型化，而且使焊料連接部分能夠目視的半導體元件搭載用基板以及其製造方法，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。Therefore, according to the present invention, in the semiconductor element mounting substrate for manufacturing a semiconductor package of the following type, it is possible to improve the yield and production efficiency of the semiconductor package product, and it is also possible to correspond to miniaturization and to make the solder connection portion. The semiconductor element mounting substrate which is manufactured by removing a metal plate from a resin sealing body in which a region in which a semiconductor element is mounted is sealed with a sealing resin, and which is exposed on the back surface side, and a method of manufacturing the same. A semiconductor package of a type in which an external connection terminal made of a plating layer is connected to an external device such as a printed circuit board.
以下，參照附圖來對用於實施本發明的方案進行說明。Hereinafter, embodiments for carrying out the invention will be described with reference to the accompanying drawings.
圖1（a）、（b）、（c）、（d）、（e）是示出本發明的一個實施方式的半導體元件搭載用基板的主要部分結構的一個例子的說明圖，（a）是示出端子部的構造的剖視圖，（b）是示出排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的一個例子的俯視圖，（c）是示出在（a）的半導體元件搭載用基板搭載半導體元件的一個方案的說明圖，（d）是示出在（a）的半導體元件搭載用基板搭載半導體元件的其它方案的說明圖，（e）是示出（a）的半導體元件搭載用基板的一個變形例的說明圖。圖2的（a）、（b）是示出圖1的（a）、（b）的半導體元件搭載用基板中的相鄰的半導體封裝區域的端子部彼此的配置方案的其它例子的圖，（a）是剖視圖，（b）是排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的俯視圖。圖3的（a）、（b）、（c）是示出本發明的其它實施方式的半導體元件搭載用基板的主要部分結構的一個例子的說明圖，（a）是示出端子部的構造的剖視圖，（b）是示出排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的一個例子的俯視圖，（c）是示出在（a）的半導體元件搭載用基板搭載半導體元件的一個方案的說明圖。(a), (b), (c), (d), and (e) are explanatory views showing an example of a configuration of a main part of a semiconductor element mounting substrate according to an embodiment of the present invention, (a) (b) is a cross-sectional view showing a structure of a terminal portion, and (b) is a plan view showing an example of a multi-row type semiconductor element mounting substrate on which a plurality of rows (a) of semiconductor element mounting substrates are arranged, and (c) is a view (d) is an explanatory view showing another aspect in which a semiconductor element is mounted on a semiconductor element mounting substrate of (a), and (d) is an explanatory view of a semiconductor device mounting substrate (a). An explanatory view of a modification of the semiconductor element mounting substrate of (a) is shown. (a) and (b) of FIG. 2 are diagrams showing another example of the arrangement of terminal portions of adjacent semiconductor package regions in the semiconductor element mounting substrate of (a) and (b) of FIG. 1 . (a) is a cross-sectional view, and (b) is a top view of the multi-row type semiconductor element mounting substrate in which a plurality of rows (a) of semiconductor element mounting substrates are arranged. (a), (b), and (c) of FIG. 3 are explanatory views showing an example of a configuration of a main part of a semiconductor element mounting substrate according to another embodiment of the present invention, and (a) shows a structure of a terminal portion. (b) is a plan view showing an example of a multi-row type semiconductor element mounting substrate on which a plurality of rows (a) of semiconductor element mounting substrates are arranged, and (c) is a semiconductor element shown in (a) An illustration of one aspect of mounting a semiconductor element on a mounting substrate.
例如如圖1的（a）所示，本實施方式的半導體元件搭載用基板1具有凹部11和複數個端子部12，並如圖1的（b）所示地排列多列。 凹部11形成於金屬板10的一側的表面10a，並且具有尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的尺寸。 端子部12由鍍層構成，且在從凹部11的底面11a至側面11b以及凹部11的外側的表面（即，金屬板10的一側的表面10a）的既定位置具有段差地形成。 而且，如圖1的（c）、（d）所示，複數個端子部12能夠經由焊料15等連接部件將半導體元件20以倒裝片的方式安裝在端子部12的下層（圖1的（c）的例子）或者端子部12的上層（圖1的（d）的例子）。 此外，對於本實施方式的半導體元件搭載用基板1而言，在圖1的（a）、（b）的例子中，配置為相鄰的半導體封裝區域（未圖示）的端子部彼此連接的狀態，但也可以如圖2（a）、（b）所示，配置為相鄰的半導體封裝區域（未圖示）的端子部彼此分離的狀態。 並且，本實施方式的半導體元件搭載用基板1也可以構成為，如圖3的（a）、（b）所示，具有：由鍍層形成在凹部11的底面11a的中央部的焊墊部12-1；和複數個端子部12-2，由鍍層構成且在焊墊部12-1的周邊且在從凹部11a的底面11a至側面11b以及凹部11的外側的表面的既定位置具有段差地形成，並且如圖3的（c）所示，能夠在焊墊部12-1搭載半導體元件20，並且能夠經由接合線16等連接部件來將端子部12-1的上層和半導體元件20進行引線接合。For example, as shown in FIG. 1( a ), the semiconductor element mounting substrate 1 of the present embodiment has the concave portion 11 and the plurality of terminal portions 12 and is arranged in a plurality of rows as shown in FIG. 1( b ). The recess 11 is formed on the surface 10a of one side of the metal plate 10, and has a size smaller than the size of the bottom surface of the semiconductor package and larger than the size of the bottom surface of the semiconductor element. The terminal portion 12 is formed of a plating layer, and is formed with a stepped position at a predetermined position from the bottom surface 11a of the concave portion 11 to the side surface 11b and the outer surface of the concave portion 11 (that is, the surface 10a on one side of the metal plate 10). Further, as shown in (c) and (d) of FIG. 1, the plurality of terminal portions 12 can be mounted on the lower layer of the terminal portion 12 by flip chip mounting via a connecting member such as solder 15 (Fig. 1 ( An example of c) or an upper layer of the terminal portion 12 (an example of (d) of Fig. 1). Further, in the semiconductor element mounting substrate 1 of the present embodiment, in the examples of (a) and (b) of FIG. 1, the terminal portions of the adjacent semiconductor package regions (not shown) are connected to each other. In the state, as shown in FIGS. 2(a) and 2(b), the terminal portions of the adjacent semiconductor package regions (not shown) may be separated from each other. In addition, as shown in FIGS. 3( a ) and 3 ( b ), the semiconductor element mounting substrate 1 of the present embodiment may have a pad portion 12 formed in a central portion of the bottom surface 11 a of the concave portion 11 by a plating layer. -1; and a plurality of terminal portions 12-2 are formed of a plating layer and are formed at a predetermined position on the periphery of the pad portion 12-1 at a predetermined position from the bottom surface 11a of the concave portion 11a to the side surface 11b and the outer surface of the concave portion 11 As shown in FIG. 3(c), the semiconductor element 20 can be mounted on the pad portion 12-1, and the upper layer of the terminal portion 12-1 and the semiconductor element 20 can be wire-bonded via a connection member such as the bonding wire 16 or the like. .
除此之外，在本實施方式的半導體元件搭載用基板1中，凹部11的深度較佳為形成為0.005~0.11mm。 並且，在本實施方式的半導體元件搭載用基板1中，在一個半導體封裝區域內也可以具有複數個深度不同的凹部11。 並且，在本實施方式的半導體元件搭載用基板1中，也可以如圖1的（e）所示地構成為，凹部11的底面11a具有段差，端子部12具有三個以上的高度不同的表面。In addition, in the semiconductor element mounting substrate 1 of the present embodiment, the depth of the concave portion 11 is preferably formed to be 0.005 to 0.11 mm. Further, in the semiconductor element mounting substrate 1 of the present embodiment, a plurality of concave portions 11 having different depths may be provided in one semiconductor package region. Further, in the semiconductor element mounting substrate 1 of the present embodiment, as shown in FIG. 1(e), the bottom surface 11a of the concave portion 11 may have a step, and the terminal portion 12 may have three or more surfaces having different heights. .
接下來，使用圖4對如圖1的（a）、（b）所示那樣構成的本實施方式的半導體元件搭載用基板1的製造步驟的一個例子進行說明。此外，為便於說明，省略在製造的各步驟中實施的包括藥液清洗、水洗清洗在內的前處理、後處理等的說明。 首先，準備銅或者銅合金的金屬板10作為引線框材料（參照圖4的（a））。 接下來，對金屬板10實施半蝕刻加工來形成凹部11。詳細為，在金屬板10的兩面形成乾膜抗蝕劑等第一抗蝕劑層R1（參照圖4的（b））。接著，使用描繪有如圖1的（a）、（b）所示的與凹部11對應的既定圖案的玻璃遮罩，使金屬板10的一側的第一抗蝕劑層R1曝光，並且使金屬板10的另一側的第一抗蝕劑層R1的整個面曝光，在曝光後使各個第一抗蝕劑層R1顯影。而且，在金屬板10的一側的表面上形成具有尺寸比半導體封裝件的外形小且比半導體元件的底面大的尺寸的開口部的蝕刻用抗蝕劑遮罩31，並且在金屬板10的另一側的表面上形成覆蓋整個面的蝕刻用抗蝕劑遮罩31（參照圖4的（c））。接著，從金屬板10的一側起實施半蝕刻加工來形成凹部11（參照圖4的（d））。接著，將形成於金屬板10的一側的表面上的蝕刻用抗蝕劑遮罩31除去（參照圖4的（e））。 接下來，在金屬板10的一側的從凹部11的底面11a至側面11b以及凹部11的外側的表面的既定位置形成由鍍層構成的複數個端子部12。詳細為，在金屬板10的一側的表面形成乾膜抗蝕劑等第二抗蝕劑層R2（參照圖4的（f））。接著，使用描繪有如圖1的（a）、（b）所示的與端子部12對應的既定圖案的玻璃遮罩來使金屬板10的一側的第二抗蝕劑層R2，在曝光後使第二抗蝕劑層R2顯影。而且，在金屬板10的一側的表面上形成有在從凹部11的底面11a至側面11b以及凹部11的外側的表面的與端子部12對應的區域具有複數個開口部的電鍍用抗蝕劑遮罩32（參照圖4的（g））。接著，例如按照Au、Pd、Ni、Pd的順序在電鍍用抗蝕劑遮罩32的開口部實施電鍍加工，從而形成帶有段差的複數個端子部12（參照圖4的（h））。 此外，鍍層的表面適宜實施粗化處理。在對鍍層的表面進行粗化處理的情況下，例如也可以以鍍鎳來結束鍍層的形成，並以粗化電鍍來形成Ni鍍層。並且，例如也可以在形成平滑的Ni鍍層後，通過蝕刻來對Ni鍍層的表面進行粗化處理。並且，例如也可以以鍍銅來結束鍍層的形成，並通過陽極氧化處理或者蝕刻來對Cu鍍層的表面進行粗化處理。另外，例如也可以在形成粗化鍍層後，依次層疊Pd/Au鍍層。 接著，將形成於金屬板10的兩面上的抗蝕劑遮罩31、32除去（參照圖4的（i））。 由此，完成本實施方式的半導體元件搭載用基板1。Next, an example of a manufacturing procedure of the semiconductor element mounting substrate 1 of the present embodiment configured as shown in (a) and (b) of FIG. 1 will be described with reference to FIG. In addition, for convenience of explanation, the description of the pretreatment, the post treatment, and the like including the chemical liquid washing and the water washing washing performed in each step of the manufacturing is omitted. First, a metal plate 10 of copper or a copper alloy is prepared as a lead frame material (see (a) of FIG. 4). Next, the metal plate 10 is subjected to a half etching process to form the concave portion 11. Specifically, a first resist layer R1 such as a dry film resist is formed on both surfaces of the metal plate 10 (see (b) of FIG. 4 ). Next, using a glass mask in which a predetermined pattern corresponding to the concave portion 11 as shown in FIGS. 1(a) and 1(b) is drawn, the first resist layer R1 on one side of the metal plate 10 is exposed, and the metal is made. The entire surface of the first resist layer R1 on the other side of the board 10 is exposed, and each of the first resist layers R1 is developed after exposure. Further, an etching resist mask 31 having an opening portion having a size smaller than that of the semiconductor package and larger than the bottom surface of the semiconductor element is formed on the surface of one side of the metal plate 10, and is in the metal plate 10 An etching resist mask 31 covering the entire surface is formed on the other surface (see (c) of FIG. 4). Next, a half etching process is performed from one side of the metal plate 10 to form the concave portion 11 (see (d) of FIG. 4). Next, the etching resist mask 31 formed on the surface of one side of the metal plate 10 is removed (refer to (e) of FIG. 4). Next, a plurality of terminal portions 12 composed of a plating layer are formed on a side of the metal plate 10 from the bottom surface 11a of the concave portion 11 to the side surface 11b and the outer surface of the concave portion 11. Specifically, a second resist layer R2 such as a dry film resist is formed on the surface of one side of the metal plate 10 (see (f) of FIG. 4). Next, using the glass mask in which a predetermined pattern corresponding to the terminal portion 12 as shown in FIGS. 1(a) and 1(b) is drawn, the second resist layer R2 on one side of the metal plate 10 is exposed. The second resist layer R2 is developed. Further, on one surface of the metal plate 10, a plating resist having a plurality of openings in a region corresponding to the terminal portion 12 from the bottom surface 11a of the concave portion 11 to the side surface 11b and the outer surface of the concave portion 11 is formed. The mask 32 (refer to (g) of FIG. 4). Then, for example, in the order of Au, Pd, Ni, and Pd, plating is performed on the opening of the resist mask 32 for plating to form a plurality of terminal portions 12 having a step (see (h) of FIG. 4). Further, the surface of the plating layer is suitably subjected to a roughening treatment. When the surface of the plating layer is roughened, for example, the formation of the plating layer may be completed by nickel plating, and the Ni plating layer may be formed by rough plating. Further, for example, after the smooth Ni plating layer is formed, the surface of the Ni plating layer may be roughened by etching. Further, for example, the formation of the plating layer may be completed by copper plating, and the surface of the Cu plating layer may be roughened by anodization or etching. Further, for example, after the rough plating layer is formed, a Pd/Au plating layer may be sequentially laminated. Next, the resist masks 31 and 32 formed on both surfaces of the metal plate 10 are removed (refer to (i) of FIG. 4). Thus, the semiconductor element mounting substrate 1 of the present embodiment is completed.
接下來，使用圖5對使用了本實施方式的半導體元件搭載用基板1的半導體封裝件的製造順序進行說明。 首先，在端子部12的表面的內部端子連接部經由焊料15等以倒裝片的方式連接半導體元件20（參照圖5的（a））。 接下來，裝配未圖示的模制金屬模具，用密封樹脂21對半導體元件搭載側進行密封（參照圖5的（b））。 接下來，除去金屬板10（參照圖5的（c）），並切斷為既定的半導體封裝件的尺寸（參照圖5的（d））。由此，完成使用了本實施方式的半導體元件搭載用基板1的半導體封裝件40（參照圖5的（e））。Next, a manufacturing procedure of the semiconductor package using the semiconductor element mounting substrate 1 of the present embodiment will be described with reference to FIG. First, the internal terminal connecting portion on the surface of the terminal portion 12 is connected to the semiconductor element 20 by flip chip bonding via solder 15 or the like (see (a) of FIG. 5). Next, a mold metal mold (not shown) is attached, and the semiconductor element mounting side is sealed by the sealing resin 21 (see FIG. 5( b )). Next, the metal plate 10 is removed (see (c) of FIG. 5), and cut into the size of a predetermined semiconductor package (see (d) of FIG. 5). Thus, the semiconductor package 40 using the semiconductor element mounting substrate 1 of the present embodiment is completed (see (e) of FIG. 5).
根據本實施方式的半導體元件搭載用基板1，由於構成為具有形成於金屬板10的一側的表面並且尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的凹部11、和在從凹部11的底面11a至側面11b以及凹部11的外側的表面的既定位置帶有段差地形成且由鍍層構成的複數個端子部12，所以通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板10而露出的由鍍層構成的端子部12的背面的外部連接用端子部形成為從半導體封裝40的底面朝向側面具有段差的形狀，並在側面側的段差部分設置空間部。因此，在使用本實施方式的半導體元件搭載用基板1製造了半導體封裝40的情況下，當例如如圖6的（a）~（c）所示地將半導體封裝件40經由焊料90與外部設備（例如，印製電路板80）連接時，因回流而熔融了的焊料潤濕擴展到通過形成端子部12的背面的外部連接用端子部的段差而設置的空間部。其結果，即使是用於製造如下類型的半導體封裝件的半導體元件搭載用基板，也能夠從在半導體封裝40的側面露出的由鍍層構成的外部連接用端子的端緣部的一側目視確認將半導體封裝件40經由焊料90連接至外部基板80後的焊料的連接狀態，上述半導體封裝件是通過從用密封樹脂21密封搭載有半導體元件20的區域而成的樹脂密封體除去金屬板10來製造且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。The semiconductor element mounting substrate 1 according to the present embodiment is configured to have a recess 11 formed on the surface of one side of the metal plate 10 and having a size smaller than the bottom surface of the semiconductor package and larger than the bottom surface of the semiconductor element, and Since the plurality of terminal portions 12 formed of a plating layer are formed at a predetermined position on the outer surface of the concave portion 11 from the bottom surface 11a to the side surface 11b and the outer surface of the concave portion 11, the semiconductor element is sealed by sealing the resin element. In the resin sealing body, the external connection terminal portion of the rear surface of the terminal portion 12 formed of the plating layer, which is exposed by the removal of the metal plate 10, is formed in a shape having a step from the bottom surface of the semiconductor package 40 toward the side surface, and a space is provided in the step portion on the side surface side. unit. Therefore, when the semiconductor package 40 is manufactured using the semiconductor element mounting substrate 1 of the present embodiment, the semiconductor package 40 is soldered to the external device via solder 90, for example, as shown in (a) to (c) of FIG. 6 . When the printed circuit board 80 is connected, for example, the solder melted by the reflow is spread to a space portion provided by forming a step of the external connection terminal portion on the back surface of the terminal portion 12. As a result, even the semiconductor element mounting substrate for manufacturing a semiconductor package of the following type can be visually confirmed from the side of the edge portion of the external connection terminal formed of the plating layer exposed on the side surface of the semiconductor package 40. The semiconductor package 40 is connected to the solder of the external substrate 80 via the solder 90, and the semiconductor package is manufactured by removing the metal plate 10 from the resin sealing body in which the semiconductor element 20 is mounted by sealing the resin 21. Further, a semiconductor package of a type in which an external connection terminal made of a plating layer exposed on the back side is connected to an external device such as a printed circuit board.
並且，根據本實施方式的半導體元件搭載用基板1，帶有段差地形成的由鍍層構成的複數個端子部12從金屬板10的凹部11的底面11a至側面11b以及凹部11的外側的表面以無縫隙的狀態緊貼。因此，與專利文獻1所記載的技術中的槽部不同，在樹脂密封時，沒有密封樹脂進入端子部的槽而使半導體封裝產品的良率變差的擔憂。Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the plurality of terminal portions 12 formed of a plating layer having a stepped surface are formed from the bottom surface 11a of the concave portion 11 of the metal plate 10 to the side surface 11b and the outer surface of the concave portion 11 The seamless state of the gap is close. Therefore, unlike the groove portion in the technique described in Patent Document 1, when the resin is sealed, there is no possibility that the sealing resin enters the groove of the terminal portion and the yield of the semiconductor package product is deteriorated.
並且，根據本實施方式的半導體元件搭載用基板1，與專利文獻2所記載的技術不同，在樹脂密封後，不需要使用刀片的半切和全切的兩次切斷步驟，從而生產效率良好，且能夠減少成本。並且，由於外部連接用端子不向側方突出，所以使半導體封裝產品容易變得小型。Further, the semiconductor element mounting substrate 1 according to the present embodiment differs from the technique described in Patent Document 2 in that it is not necessary to use a half-cutting and a full-cutting step of the blade after the resin sealing, so that the production efficiency is good. And can reduce costs. Further, since the external connection terminals do not protrude to the side, the semiconductor package product is easily made small.
並且，在本實施方式的半導體元件搭載用基板1中，如圖1的（c）所示，若在具有段差的由鍍層構成的各個端子部12的下層的表面以倒裝片的方式安裝半導體元件20，則能夠將半導體封裝件的厚度減薄相當於鍍層的段差的量。Further, in the semiconductor element mounting substrate 1 of the present embodiment, as shown in FIG. 1(c), the semiconductor is flip-chip mounted on the surface of the lower layer of each of the terminal portions 12 each having a plating layer having a step. The element 20 is capable of reducing the thickness of the semiconductor package by an amount corresponding to the step of the plating layer.
並且，在本實施方式的半導體元件搭載用基板1中，如圖1的（d）所示，若在具有段差的由鍍層構成的各個端子部12-2的上層的表面以倒裝片的方式安裝半導體元件20，則在用密封樹脂進行了密封後，能夠較厚地形成蔓延至半導體元件20的背面側的密封樹脂的層，也能夠確保密封樹脂與鍍層的緊貼面積較大，從而能夠確保密封樹脂與端子部12的連接強度較高。並且，能夠充分確保焊墊部12-1的表面與半導體元件20之間的空間，提高絕緣性，難以拾起雜訊。In the semiconductor element mounting substrate 1 of the present embodiment, as shown in FIG. 1(d), the surface of the upper layer of each of the terminal portions 12-2 made of a plating layer having a step is flip-chip mounted. When the semiconductor element 20 is mounted, the sealing resin can be formed in a thick layer to form a layer of the sealing resin that spreads to the back side of the semiconductor element 20, and the contact area between the sealing resin and the plating layer can be ensured to ensure a large area. The connection strength between the sealing resin and the terminal portion 12 is high. Further, the space between the surface of the pad portion 12-1 and the semiconductor element 20 can be sufficiently ensured, and the insulation property can be improved, and it is difficult to pick up noise.
並且，在本實施方式的半導體元件搭載用基板1中，若使凹部11的深度形成為0.005mm~0.025mm左右，則由於形成於凹部11的成為端子部12等的鍍層不會從半導體封裝件40的背面較大地突出，因而在半導體封裝件40的製造中，當從密封樹脂體剝下並除去金屬板10時，能夠防止形成於凹部11的鍍層向金屬板的勾掛，容易剝下金屬板10。In the semiconductor element mounting substrate 1 of the present embodiment, when the depth of the concave portion 11 is formed to be about 0.005 mm to 0.025 mm, the plating layer to be the terminal portion 12 or the like formed in the concave portion 11 does not protrude from the semiconductor package. The back surface of 40 is largely protruded, so that in the manufacture of the semiconductor package 40, when the metal plate 10 is peeled off and removed from the sealing resin body, the plating formed on the concave portion 11 can be prevented from being caught on the metal plate, and the metal can be easily peeled off. Board 10.
並且，在本實施方式的半導體元件搭載用基板1中，若使凹部11的深度形成為0.03mm~0.06mm左右，則能夠將搭載半導體元件後的半導體元件20的背面側與焊墊部等的表面之間的空間確保為可以採取雜訊對策（提高絕緣性，難以拾起雜訊）、焊料洩漏對策（阻止在將半導體元件20焊接連接至形成於凹部11的底面的成為端子部12等的鍍層時的、焊料向鍍層表面與半導體元件20的耦合點以外的鍍層整個區域的潤濕擴展，防止阻礙鍍層表面與密封樹脂的緊貼性，並且阻止在將半導體封裝件焊接連接至外部設備時的、焊料向鄰接的端子側的潤濕擴展，防止電氣短路）的程度。 並且，根據本實施方式的圖1的（e）的半導體元件搭載用基板，由於端子部12具有三個以上的高度不同的表面，所以當將半導體封裝件焊接連接至外部設備後，經由具有複數個段差的表面將焊料引導至最寬廣的空間區域，從而容易停留在以最寬廣的空間區域介入焊料的狀態。其結果，容易採取焊料洩漏對策（阻止在將半導體元件20焊接連接至形成於凹部11的底面的成為端子部12等的鍍層時的、焊料向鍍層表面與半導體元件20的耦合點以外的鍍層整個區域的潤濕擴展，防止阻礙鍍層表面與密封樹脂的緊貼性，並且阻止在將半導體封裝件焊接連接至外部設備時的、焊料向鄰接的端子側的潤濕擴展，防止電氣短路）。In the semiconductor element mounting substrate 1 of the present embodiment, when the depth of the recessed portion 11 is set to about 0.03 mm to 0.06 mm, the back surface side of the semiconductor element 20 on which the semiconductor element is mounted, the pad portion, and the like can be used. The space between the surfaces is ensured to be able to take noise countermeasures (improving insulation, and it is difficult to pick up noise), and solder leakage countermeasures (to prevent the semiconductor element 20 from being soldered and connected to the bottom surface of the concave portion 11 to be the terminal portion 12 or the like) The wetting spread of the solder to the entire region of the plating layer other than the coupling point of the plating surface and the semiconductor element 20 at the time of plating prevents the adhesion of the plating surface to the sealing resin from being hindered, and prevents the semiconductor package from being soldered to the external device. The extent to which the solder spreads to the adjacent terminal side to prevent electrical shorting. Further, according to the semiconductor element mounting substrate of FIG. 1(e) of the present embodiment, since the terminal portion 12 has three or more surfaces having different heights, the semiconductor package is soldered to an external device, and has a plurality of The stepped surface guides the solder to the widest spatial area, thereby easily staying in a state where the solder is interposed in the widest spatial area. As a result, it is easy to take measures against the solder leakage (preventing the entire plating layer from the point where the solder is bonded to the surface of the plating layer and the semiconductor element 20 when the semiconductor element 20 is soldered to the plating layer which is formed on the bottom surface of the concave portion 11 to be the terminal portion 12 or the like. The wetting spread of the region prevents the adhesion of the plating surface to the sealing resin from being impeded, and prevents the wetting spread of the solder to the adjacent terminal side when the semiconductor package is soldered to the external device, preventing electrical shorting).
並且，在本實施方式的半導體元件搭載用基板1中，若使凹部11的深度形成為0.08mm~0.11mm左右，則在具有段差的端子部12的背面的外部連接用端子處設置於半導體封裝件40的側面側的段差部分的、能夠介入焊料的空間部的區域會在半導體封裝40的厚度方向上增加。其結果，變得更加容易觀察製造半導體封裝件後的外部連接用端子與外部設備的焊料連接狀態。 並且，若使凹部11的深度形成為0.08mm~0.11mm左右，則在搭載半導體元件20且用密封樹脂進行密封後，在通過藥液的溶化來進行作為基材的金屬板10的除去的情況下，能夠以加深凹部11的深度的量使溶化的金屬板10的體積更少。其結果，能夠抑制在藥液中溶化的金屬板10成分的濃度的上升，並且能夠確保穩定的溶化狀態，能夠減少藥液調整（金屬板成分的濃度變高後的溶液的汲取以及新溶液的補充）。In the semiconductor element mounting substrate 1 of the present embodiment, when the depth of the concave portion 11 is formed to be about 0.08 mm to 0.11 mm, the external connection terminal on the back surface of the terminal portion 12 having the step is provided in the semiconductor package. A region of the step portion on the side surface side of the member 40 that can intervene in the space portion of the solder increases in the thickness direction of the semiconductor package 40. As a result, it becomes easier to observe the solder connection state of the external connection terminal and the external device after the semiconductor package is manufactured. In addition, when the depth of the concave portion 11 is set to about 0.08 mm to 0.11 mm, the semiconductor element 20 is mounted and sealed with a sealing resin, and the metal plate 10 as a base material is removed by melting of the chemical solution. Next, the volume of the molten metal plate 10 can be made smaller by increasing the depth of the concave portion 11. As a result, it is possible to suppress an increase in the concentration of the metal plate 10 component melted in the chemical solution, and it is possible to ensure a stable molten state, and it is possible to reduce the adjustment of the chemical solution (the extraction of the solution after the concentration of the metal plate component is increased and the new solution) supplement).
因此，根據本實施方式，在用於製造如下類型的半導體封裝件的半導體元件搭載用基板中，可得到半導體封裝產品的良率、生產效率變高，也能夠對應於小型化，而且使焊料連接部分能夠目視的半導體元件搭載用基板以及其製造方法，其中，上述半導體封裝件是通過從用密封樹脂密封搭載有半導體元件的區域而成的樹脂密封體除去金屬板來製造的且在背面側露出的由鍍層構成的外部連接用端子與印製電路板等外部設備連接的類型的半導體封裝件。 實施例Therefore, according to the present embodiment, in the semiconductor element mounting substrate for manufacturing a semiconductor package of the following type, the yield and production efficiency of the semiconductor package product can be improved, and the solder can be connected in accordance with the miniaturization. A semiconductor element mounting substrate which is manufactured by removing a metal plate from a resin sealing body in which a region in which a semiconductor element is mounted by sealing resin is sealed, and which is exposed on the back side, and a method of manufacturing the same. A semiconductor package of a type in which an external connection terminal made of a plating layer is connected to an external device such as a printed circuit board. Example
接下來，對本發明的引線框和其製造方法的實施例進行說明。 實施例1 首先，作為金屬板10，準備厚度0.20mm的銅系材料（參照圖4的（a）），並在兩面層疊有乾膜抗蝕劑作為第一抗蝕劑層R1（參照圖4的（b））。Next, an embodiment of the lead frame of the present invention and a method of manufacturing the same will be described. Example 1 First, a copper-based material having a thickness of 0.20 mm was prepared as the metal plate 10 (see FIG. 4(a)), and a dry film resist was laminated on both surfaces as the first resist layer R1 (refer to FIG. 4). (b)).
接下來，使用描繪有如圖1的（a）、（b）所示的與凹部11對應的既定圖案的玻璃遮罩，使金屬板10的一側的第一抗蝕劑層R1曝光，並且使金屬板10的另一側的第一抗蝕劑層R1的整個面曝光，在曝光後使各個第一抗蝕劑層R1顯影，在金屬板10的一側的表面上形成具有尺寸比半導體封裝件的底面尺寸小且比半導體元件的底面尺寸大的開口部的蝕刻用抗蝕劑遮罩31，並且在金屬板10的另一側的表面上形成覆蓋整個面的蝕刻用抗蝕劑遮罩31（參照圖4的（c））。 接下來，從金屬板10的一側實施深度0.015mm的半蝕刻加工，在金屬板的實施有半蝕刻加工的深度處形成凹部11（參照圖4的（d））。此外，蝕刻液使用氯化鐵液。 接下來，將形成於金屬板10的一側的表面上的蝕刻用抗蝕劑遮罩31剝離（參照圖4的（e））。Next, the first resist layer R1 on one side of the metal plate 10 is exposed by using a glass mask in which a predetermined pattern corresponding to the concave portion 11 as shown in (a) and (b) of FIG. 1 is drawn, and The entire surface of the first resist layer R1 on the other side of the metal plate 10 is exposed, and each of the first resist layers R1 is developed after exposure, and a semiconductor package having a size ratio is formed on one surface of the metal plate 10. An etching resist mask 31 having a small bottom surface and an opening larger than the bottom surface of the semiconductor element, and an etching resist mask covering the entire surface on the surface of the other side of the metal plate 10 31 (refer to (c) of FIG. 4). Next, a half etching process having a depth of 0.015 mm is performed from one side of the metal plate 10, and a concave portion 11 is formed at a depth at which the metal plate is half-etched (see (d) of FIG. 4). Further, the etching solution uses a ferric chloride solution. Next, the etching resist mask 31 formed on the surface of one side of the metal plate 10 is peeled off (refer to (e) of FIG. 4).
接下來，在金屬板10的一側的表面層疊乾膜抗蝕劑作為第二抗蝕劑層R2（參照圖4的（f））。 接下來，使用描繪有如圖1的（a）、（b）所示的與端子部12對應的既定圖案的玻璃遮罩，使金屬板10的一側的第二抗蝕劑層R2曝光，在曝光後使第二抗蝕劑層R2顯影，在金屬板10的一側的表面上形成有在從凹部11的底面11a至側面11b以及凹部11的外側的表面的與端子部12對應的區域具有複數個開口部的電鍍用抗蝕劑遮罩32（參照圖4的（g））。 接下來，按照Au為0.01μm、Pd為0.03μm、Ni為30.0μm、Pd為0.03μm的厚度依次對電鍍用抗蝕劑遮罩32的開口部實施電鍍加工，從而形成有帶有段差的複數個端子部12（參照圖4的（h））。 接下來，將形成於金屬板10的兩面上的抗蝕劑遮罩31、32剝離（參照圖4的（i）），從而得到了實施例1的半導體元件搭載用基板1。Next, a dry film resist is laminated on the surface of one side of the metal plate 10 as the second resist layer R2 (refer to (f) of FIG. 4). Next, the second resist layer R2 on one side of the metal plate 10 is exposed by using a glass mask in which a predetermined pattern corresponding to the terminal portion 12 as shown in FIGS. 1(a) and 1(b) is drawn. After the exposure, the second resist layer R2 is developed, and a surface corresponding to the terminal portion 12 having a surface from the bottom surface 11a of the concave portion 11 to the side surface 11b and the outer side of the concave portion 11 is formed on the surface of one side of the metal plate 10. A plurality of plating resist masks 32 for plating (see (g) of FIG. 4). Next, the openings of the resist mask 32 for electroplating are sequentially plated in a thickness of 0.01 μm for Au, 0.03 μm for Pd, 30.0 μm for Ni, and 0.03 μm for Pd, thereby forming a plurality of steps with a step. The terminal portion 12 (see (h) of Fig. 4). Then, the resist masks 31 and 32 formed on both surfaces of the metal plate 10 are peeled off (see (i) of FIG. 4), and the semiconductor element mounting substrate 1 of the first embodiment is obtained.
接下來，在實施例1的半導體元件搭載用基板1中的端子部12的表面的內部端子連接部經由焊料15等以倒裝片的方式連接半導體元件20（參照圖5的（a）），裝配未圖示的模制金屬模具，用密封樹脂21將半導體元件搭載側進行密封（參照圖5的（b））。 接下來，除去金屬板10（參照圖5的（c））。Then, the internal terminal connecting portion on the surface of the terminal portion 12 in the semiconductor element mounting substrate 1 of the first embodiment is connected to the semiconductor element 20 by flip chip bonding via solder 15 or the like (see (a) of FIG. 5). A molded metal mold (not shown) is attached, and the semiconductor element mounting side is sealed with a sealing resin 21 (see FIG. 5( b )). Next, the metal plate 10 is removed (refer to (c) of FIG. 5).
此時，除去金屬板10後的密封樹脂體中的與半導體元件搭載側相反的一側的表面（背面）形成為凸形狀，完成為構成成為外部連接用端子的端子部12的鍍層從形成為凸形狀的密封樹脂體的表面露出的狀態。 接下來，切斷為既定的半導體封裝件的尺寸（參照圖5的（d））。由此，得到使用了實施例1的半導體元件搭載用基板1的半導體封裝件40（參照圖5的（e））。 接下來，將使用了實施例1的半導體元件搭載用基板1的半導體封裝件40的外部連接用端子焊接連接至作為外部設備的印製電路板80的端子，將其裝配於印製電路板80。此時，因回流而熔融了的焊料90潤濕擴展到端子部12的背面的通過形成外部連接用端子部的段差而設置的空間部，能夠目視確認在半導體封裝件40的側面露出的外部連接用端子12的焊料連接部分，成為能夠目視檢查半導體封裝件40與作為外部設備的印製電路板80的焊料連接狀態的合格、不合格的狀態（參照圖6的（a）~（c））。At this time, the surface (back surface) on the side opposite to the mounting side of the semiconductor element in the sealing resin body after the metal plate 10 is removed is formed into a convex shape, and the plating layer which is the terminal portion 12 constituting the external connection terminal is formed into The state in which the surface of the convex sealing resin body is exposed. Next, it is cut into the size of a predetermined semiconductor package (refer to (d) of FIG. 5). Thus, the semiconductor package 40 using the semiconductor element mounting substrate 1 of the first embodiment is obtained (see (e) of FIG. 5). Next, the external connection terminal of the semiconductor package 40 using the semiconductor element mounting substrate 1 of the first embodiment is solder-bonded to the terminal of the printed circuit board 80 as an external device, and is mounted on the printed circuit board 80. . At this time, the solder 90 which has been melted by the reflow is wetted and spread to the space portion provided on the back surface of the terminal portion 12 by the step of forming the external connection terminal portion, and the external connection exposed on the side surface of the semiconductor package 40 can be visually confirmed. By the solder connection portion of the terminal 12, it is possible to visually check the solder connection state of the semiconductor package 40 and the printed circuit board 80 as an external device. (See (a) to (c) of FIG. 6) .
比較例1 在比較例1中，省略實施例1中的通過半蝕刻加工來形成凹部11的形成步驟，除此以外以與實施例1大致相同的條件以及順序製造半導體元件搭載用基板。 更詳細為，在金屬板的兩面層疊壓乾膜抗蝕劑作為第一抗蝕劑層，並使用描繪有如圖1的（b）所示的與端子部12對應的既定圖案的玻璃遮罩，使金屬板的一側的第一抗蝕劑層曝光，並且使金屬板的另一側的第一抗蝕劑層的整個面曝光，在曝光後使各個第一抗蝕劑層顯影，在金屬板的一側的表面上形成有在如圖1的（b）所示的與端子部12對應的區域具有複數個開口部的電鍍用抗蝕劑遮罩，並且在金屬板的另一側的表面上形成有覆蓋整個面的電鍍用抗蝕劑遮罩。 接下來，按照Au為0.01μm、Pd為0.03μm、Ni為30.0μm、Pd為0.03μm的厚度依次對電鍍用抗蝕劑遮罩的開口部實施電鍍加工，從而形成複數個端子部。 接下來，將形成於金屬板的兩面上的抗蝕劑遮罩剝離，從而得到比較例1的半導體元件搭載用基板。(Comparative Example 1) The semiconductor element mounting substrate was manufactured in the same manner and in the same manner as in the first embodiment except that the step of forming the concave portion 11 by the half etching process in the first embodiment was omitted. More specifically, a dry film resist is laminated on both surfaces of the metal plate as a first resist layer, and a glass mask in which a predetermined pattern corresponding to the terminal portion 12 as shown in FIG. 1( b ) is drawn is used. Exposing the first resist layer on one side of the metal plate and exposing the entire surface of the first resist layer on the other side of the metal plate, and developing each of the first resist layers after exposure, in the metal A plating resist for plating having a plurality of openings in a region corresponding to the terminal portion 12 as shown in FIG. 1(b) is formed on the surface of one side of the plate, and is on the other side of the metal plate. A resist mask for plating covering the entire surface is formed on the surface. Next, an opening portion of the resist mask for plating is sequentially plated in a thickness of 0.01 μm of Au, 0.03 μm of Pd, 30.0 μm of Ni, and Pd of 0.03 μm to form a plurality of terminal portions. Next, the resist mask formed on both surfaces of the metal plate was peeled off, and the semiconductor element mounting substrate of Comparative Example 1 was obtained.
接下來，與實施例1相同，在比較例1的半導體元件搭載用基板中的端子部的表面的內部端子連接部經由焊料等以倒裝片的方式連接半導體元件，裝配未圖示的模制金屬模具，用密封樹脂將半導體元件搭載側進行密封，之後，除去金屬板。 此時，除去金屬板後的密封樹脂體中的與半導體元件搭載側相反的一側的表面形成為平坦，完成為構成成為外部連接用端子的端子部的鍍層從形成為平坦的密封樹脂體的表面露出的狀態。 接下來，切斷為既定的半導體封裝件的尺寸。由此，得到使用了比較例1的半導體元件搭載用基板的半導體封裝件。 接下來，將使用了比較例1的半導體元件搭載用基板的半導體封裝件的外部連接用端子焊接連接至作為外部設備的印製電路板的端子，將其裝配於印製電路板。Then, in the semiconductor element mounting substrate of the comparative example 1, the internal terminal connection portion on the surface of the terminal portion is connected to the semiconductor element by flip chip bonding, and the molding is performed, not shown, in the same manner as in the first embodiment. The metal mold is sealed with a sealing resin on the side on which the semiconductor element is mounted, and then the metal plate is removed. At this time, the surface of the sealing resin body after the removal of the metal plate is formed to be flat on the side opposite to the side on which the semiconductor element is mounted, and the plating layer that is the terminal portion that constitutes the external connection terminal is formed into a flat sealing resin body. The state where the surface is exposed. Next, it is cut to the size of a predetermined semiconductor package. Thus, a semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 was obtained. Next, the external connection terminal of the semiconductor package using the semiconductor element mounting substrate of Comparative Example 1 is solder-bonded to a terminal of a printed circuit board as an external device, and is mounted on a printed circuit board.
連接外部設備後的焊料連接狀態的外觀觀察的容易度的比較 對經由焊料將使用實施例1以及比較例1的各個半導體元件搭載用基板而製造出的各個半導體封裝件連接至作為外部設備的印製電路板的端子後的焊料連接狀態的外觀觀察的容易度進行了比較。 在將使用比較例1的半導體元件搭載用基板而製造出的半導體封裝件連接至作為外部設備的印製電路板的端子的情況下，沒有來自半導體封裝件的側面的焊料的露出，難以目視確認外部連接用端子部與作為外部設備的印製電路板的端子的焊料連接狀態。 與此相對，在將使用實施例1的半導體元件搭載用基板1而製造出的半導體封裝件40連接至作為外部設備的印製電路板80的端子的情況下，能夠從在半導體封裝件40的側面露出的由鍍層構成的外部連接用端子的端緣部的一側目視確認：在半導體封裝件40的側面且在所有端子部12的外部設備側的表面與作為外部設備的印製電路板80的端子之間填充有焊料的情況。Comparison of the ease of observation of the appearance of the solder connection state after the connection of the external device to each of the semiconductor packages manufactured using the respective semiconductor element mounting substrates of the first embodiment and the comparative example 1 to the external device The ease of observation of the appearance of the solder connection state behind the terminals of the circuit board was compared. When the semiconductor package manufactured using the semiconductor element mounting substrate of the first embodiment is connected to the terminal of the printed circuit board as an external device, the solder from the side surface of the semiconductor package is not exposed, and it is difficult to visually confirm The solder connection state of the external connection terminal portion and the terminal of the printed circuit board as an external device. On the other hand, when the semiconductor package 40 manufactured by using the semiconductor element mounting substrate 1 of the first embodiment is connected to the terminal of the printed circuit board 80 as an external device, it can be obtained from the semiconductor package 40. The side of the edge portion of the external connection terminal formed of the plating layer exposed on the side surface was visually confirmed on the side surface of the semiconductor package 40 and on the surface of the external device side of all the terminal portions 12 and the printed circuit board 80 as an external device. The case where the terminals are filled with solder.
以上，對本發明的較佳的實施方式以及實施例進行了詳細說明，但本發明並不限定於上述的實施方式以及實施例，在不脫離本發明的範圍的情況下，能夠對上述的實施方式以及實施例施加各種變形以及置換。 工業上的可利用性The preferred embodiments and examples of the present invention have been described in detail above, but the present invention is not limited to the embodiments and examples described above, and the embodiments described above can be applied without departing from the scope of the present invention. And the embodiments apply various modifications and permutations. Industrial availability
本發明的半導體元件搭載用基板以及其製造方法在要求用於「端子部由鍍層形成且在背面側露出的端子部背面的外部連接用端子與印製電路板等連接的類型」的半導體封裝件的領域中有用。The semiconductor element mounting substrate of the present invention and the method of manufacturing the same are required for a semiconductor package in which the terminal for external connection of the terminal portion formed on the back side of the terminal portion is connected to a printed circuit board or the like. Useful in the field.
1‧‧‧半導體元件搭載用基板1‧‧‧Semiconductor component mounting substrate
10‧‧‧金屬板10‧‧‧Metal plates
10a‧‧‧金屬板的一側的表面10a‧‧‧ Surface of one side of the metal plate
11‧‧‧凹部11‧‧‧ recess
11a‧‧‧底面11a‧‧‧ bottom
11b‧‧‧側面11b‧‧‧ side
12‧‧‧端子部12‧‧‧ Terminals
15‧‧‧焊料15‧‧‧ solder
16‧‧‧接合線16‧‧‧bonding line
20、60‧‧‧半導體元件20, 60‧‧‧ semiconductor components
21、70‧‧‧密封樹脂21, 70‧‧‧ sealing resin
31‧‧‧蝕刻用抗蝕劑遮罩31‧‧‧Resist mask for etching
32‧‧‧電鍍用抗蝕劑遮罩32‧‧‧Resist mask for electroplating
40‧‧‧半導體封裝件40‧‧‧Semiconductor package
51‧‧‧端子部（外部連接用端子）51‧‧‧Terminal part (terminal for external connection)
51a‧‧‧空間部51a‧‧‧Space Department
51b‧‧‧槽51b‧‧‧ slot
52‧‧‧焊墊部52‧‧‧ solder pad
61‧‧‧接合線61‧‧‧bonding line
80‧‧‧外部設備（印製電路板）80‧‧‧External equipment (printed circuit board)
81‧‧‧端子81‧‧‧ terminals
90‧‧‧焊料90‧‧‧ solder
R1‧‧‧第一抗蝕劑層R1‧‧‧First resist layer
R2‧‧‧第二抗蝕劑層R2‧‧‧second resist layer
圖1的（a）、（b）、（c）、（d）、（e）是示出本發明的一個實施方式的半導體元件搭載用基板的主要部分結構的一個例子的說明圖，（a）是示出端子部的構造的剖視圖，（b）是示出排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的一個例子的俯視圖，（c）是示出在（a）的半導體元件搭載用基板搭載半導體元件的一個方案的說明圖，（d）是示出在（a）的半導體元件搭載用基板搭載半導體元件的其它方案的說明圖，（e）是示出（a）的半導體元件搭載用基板的一個變形例的說明圖。 圖2的（a）、（b）是示出圖1的（a）、（b）的半導體元件搭載用基板中的相鄰的半導體封裝區域的端子部彼此的配置方案的其它例子的圖，（a）是剖視圖，（b）是排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的俯視圖。 圖3（a）、（b）、（c）是示出本發明的其它實施方式的半導體元件搭載用基板的主要部分結構的一個例子的說明圖，（a）是示出端子部的構造的剖視圖，（b）是示出排列有多列（a）的半導體元件搭載用基板的多列型半導體元件搭載用基板的一個例子的俯視圖，（c）是示出在（a）的半導體元件搭載用基板搭載半導體元件的一個方案的說明圖。 圖4的（a）、（b）、（c）、（d）、（e）、（f）、（g）、（h）、（i）是示出圖1的（a）的半導體元件搭載用基板的製造順序的一個例子的說明圖。 圖5的（a）、（b）、（c）、（d）、（e）是示出使用了按照圖4的製造順序製造出的半導體元件搭載用基板的半導體封裝件的製造順序的一個例子的說明圖。 圖6的（a）、（b）、（c）是階段性示出將使用本發明的實施方式的半導體元件搭載用基板而製造出的半導體封裝件經由焊料連接至外部基板時的狀態的說明圖，（a）是示出連接前的狀態的圖，（b）是示出與焊料連接的狀態的圖，（c）是示出從（b）的狀態起進一步壓焊半導體封裝件、並利用加熱將回流了的焊料浸潤擴展的狀態的圖。 圖7的（a）、（b）、（c）、（d）是示出用於使半導體封裝件能夠目視的焊料連接部分的現有技術的一個例子的說明圖，（a）是從用於半導體封裝件的引線框的與外部設備連接的一側觀察的圖，（b）是使用（a）的引線框組裝成的半導體封裝件的（a）的A-A剖視圖，（c）是示出將（b）的半導體封裝件的外部連接用端子焊接連接於外部設備的狀態的圖，（d）是示出（a）的引線框的成為外部連接用端子的端子部的B-B剖視圖。(a), (b), (c), (d), and (e) of FIG. 1 are explanatory views showing an example of a configuration of a main part of a semiconductor element mounting substrate according to an embodiment of the present invention, (a) (b) is a cross-sectional view showing a structure of a terminal portion, and (b) is a plan view showing an example of a multi-row type semiconductor element mounting substrate on which a plurality of rows (a) of semiconductor element mounting substrates are arranged, and (c) is a view (a) is an explanatory view showing another aspect in which a semiconductor element is mounted on a semiconductor element mounting substrate of (a), and (d) is an explanatory view showing another aspect in which a semiconductor element is mounted on the semiconductor element mounting substrate of (a), (e) It is explanatory drawing which shows the modification of the semiconductor element mounting substrate of (a). (a) and (b) of FIG. 2 are diagrams showing another example of the arrangement of terminal portions of adjacent semiconductor package regions in the semiconductor element mounting substrate of (a) and (b) of FIG. 1 . (a) is a cross-sectional view, and (b) is a top view of the multi-row type semiconductor element mounting substrate in which a plurality of rows (a) of semiconductor element mounting substrates are arranged. (a), (b), and (c) are explanatory views showing an example of a configuration of a main part of a semiconductor element mounting substrate according to another embodiment of the present invention, and (a) is a view showing a structure of a terminal portion. (b) is a plan view showing an example of a multi-row type semiconductor element mounting substrate in which a plurality of rows (a) of semiconductor element mounting substrates are arranged, and (c) is a semiconductor element mounted in (a). An explanatory view of one aspect of mounting a semiconductor element on a substrate. 4(a), (b), (c), (d), (e), (f), (g), (h), (i) are semiconductor elements showing (a) of FIG. An explanatory diagram of an example of a manufacturing procedure of the mounting substrate. (a), (b), (c), (d), and (e) of FIG. 5 are ones showing a manufacturing procedure of a semiconductor package using the semiconductor element mounting substrate manufactured in the manufacturing sequence of FIG. An illustration of the example. (a), (b), and (c) of FIG. 6 are views showing a state in which a semiconductor package manufactured by using the semiconductor element mounting substrate of the embodiment of the present invention is connected to an external substrate via solder. (a) is a view showing a state before connection, (b) is a view showing a state of being connected to solder, and (c) is a view showing that the semiconductor package is further pressure-bonded from the state of (b), A diagram of the state in which the reflowed solder is wetted by heating. (a), (b), (c), and (d) of FIG. 7 are explanatory views showing an example of a prior art of a solder joint portion for allowing a semiconductor package to be visually observed, and (a) is used for (b) is a cross-sectional view of (a) of the semiconductor package assembled using the lead frame of (a), and (c) is a view showing a side of the lead frame of the semiconductor package connected to the external device, (b) (b) is a BB cross-sectional view showing a terminal portion of the lead frame of the (a) which is an external connection terminal, in a state in which the external connection terminal of the semiconductor package (b) is soldered to the external device.
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| JP7184429B2 (en) * | 2019-04-02 | 2022-12-06 | 大口マテリアル株式会社 | Method for manufacturing substrate for mounting semiconductor device |
| JP7260372B2 (en) * | 2019-04-02 | 2023-04-18 | 大口マテリアル株式会社 | Method for manufacturing substrate for mounting semiconductor device |
| CN111924795B (en) * | 2020-07-17 | 2021-06-22 | 诺思(天津)微系统有限责任公司 | Device packaging module, packaging method and electronic device with module |
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| CN109285823B (en) | 2022-08-12 |
| TWI765068B (en) | 2022-05-21 |
| JP6863846B2 (en) | 2021-04-21 |
| CN109285823A (en) | 2019-01-29 |
| JP2019021815A (en) | 2019-02-07 |
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