JP6679125B2 - Lead frame, semiconductor device using the same, and manufacturing method thereof - Google Patents

Description

  The present invention relates to a lead frame, a semiconductor device using the same, and a manufacturing method thereof.

  2. Description of the Related Art In recent years, electronic devices have been rapidly reduced in size and weight, and semiconductor devices used in these electronic devices are also required to be reduced in size, weight, and functionality. As a relatively small and thin semiconductor device among general semiconductor devices, there is a semiconductor device using a lead frame formed by processing a metal plate such as QFN (Quad Flat No-Lead).

  Further, when connecting the semiconductor element and the lead portion, a wire bonding method using a gold wire is generally adopted. However, due to the soaring Au price in recent years, the adoption of a flip chip method in which a semiconductor element and a lead portion are directly connected without using a gold wire is increasing.

  For example, in Patent Document 1, in order to improve the bonding property of the surface of a metal lead frame, a lead frame in which a surface treatment such as noble metal plating such as Au or Ag is prepared in advance in a region including a semiconductor element mounting portion is prepared. It is bonded to the electrode portion of the semiconductor element by thermocompression bonding or ultrasonic thermocompression bonding via a metal bump or the like. After that, the semiconductor element and the entire lead frame are resin-sealed and cut into a predetermined size to complete the semiconductor device.

  Further, Patent Document 2 describes a power semiconductor device. Since a relatively large current is passed through the power semiconductor device, a plurality of gold wires are connected to one lead portion to reduce the resistance between the electrode of the semiconductor element and the lead portion. There is also a description in which a plurality of solder bumps are formed on the electrode portion of the semiconductor element with respect to one lead portion and flip-chip mounting is performed.

  Further, Patent Document 3 describes a power semiconductor device that performs flip-chip mounting using a plurality of Au bumps on the same plane for one or a plurality of terminals.

  Under the circumstances described above, the semiconductor device is a semiconductor device using a lead frame formed by processing a metal plate such as QFN in response to a demand for cost reduction as well as size reduction, and a method for connecting an electrode portion and a lead portion of a semiconductor element. However, the number of devices using the flip chip method is increasing. In addition, there is a demand for further miniaturization and increase in the number of pins. In the case of flip-chip mounting, the electrode portion of the semiconductor element is arranged around the outer shape of the semiconductor element. Accordingly, the internal terminal portion at the tip of the lead portion is arranged so as to match with this. As shown in Patent Document 1, the tip shape of the conventional lead portion has a shape sufficiently larger than the bump including the bump forming portion.

JP, 10-294411, A JP, 2003-188203, A JP 2000-223634 A

  However, due to demands for miniaturization and increase in the number of pins, the pitch between the electrodes has become narrower as the size of the semiconductor element itself becomes smaller and as the number of pins increases. Also, the tip shape of the lead portion is such that the tip of the lead portion does not come into contact with the adjacent lead portion, and the tip of the internal terminal portion of the lead portion does not come into contact with the semiconductor element itself. It has been demanded that the sizes of the tip shapes of the parts be almost the same. If the flip-chip mounting is performed in such a state, the position of the electrode and the position of the lead portion may be displaced. Further, when the bumps are solder bumps, the solder may spread on the side surface of the lead during reflow and may contact the adjacent lead. In the case of the power semiconductor device described in Patent Document 2 or Patent Document 3, since a plurality of flip-chip mounting is performed on one or a plurality of terminals on the same plane, the interval between bumps becomes narrow, There is an increased possibility that some of them will contact the adjacent bumps. In addition, although no contact occurs, the bumps swell or expand and the gap between the bumps becomes narrower, so the resin cannot be sufficiently filled between the bumps in the subsequent resin encapsulation process, which is a problem of resin unfilling. Is more likely to occur. In particular, in order to reduce the cost, in a power semiconductor device using solder bumps for flip chip mounting, it is important to control the wetting and spreading of the solder bumps during reflow.

  Therefore, the present invention has been invented in view of the above situation, and is suitable for flip-chip mounting, can reduce the chip size, increase the number of pins, and reduce the cost, and reflow solder bumps. An object of the present invention is to provide a lead frame capable of controlling wet spread and a semiconductor device using the same, and a manufacturing method thereof.

In order to achieve the above object, a lead frame according to an aspect of the present invention is a lead frame for mounting a semiconductor element made of a metal material,
A lead portion having an internal terminal portion capable of flip-chip connecting a semiconductor element to a predetermined region on the front surface side,
A concave portion formed on the surface of the internal terminal portion of the lead portion, the concave portion having a bottom portion of a substantially flat surface and a curved side surface convex downward.
Possess a plating layer formed on the inner side of the recess, and
A plurality of the lead portions are provided, and the plurality of lead portions include at least one first lead portion having the recess and the plating layer formed on the front surface side, and the recess on the front surface side. And at least one second lead portion having a plurality of the plating layers formed thereon .

A semiconductor device according to another aspect is a lead portion made of a metal material and having an internal terminal portion on the surface side, in which a plating layer is formed inside a recess formed on the surface,
A semiconductor element flip-chip connected to the internal terminal portion via a bump provided on the plating layer in the recess,
The semiconductor element, have a, a resin for sealing a region including the surface of the bumps, and the lead portion,
A plurality of the lead portions are provided, and the plurality of the lead portions include at least one first lead portion in which only one of the recess and the plating layer is formed on the front surface side,
A plurality of lead portions are provided, and the plurality of lead portions include at least one second lead portion having a plurality of the recesses and the plating layer formed on the front surface side .

A method of manufacturing a lead frame according to another aspect is a method of manufacturing a lead frame for mounting a semiconductor element, which includes a lead portion having an internal terminal portion on a front surface side,
A step of forming a plurality of concave portions having a bottom portion of a substantially flat surface and a downward curved convex-shaped side surface in a predetermined region where the internal terminal portion on the surface side of the metal plate is to be formed;
A step of forming a plating layer inside the recess,
A first lead portion having only one recess in the internal terminal portion and having a predetermined shape, and a second lead portion having a plurality of recesses in the internal terminal portion and having a predetermined shape. Forming process,
Have.

Furthermore, a method of manufacturing a semiconductor device according to another aspect includes a step of forming a bump on the plating layer in the recess of the lead frame manufactured by the method of manufacturing the lead frame,
A step of flip-chip mounting a semiconductor element on the surface side of the lead portion using the bump;
And a step of sealing a region other than the front surface of the semiconductor element, the bump, and the lead portion with a resin.

  According to the present invention, there are provided a lead frame suitable for flip-chip mounting, capable of reducing the chip size, increasing the number of pins, and reducing the cost, a semiconductor device using the same, and a manufacturing method thereof. it can.

It is a figure which shows an example of the lead frame which concerns on the 1st Embodiment of this invention. FIG. 1A is a sectional view showing an example of a lead frame according to an embodiment of the present invention. FIG. 1B is a plan view showing an example of the lead frame according to the first embodiment of the present invention. FIG. 3 is a perspective view showing an example of a tip shape of a lead portion of the lead frame according to the first embodiment of the present invention. It is sectional drawing which showed an example of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure which showed the example of the lead frame 50 which concerns on the 1st Embodiment of this invention with the comparative example. FIG. 4A is a diagram showing an example of the lead frame 50 according to the first embodiment of the present invention. FIG. 4B is a diagram showing a lead frame according to a comparative example. FIG. 4 is a diagram showing a series of steps in the first half of an example of the method for manufacturing the lead frame for mounting a semiconductor element according to the first embodiment of the present invention. FIG. 5A is a diagram showing an example of the metal plate preparing step. FIG. 5B is a diagram showing an example of the recess resist forming step. FIG. 5C is a diagram showing an example of the recess etching step. FIG. 5D is a diagram showing an example of the recess plating process. FIG. 6 is a diagram showing a series of steps in the latter half of the example of the method for manufacturing the semiconductor element mounting lead frame according to the first embodiment of the present invention. FIG. 6A is a diagram showing an example of a recessed resist removing step. FIG. 6B is a diagram showing an example of the lead portion resist forming step. FIG. 6C is a diagram showing an example of the lead portion etching step. FIG. 6D is a diagram showing an example of the lead portion resist removing step. FIG. 6 is a diagram showing a series of steps of an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 7A is a diagram showing an example of the bump forming process. FIG. 7B is a diagram showing an example of a semiconductor element mounting process. FIG.7 (c) is the figure which showed an example of the resin sealing process. FIG.7 (d) is the figure which showed an example of the individualization process. It is sectional drawing which shows an example of the lead frame which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows an example of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure showing a series of steps of the first half of an example of a manufacturing method of a lead frame for semiconductor device mounting concerning a 2nd embodiment of the present invention. FIG. 10A is a diagram showing an example of the metal plate preparing step. FIG. 10B is a diagram showing an example of the recess resist forming step. FIG. 10C is a diagram showing an example of the recess etching process. FIG. 10D is a diagram showing an example of the recess plating step. It is a figure showing a series of steps of a middle stage of an example of a manufacturing method of a semiconductor device mounting lead frame concerning a 2nd embodiment of the present invention. FIG. 11A is a diagram showing an example of a resist stripping process for recesses. FIG. 11B is a diagram showing an example of a back surface plating resist forming step. FIG. 11C is a diagram showing an example of the back surface plating step. FIG. 11D is a diagram showing an example of the resist stripping process for backside plating. It is a figure showing a series of steps of the latter half of an example of a manufacturing method of a lead frame for mounting a semiconductor device concerning a 2nd embodiment of the present invention. FIG. 12A is a diagram showing an example of the lead portion resist forming step. FIG. 12B is a diagram showing an example of the lead portion etching step. FIG. 12C is a diagram showing an example of the lead portion resist stripping step. It is a figure showing a series of processes of an example of manufacturing method 100a of a semiconductor device concerning an embodiment of the present invention. FIG. 13A is a diagram showing an example of the bump forming process. FIG. 13B is a diagram showing an example of a semiconductor element mounting process. FIG. 13C is a diagram showing an example of the resin sealing step. FIG. 13D is a diagram showing an example of an etching process after resin sealing.

  Embodiments for carrying out the present invention will be described below with reference to the drawings.

[Leadframe and Semiconductor Device of First Embodiment]
FIG. 1 is a diagram showing an example of a lead frame according to the first embodiment of the present invention. FIG. 1A is a sectional view showing an example of a lead frame according to an embodiment of the present invention. FIG. 1B is a plan view showing an example of the lead frame according to the first embodiment of the present invention. FIG. 2 is a perspective view showing an example of the tip shape of the lead portion of the lead frame according to the first embodiment of the present invention.

  As shown in FIGS. 1A and 1B, the lead frame 50 according to the first embodiment of the present invention has a semiconductor element mounting region 40 on which a semiconductor element can be mounted. Further, the lead frame 50 has lead portions 11 and 12 extending from an area included in the semiconductor element mounting area 40 to the periphery of the semiconductor element mounting area 40. The lead parts 11 and 12 have external terminal parts 111 and 121 on the back surface side for connecting to an external device, and have internal terminal parts 110 and 120 for connecting the electrodes of the semiconductor element on the front surface side. ing. The internal terminal portion 110120 is an area that extends inward with a certain width at the tips of the lead portions 11 and 12. As shown in FIGS. 1 and 2, the recesses 20 are formed on the surfaces of the internal terminal portions 110 and 120, and the plating layer 30 is formed inside the recesses 20. In the lead frame for a power semiconductor device, the lead parts 11 and 12 are specifically the control system lead part 11 and the power system lead part 12. However, when it is not necessary to distinguish the two, the lead parts 11 and 12 are simply used. , 12 may be called.

  Although the bottom surface 21 and the side surface 22 of the recess 20 are clearly separated in FIG. 2, since the recess 20 is formed by etching, the bottom surface 21 and the side surface 22 are actually formed. It becomes a dent shape with a gentle curved surface with an ambiguous boundary.

  FIG. 3 is a sectional view showing an example of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 3, the semiconductor device 100 according to the first embodiment is configured using the lead frame 50 according to the above-described first embodiment. Specifically, in the semiconductor device 100, the semiconductor element 60 is flip-chip connected to the lead portions 11 and 12 of the lead frame 50 via the bump 70, and the semiconductor element 60, the bump 70, and the upper surfaces of the lead portions 11 and 12. And the side surfaces are sealed with resin 80.

  Hereinafter, each component of the lead frame 50 and the semiconductor device 100 according to the first embodiment will be individually described.

  As shown in FIG. 3, in the semiconductor device 100, the electrode 61 of the semiconductor element 60 and the lead portions 11 and 12 of the lead frame 50 are connected by a flip-chip connection method. Therefore, the lead frame 50 does not have a die pad portion or the like on which the semiconductor element 60 is mounted. As shown in FIG. 1B, the semiconductor element mounting region 40 is a region that covers the internal terminal portions 110 and 120 of the lead portions 11 and 12.

  As shown in FIGS. 1 and 3, the lead portions 11 and 12 are formed by etching the metal plate 10. The metal plate 10 generally uses a Cu material or a Cu alloy material. Internal terminal portions 110 and 120, which are connected to the electrodes 61 of the semiconductor element 60, are arranged on the front surface side of the tip portions of the lead portions 11 and 12. External terminal portions 111 and 121, which are connected to an external device with a solder alloy or the like, are provided on the back surface side. A plating layer may be formed on the back surfaces of the lead portions 11 and 12, and the regions where the plating layer is formed may be used as the external terminal portions 111 and 121.

  Next, features of the lead frame 50 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3. The feature of the lead frame 50 according to the first embodiment of the present invention is that the recesses 20 are formed in the regions of the internal terminal portions 110 and 120 that are connected to the electrodes 61 of the semiconductor element 60 by the flip chip method. That is, the plating layer 30 is formed. In the case of flip-chip mounting, the electrodes 61 of the semiconductor element 60 are often arranged around the outer shape of the semiconductor element 60. In accordance with this, the internal terminal portions 110 and 120 at the tips of the lead portions 11 and 12 are arranged so as to match them. Due to the miniaturization and the increase in the number of pins, the pitch between the electrodes becomes narrower as the size of the semiconductor element 60 becomes smaller and the number of pins becomes larger, and the tip shapes of the lead parts 11 and 12 are adjacent to each other. Of the bumps and the lead portions 11 including the internal terminal portions 110 and 120 so that the tips of the internal terminal portions 110 and 120 of the lead portions 11 and 12 do not contact the semiconductor element 60 itself. It has been demanded that the tip shapes of 12 be substantially equal in size. Therefore, it is necessary to improve the accuracy of the mounting position of the bump 70 and match the position of the electrode 61 of the semiconductor element 60. Therefore, if the bump 70 protrudes from a predetermined position, it may exceed the lead shape and come into contact with the adjacent lead portions 11 and 12. When the bumps 70 are solder bumps, the solder may wet and spread on the side surfaces of the lead portions 11 and 12 during reflow, and may come into contact with the adjacent lead portions 11 and 12.

  1 and 3, the lead frame 50 for mounting a power semiconductor element and the power semiconductor device 100 are taken as an example. The power semiconductor element 60 is a semiconductor element 60 that controls electric power. Therefore, the power semiconductor device 100 has a power system lead section 12 for inputting and outputting electric power and a control system lead section 11 for controlling input and output of electric power, in which a relatively large current flows. A characteristic of the power semiconductor device 100 is that a relatively large current flows through the power system lead section 12, so that the connection between the power system lead section 12 and the electrode of the semiconductor element is preferably low resistance. While one lead is connected to one lead, a plurality of bumps 70 are formed, and the bump shape is elliptical and the area is increased to reduce the resistance. When these are flip-chip mounted, since a plurality of bumps 70 are formed on the same plane, stress is likely to be applied to the joint portion, and in order to prevent this, solder bumps are often used as the bumps 70. Hereinafter, an example in which the bump 70 is configured as a solder bump will be described. The solder bump 70 absorbs such stress. However, in the case of the solder bump 70, there is a tendency that the wetting and spreading during reflow increases. Particularly, in the power system lead portion 12 of the power semiconductor device 100 having a reduced package size, the interval between the bumps 70 becomes narrow, and a solder bridge may occur during reflow. Further, even if the solder bridge is not reached, the solder bump 70 may spread beyond a predetermined range. These are then resin-sealed, including the flip-chip joints, but at this time, solder bridges and wet-spreading portions exceeding a predetermined range become an obstacle, and unfilled portions are generated in a part between the bumps 70. Therefore, in the power semiconductor device 100, it is important to manage the spread of solder.

  Therefore, the lead frame 50 according to the first embodiment of the present invention has been studied in view of the above problems. The recesses 20 were formed in the internal terminal portions 110, 120 at the tips of the lead portions 11, 12 of the lead frame 50 according to the present embodiment, and the plating layer 30 was formed inside the recesses 20. The plating layer 30 covers the inner surface of the recess 20 and has a hollow shape in which the peripheral portion of the plating layer 30 is high and the central portion is low.

  FIG. 4 is a diagram showing an example of the lead frame 50 according to the first embodiment of the present invention together with a comparative example. FIG. 4A is a diagram showing an example of the lead frame 50 according to the first embodiment of the present invention. As shown in FIG. 4A, the plating layer 30 is formed inside the recess 20. However, the recess 20 has a shape in which the central portion is slightly deeper and the peripheral portion is more deeply recessed than the central portion. It is shallow and the bottom is high. Accordingly, the plating layer 30 also has a hollow shape in which the central portion is lower than the peripheral portion.

  On the other hand, FIG. 4B is a diagram showing a lead frame according to a comparative example, but when the recess 20 is not formed and the plating layer is formed on the flat surface, the plating layer is projected more than the surface. It has a shape.

  As described above, when the recesses 20 are formed on the surfaces of the internal terminal portions 110 and 120 of the lead portions 11 and 12 by etching and the plating layer 30 is formed on the recesses 20, the center portion of the plating layer 30 is recessed more than the peripheral portion. It becomes a dimple shape. The depth of the depression shape of the plating layer 30 is, for example, 3 μm to 20 μm. Solder bumps 70 are formed in the recesses, and then the semiconductor element 60 is mounted by flip chip bonding. At this time, the solder is reflowed. The depth of the recess is set according to the size of the solder bump 70 so that the solder does not spread beyond the plating layer 30 when the solder is reflowed. If the depth of the depression is large, the risk of contact between the lead portions 11 and 12 and the lower surface of the semiconductor element increases, and if the gap is narrow, the gap may not be filled with the sealing resin. On the contrary, if the depth of the depression is shallow, there is no effect. Therefore, the recess depth is set to be 5 μm to 20 μm. It is preferably 5 μm to 10 μm.

  The type of plating of the plating layer 30 is not limited as long as it has good bondability with solder bumps and the like. A single layer plating of Au, Ag, and Pd, or a laminated plating in which a Ni plating layer, a Pd plating layer, and an Au plating layer are stacked from the surface of the recess 20 may be used. The outermost surface layer of the plating layer 30 is preferably Au plating that has good wettability with the solder bumps. In the lead frame 50 according to the first embodiment of the present invention, in the lead portions 11 and 12, the formation of the plating layer 30 is limited to only the inner surface of the recess 20 in which the solder bump or the like is formed. The periphery of the recess 20 is not plated, and the material surface of the lead frame 50 (the surface of the metal plate 10) is exposed. If the outermost surface layer of the plating layer 30 is an Au plating layer, when the solder bumps are reflowed, the solder concentrates on the Au plating having good solder wettability, and the material surface of the lead frame 50 is exposed in the recess 20. It is possible to prevent the surrounding from spreading. When the same kind of plating is applied to the periphery of the recess 20, the solder may spread. In the case of gold bumps, solder plating may be used.

  The thickness of the plating layer 30 is not limited. The thickness of the plating layer 30 is set in consideration of the type of plating, the bondability with the solder bump 70, and the like. The thickness of the plating layer 30 is closely related to the depth of the recess 20.

  The recess 20 is arranged at a position for flip-chip mounting. The size is set to such an extent that the solder bump 70 can prevent the solder from spreading when it is reflowed. After that, since the inside of the recess 20 is plated, the depth of the recess 20 is adjusted so that the depth of the recess of the plating layer 30 finally becomes 5 μm to 20 μm in consideration of the thickness of the plating layer 30. And the thickness of the plating layer 30 are set. For example, when the depth of the recess 20 is 10 μm and Ag plating is performed on the inner surface of the recess 20 with a plating thickness of 5 μm, the plating layer 30 is plated also on the side surface of the recess 20 so that the peripheral portion of the plating layer 30 is It is possible to form a hollow shape having a high center and a low center. When the amount of the solder bumps 70 is large or the amount of the solder bumps 70 is likely to vary, such as the power system lead portion 12 of the power semiconductor device 100 described above, it is possible to adjust it by the depth of the recess of the plating layer 30. You can and are effective.

  As shown in FIG. 2, the concave portion 20 has a bottom surface 21 and a curved side surface 22 that is convex downward. The side surface 22 does not necessarily have to be a curved surface, but since the recess 20 is formed by etching the surface of the metal plate 10, the etched surface has a curved surface. Since the bottom surface 21 is also an etching surface, it is not a completely flat surface but a surface having some irregularities.

  Further, the recess 20 has a depth of 10 μm, the inner surface of the recess 20 is Ni-plated to have a plating thickness of 10 μm, and then Pd plating is formed to a thickness of 0.05 μm, and an Au plating layer is further formed thereon. When the three-layer laminated plating is formed to have a thickness of 0.005 μm, the central portion of the plating layer 30 has substantially the same height as the position of the surface of the lead portion. On the other hand, in the peripheral portion of the plating layer 30, plating is applied from the side surface of the recess 20, and the current concentrates on the edge of the recess 20, and the peripheral effect of the plating layer 30 is increased due to the edge effect of thick plating on the peripheral portion. Get higher When the semiconductor device is miniaturized, integrated, has a large number of pins, the area for flip-chip connection is small, and the solder bump 70 is small, the distance between the lead portions 11 and 12 and the semiconductor element is ensured and the solder spreads. This is effective as a method of forming the concave portion 20 for preventing the above. Further, by forming the recessed shape of the plating layer 30 and making the thickness of the plating layer 30 thicker than the depth of the recess 20, the position of the central portion of the plating layer 30 is made higher than the position of the surface of the lead portions 11 and 12. You can also That is, the distance between the lead portions 11 and 12 and the semiconductor element 60 can be made wider. In this case, when the solder bump 70 is reflowed, it may spread from the recessed portion of the plating layer 30 to the side surface of the plating layer 30, so that the size of the bump needs to be careful.

  As described above, the power semiconductor device 100 has the power system lead section 12 and the control system lead section lead section 11, which have different functions. Therefore, the power system lead portion 12 preferably has low resistance for connection of electrodes of the semiconductor element, has a connection shape of an elliptical shape or the like, has a large area, and has a large amount of solder bumps. Therefore, the depression position of the plating layer 30 is set lower than the surface of the power system lead portion 12, and the depression position of the plating layer 30 in the control system lead portion 11 is set to a height almost equal to that of the control system lead portion 11. You may form the plating layer 30 so that it may become.

  Examples of the power semiconductor device include a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor and a transistor such as an IGBT (Insulator Gate Bipolar Transistor) whose control input terminal is a gate. The input terminal and the output terminal are the source and the drain in the case of the power MOSFET, and the emitter and the collector in the case of the IGBT.

  The shape of the recess 20 is not particularly limited, but is generally circular in many cases. In addition, the power system lead portion 12 and the like of the power system semiconductor device 100 need to flow a large current and need to have a large grounding area. Therefore, it is preferable to use a shape having a large area such as an elliptical shape.

  Since the plating layer 30 has a hollow shape having a high peripheral portion and a low central portion, it is also effective as a guide when forming the solder bumps 70. Since the central portion has a low dent shape, the solder bump 70 tends to be due to the central portion of the plating layer 30, and when flip-chip connection is performed, improvement in positional accuracy with the solder bump 70 can be expected.

[Method for Manufacturing Lead Frame According to First Embodiment]
Next, a method of manufacturing the semiconductor element mounting lead frame 50 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a diagram showing a series of steps in the first half of the example of the method for manufacturing the lead frame for mounting a semiconductor element according to the first embodiment of the present invention.

  FIG. 5A is a diagram showing an example of the metal plate preparing step. As shown in FIG. 5A, in manufacturing the lead frame according to the embodiment of the present invention, first, the metal plate 10 is prepared. The material of the metal plate 10 used is not particularly limited as long as it is a lead frame material, but Cu alloy or Cu is generally used.

  FIG. 5B is a diagram showing an example of the recess resist forming step. In the resist forming step for the recess, specifically, the surface of the metal plate 10 is covered with a resist, exposed and developed to form a resist mask 92 for the recess. The entire front and back surfaces of the metal plate 10 are covered with the resist 90. As the resist 90 to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by coating and drying a liquid resist can be used. Next, in the exposure, after the front and back surfaces of the metal plate 10 are coated with the resist 90 in the previous resist coating step, the resist 90 is covered, and on the front surface side, the concave portions 20 are formed in the internal terminal portions 110 and 120. A mask (ultraviolet light shielding glass mask) having a desired pattern and a pattern covering the entire back surface is formed and exposed.

  In the development, the mask is removed and the resist 90 is developed to remove the portion (uncured portion) forming the recess 20 on the surface to form the opening 91 and expose the surface of the metal plate 10. As a result, a concave mask 92 composed of the resist 90 and the opening 91 that remain after curing is formed.

  FIG. 5C is a diagram showing an example of the recess etching step. As shown in FIG. 5C, the formed resist mask 92 is used as a recess etching mask 92 to perform etching on the surface of the metal plate 10 to form the recess 20. The etching depth is 5 μm or more and 30 μm or less, preferably 5 μm to 20 μm.

  FIG. 5D is a diagram showing an example of the recess plating process. As shown in FIG. 5D, the formed resist mask 92 is used as a recess plating mask to perform plating on the surface of the metal plate 10 on which the recess 20 is formed to form a plating layer 30 inside the recess 20. . The plating layer 30 is formed on the bottom surface 21 and the side surface 22 of the recess 20. The type of plating is not particularly limited. For the surface layer of the plating layer 30, it is preferable to use Au or the like, which has good bonding properties.

  FIG. 6 is a diagram showing a series of steps in the latter half of the example of the method for manufacturing the semiconductor element mounting lead frame according to the first embodiment of the present invention.

  FIG. 6A is a diagram showing an example of a recessed resist removing step. In the recessed resist removing step, the cured resist 90 is removed. As a result, the concave portion 20 is formed on the front surface side of the metal plate 10, and the plating layer 30 is formed inside the concave portion 20.

  In addition, when a plating layer is required for the external terminal portion on the back surface side, after the step of FIG. 6A, the recess etching step of FIG. A series of steps of a) is performed, a resist mask is formed so as to plate the corresponding areas of the external terminal portions 111 and 121 in place of the recesses, and a plating layer is formed (not shown).

  FIG. 6B is a diagram showing an example of the lead portion resist forming step. In the lead portion resist forming step, in detail, the front surface side and the back surface side of the metal plate 10 are coated with resist, exposed, and developed to form lead portion resist masks 96 and 97. In FIG. 6B, first, the resist 94 covers the entire surface of the metal plate 10 where the recess 20 is formed and the back surface of the metal plate 10. The resist 94 used may be a conventionally known method such as laminating a dry film resist or coating a resist layer by coating and drying a liquid resist. Next, in the exposure, after the resist 94 is coated on the front and back surfaces of the metal plate 10 by the previous resist coating, a predetermined pattern is formed on the front and back surfaces so that the lead portion shape can be formed. Note that at least a region where the internal terminal portions 110 and 120 are formed is covered with the resist 94. Next, exposure is performed by covering with a mask (ultraviolet light shielding glass mask) on which a pattern is formed.

  In the development, the mask is removed and the resist 94 is developed to remove the uncured portion to form the opening 95 and expose the surface of the metal plate 10. As a result, the masks 96 and 97 for the lead portion, which are composed of the resist 94 and the opening 95 that remain after curing, are formed.

  FIG. 6C is a diagram showing an example of the lead portion etching step. In the lead portion etching step, the lead portion resist masks 96 and 97 formed in FIG. 6B are used to etch the metal plate 10 to form lead portions 11 and 12.

  FIG. 6D is a diagram showing an example of the lead portion resist removing step. In the lead portion plating resist removing step, the hardened resist 94 is removed.

  As a result, the lead frame 50 is completed. If necessary, the sheet may be cut into a predetermined size.

  In this way, the lead frame 50 according to the embodiment of the present invention is manufactured by sequentially performing the above-described steps.

[Method for Manufacturing Semiconductor Device of First Embodiment]
Next, an example of a method of manufacturing the semiconductor device 100, which manufactures the semiconductor device 100 using the lead frame 50 manufactured by the above-described manufacturing method, will be described with reference to FIG. 7. Note that FIG. 7 illustrates an example in which the semiconductor element 60 and the lead portion 30 are connected by a flip chip method.

  FIG. 7 is a diagram showing a series of steps of an example of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

  FIG. 7A is a diagram showing an example of the bump forming process. In the bump forming step, the bump 70 for connecting to the semiconductor element 60 is formed on the surface of the plating layer 30 of the internal terminal portions 110 and 120 of the lead portions 11 and 12 of the semiconductor element mounting lead frame 50.

  FIG. 7B is a diagram showing an example of a semiconductor element mounting process. The electrode 61 of the semiconductor element 60 is connected to the bump 70 formed in FIG. 7A, and the semiconductor element 60 is mounted above the internal terminal portions 110 and 120 of the lead portions 11 and 12.

  FIG.7 (c) is the figure which showed an example of the resin sealing process. In the resin sealing step, the entire surface of the lead frame 50 on which the semiconductor element 60 is mounted is sealed with the resin 80. Thereby, the semiconductor device 100 is obtained in which only the bottom surfaces of the external terminal portions 111 and 121 of the lead portions 11 and 12 are exposed from the resin 80.

  FIG.7 (d) is the figure which showed an example of the individualization process. Finally, in the individualizing step, as shown in FIG. 7D, the semiconductor device 100 is completed by cutting it into a predetermined size of the semiconductor device 100.

  According to the lead frame 50 and the semiconductor device 100 according to the first embodiment, when the power semiconductor element 60 is mounted by flip-chip connection, even if the interval between adjacent bumps is narrow, the wet spread of the bumps occurs. It is possible to meet the demand for downsizing and thinning.

[Leadframe and Semiconductor Device of Second Embodiment]
FIG. 8 is a sectional view showing an example of the lead frame 50a according to the second embodiment of the present invention. FIG. 9 is a sectional view showing an example of a semiconductor device 100a according to the second embodiment of the present invention.

  The lead frame 50a according to the second embodiment of the present invention has a semiconductor element mounting region 40a on which the semiconductor element 60a (see FIG. 9) can be mounted. The lead portion 11a is arranged in a region included in the semiconductor element mounting region 40a in a top view. The surface side of the lead portion 11a functions as the internal terminal portion 110a, and the recess 20a is formed in the internal terminal portion 110a. A lead surface plating layer 30a is formed inside the recess 20a. Further, a lead back surface plating layer 31 is formed on the back surface side of the lead portion 11a. The lead back surface plating layer 31 functions as an external terminal portion for connecting to an external device, and the lead surface plating layer 30a serves as an internal terminal portion 110a for connecting the electrode 61a of the semiconductor element 60a. The lead part 11a forms the lead part 11a and the back surface connecting metal part 13 from a part of the metal plate 10a along the substantially planar shape of the lead surface plating layer 30a from the front surface side to the back surface of the metal plate 10a. A through-hole region 14 is provided. The lead portion 11a has a columnar shape by processing the non-penetrating recessed region 14.

  Compared to the lead frame 50 according to the first embodiment, in the lead frame 50a according to the second embodiment, the lead portion 11a is formed along the substantially planar shape of the lead surface plating layer 30a, and the metal plate By forming the lead portion 11a and the non-penetrating depression region 14 forming the back surface connecting metal portion 13 from a part of 10 and performing the non-penetrating depression processing, the metal plate 10 is formed on the entire back surface side. The difference remains. In the first embodiment, since the lead parts 11 and 12 are separated from each other with a predetermined gap, they cannot be held unless they are connected to the frame part of the lead frame 50 by a connecting piece or the like. After the resin is sealed, the lead pieces 11 and 12 are individually separated by cutting the connecting piece from the frame portion. In the second embodiment, since the metal plate 10 remains on the entire back surface, the metal plate 10 can be freely set without considering the arrangement of the connecting pieces. For example, the lead portions 11a can be provided in a plurality of rows, that is, two rows and three rows without paying attention to the arrangement of the connecting pieces.

  The formation of the recess 20a in the internal terminal portion 110a, which is a feature of the present invention, and the formation of the plating layer 30a inside the recess 20a are the same as those of the lead frame 50 according to the first embodiment.

  FIG. 9 is a sectional view showing an example of a semiconductor device 100a according to the second embodiment of the present invention. The upper surface of the columnar lead portion 11a functions as the internal terminal portion 110a, the concave portion 20a is provided on the surface of the internal terminal portion 110a, and the lead surface plating layer 30a is provided on the inner surface of the concave portion 20a. The semiconductor element 60a is flip-chip connected to the internal terminal portion 110a via the bump 70a. The surface side of the semiconductor element 60a, the bump 70a, and the lead portion 11a are sealed with a resin 80a. In addition, a part of the back surface side of the columnar lead portion 11a protrudes without being sealed by the resin 80a, and a lead back surface plating layer 31 is formed on the back surface.

  The semiconductor device 100a according to the second embodiment is different from the first embodiment in that after the surface is sealed with the resin 80a, the back surface connecting metal portion 13 is formed from the back surface side using the lead back surface plating layer 31 as an etching mask. The difference is that the lead portions 11 a are individually etched and made independent, and the external terminal portions 111 a project from the resin 80 a.

  As described above, the present invention can be applied to a tapeless QFN substrate, and can be applied to various lead frames 50a and semiconductor devices 100a for flip-chip connection.

[Method for Manufacturing Lead Frame of Second Embodiment]
Next, a method of manufacturing a semiconductor element mounting lead frame according to the second embodiment of the present invention will be described with reference to FIGS.

  FIG. 10 is a diagram showing a series of steps in the first half of an example of a method for manufacturing a semiconductor device mounting lead frame according to the second embodiment of the present invention.

  FIG. 10A is a diagram showing an example of the metal plate preparing step. As shown in FIG. 10A, when manufacturing the lead frame 50a according to the embodiment of the present invention, first, the metal plate 10a is prepared. The material of the metal plate 10a used is not particularly limited as long as it is a lead frame material, but Cu alloy or Cu is generally used.

  FIG. 10B is a diagram showing an example of the recess resist forming step. In the concave portion resist forming step, specifically, the metal plate 10a is covered with a resist, exposed and developed to form a concave portion resist mask 92a. The entire front and back surfaces of the metal plate 10 are covered with the resist 90a. As the resist 90a to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by coating and drying a liquid resist can be used. Next, in the exposure, after the front and back surfaces of the metal plate 10a are coated with the resist 90a in the previous resist coating step, on the front surface side, a desired pattern is formed on the resist 90a at the positions to be the recesses 20a in the internal terminal portions 110a. On the back side, a mask (ultraviolet light shielding glass mask) having a pattern covering the entire surface is covered and exposure is performed.

  In the development, the mask is removed and the resist 90a is developed to remove the portion (uncured portion) forming the recess 20a on the surface to form the opening 91a and expose the surface of the metal plate 10a. As a result, a concave mask 92a including the resist 90a remaining after curing and the opening 91a is formed.

  FIG. 10C is a diagram showing an example of the recess etching process. As shown in FIG. 10C, using the formed resist mask 92a as a recess etching mask, etching is performed on the surface of the metal plate 10a to form the recess 20a. The etching depth is 5 μm or more and 30 μm or less, preferably 5 μm to 20 μm.

  FIG. 10D is a diagram showing an example of the recess plating step. As shown in FIG. 10D, using the formed resist mask 92a as a recess plating mask, the surface of the metal plate 10a on which the recess 20a is formed is plated to form a plating layer 30a inside the recess 20a. To do. The type of plating is not particularly limited, but it is preferable to use Ni plating that has strength even in a thin film. For the surface layer, Au or the like having good bonding property is used.

  FIG. 11 is a diagram showing a series of steps in the middle stage of an example of a method for manufacturing a lead frame for mounting a semiconductor device according to the second embodiment of the present invention.

  FIG. 11A is a diagram showing an example of a resist stripping process for recesses. In the recessed resist removing step, the cured resist 90a is removed. As a result, the recess 20a is formed on the metal plate 10a, and the plating layer 30a is formed inside the recess 20a.

  FIG. 11B is a diagram showing an example of a back surface plating resist forming step. In the back surface plating resist forming step, similarly to FIG. 10B, the surface of the metal plate 10a is covered with a resist 94a, exposed and developed to form a back surface plating resist mask 96a having an opening 95a.

  FIG. 11C is a diagram showing an example of the back surface plating step. As shown in FIG. 11C, using the formed resist mask 96a as a back surface plating mask, the back surface side of the metal plate 10a is plated to form the lead back surface plating layer 31.

  FIG. 11D is a diagram showing an example of the resist stripping process for backside plating. In the back surface plating resist removing step, the hardened resist 94a is removed.

  FIG. 12 is a diagram showing a series of steps in the latter half of the example of the method for manufacturing the lead frame for mounting a semiconductor device according to the second embodiment of the present invention.

  FIG. 12A is a diagram showing an example of the lead portion resist forming step. In the lead portion resist forming step, in detail, resist coating, exposure, and development are performed to form a lead portion resist mask 99a. In FIG. 10D, the resist 97a covers the entire surface on the front surface side and the entire surface on the rear surface side where the concave portion 20a is formed in the metal plate 10a. As the resist 97a to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by coating and drying a liquid resist can be used. Next, in the exposure, the resist 97a is coated on the front and back surfaces of the metal plate 10a by the previous resist coating, and then a pattern capable of forming a lead portion shape on the front surface side, and a pattern on the back surface side covered by the entire resist mask. A mask (ultraviolet light shielding glass mask) on which is formed is covered, and exposure is performed. At least the internal terminal portion 110a is covered with the resist 97a.

  In the development, by removing the mask and developing the resist 97a, the uncured portion is removed to form the opening 98a, and the surface side of the metal plate 10a is exposed. As a result, the lead portion mask 99a including the resist 97a that remains after curing and the opening 98a is formed.

  FIG. 12B is a diagram showing an example of the lead portion etching step. In the lead portion etching step, using the lead portion resist mask 99a formed in FIG. 12A, the front surface side of the metal plate 10a is etched to form a non-penetrating depression, thereby forming a columnar lead portion 11a. To do.

  FIG. 12C is a diagram showing an example of the lead portion resist stripping step. In the lead portion plating resist removing step, the cured resist 97a is removed.

  As a result, the lead frame 50a is completed. If necessary, the sheet may be cut into a predetermined size.

  In this way, the lead frame 50a according to the second embodiment of the present invention is manufactured by sequentially performing the above steps.

[Method of Manufacturing Semiconductor Device of Second Embodiment]
Next, a method of manufacturing the semiconductor device 100a according to the second embodiment of the present invention will be described with reference to FIG.

  FIG. 13 is a diagram showing a series of steps of an example of the semiconductor device manufacturing method 100a according to the embodiment of the present invention.

  FIG. 13A is a diagram showing an example of the bump forming process. In the bump forming step, the bump 70a for connecting to the semiconductor element 60a is formed on the surface of the plating layer 30a of the internal terminal portion 110a of the lead portion 11a of the semiconductor element mounting lead frame 50a.

  FIG. 13B is a diagram showing an example of a semiconductor element mounting process. The electrode portion 61a of the semiconductor element 60a is connected to the bump 70a formed in FIG. 13A, and the semiconductor element 60a is flip-chip mounted on the upper side of the internal terminal portion 110a of the lead portion 11a.

  FIG. 13C is a diagram showing an example of the resin sealing step. In the resin sealing process, the upper side of the front surface side of the lead frame 50a including the semiconductor element 60a, the bump 70a, and the recessed region 14 is resin-sealed with the resin 80a.

  FIG. 13D is a diagram showing an example of an etching process after resin sealing. After the resin sealing step, the lead portion 11a is individually separated by etching the back surface connecting metal portion 13 of the metal plate 10a from the back surface side using the lead back surface plating layer 31 as a mask.

  Finally, the semiconductor device 100a is completed by cutting the semiconductor device 100a into a predetermined size.

  As described above, according to the method for manufacturing the lead frame 50a and the semiconductor device 100a according to the second embodiment of the present invention, the lead frame 50a and the semiconductor device 100a that are compatible with the downsizing and the thinning of the tapeless QFN substrate are also provided. Can be manufactured.

  Examples of manufacturing and implementing the lead frame and the semiconductor device according to the embodiment of the present invention will be described below.

[Example 1]
A Cu plate having a thickness of 0.2 mm (Furukawa Electric Co., Ltd .: EFTEC64-T) is processed into a long plate having a width of 140 mm as a metal plate, and then a photosensitive dry film resist having a thickness of 0.05 mm (Asahi Kasei E. AQ-5038 manufactured by Materials Co., Ltd. was attached to both sides of the metal plate with a laminating roll.

  Next, a dry film resist was covered with a glass mask having a desired pattern for forming a recess in the internal terminal region for mounting a semiconductor element on the front surface side and a pattern for covering the entire surface on the back surface side, and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer was removed was etched. A ferric chloride solution was used as the etching solution. The etching depth was 10 μm. As a result, a recess was formed in the internal terminal portion.

  Next, the recesses formed by etching were plated in the order of Ni plating of 5 μm, Pd plating of 0.01 μm, and Au plating of about 0.003 μm including the side surfaces of the recesses. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, a concave portion was formed in the internal terminal portion of the lead portion on the metal plate, and a plating layer was formed inside the concave portion. The plating layer had a recess of 10 μm.

  Next, a photosensitive dry film resist (AQ-5038 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was again attached to both surfaces of the conductive base material with a laminating roll.

  Next, a glass mask having a pattern covering the entire surface on the front surface side and a desired pattern for forming a plating layer on the external terminal portion area on the back surface was covered on the dry film resist, and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer was removed was plated with Ni plating of 5 μm, Pd plating of 0.01 μm, and Au plating of about 0.003 μm in this order. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, a plating layer was formed on the external terminal portion.

  Next, a photosensitive dry film resist (AQ-5038 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was again attached to both surfaces of the conductive base material with a laminating roll.

  Next, a glass mask having a desired pattern corresponding to the lead portion was covered on the dry film resist and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer was removed was etched. A ferric chloride solution was used as the etching solution. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, the lead portion was formed.

  After that, the lead frame according to Example 1 of the present invention was obtained by cutting into a predetermined size.

  Next, flip chip bumps were formed in the connection regions of the internal terminals of the produced lead frame. Next, the electrode portion of the semiconductor element and the bump were mounted by the flip chip method, and the semiconductor element and the lead portion were connected. Next, the surface on which the semiconductor element was mounted was sealed with resin.

  Finally, the semiconductor device was completed by cutting it into a predetermined size.

[Example 2]
A Cu plate having a thickness of 0.2 mm (Furukawa Electric Co., Ltd .: EFTEC64-T) is processed into a long plate having a width of 140 mm as a metal plate, and then a photosensitive dry film resist having a thickness of 0.05 mm (Asahi Kasei E. AQ-5038 manufactured by Materials Co., Ltd. was attached to both sides of the metal plate with a laminating roll.

  Next, a dry film resist was covered with a glass mask having a desired pattern for forming recesses in the internal terminal region for mounting a semiconductor element on the front surface side and a pattern for covering the entire surface on the back surface, and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer was removed was etched. A ferric chloride solution was used as the etching solution. The etching depth was 10 μm. As a result, a recess was formed in the internal terminal portion.

  Next, the recesses formed by etching were plated in the order of 10 μm of Ni plating, 0.01 μm of Pd plating, and about 0.003 μm of Au plating including the side surfaces of the recesses. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, a concave portion was formed on the internal terminal portion of the lead portion on the metal plate, and a plating layer was formed inside the concave portion. The plating layer had a recess of 5 μm.

  Next, a photosensitive dry film resist (AQ-5038 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was again attached to both surfaces of the conductive base material with a laminating roll.

  Next, a glass mask having a pattern covering the entire surface on the front surface side and a desired pattern for forming a plating layer on the external terminal portion area on the back surface was covered on the dry film resist, and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer was removed was plated with Ni plating of 5 μm, Pd plating of 0.01 μm, and Au plating of about 0.003 μm in this order. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, a plating layer was formed on the external terminal portion.

  Next, a photosensitive dry film resist (AQ-5038 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was again attached to both surfaces of the conductive base material with a laminating roll.

  Next, a dry film resist was covered with a glass mask having a desired pattern corresponding to the lead portion on the front surface side and a pattern covering the entire surface on the back surface side with a mask, and exposed to ultraviolet light.

  After that, a development treatment was carried out by using a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to light by blocking the irradiation of ultraviolet light.

  Next, the exposed surface of the metal plate in the opening where the resist layer on the front surface side was removed was etched. A ferric chloride solution was used as the etching solution. Then, the dry film resist was peeled off with a sodium hydroxide solution. As a result, a columnar lead portion was formed on the front surface side.

  After that, the lead frame according to Example 2 of the present invention was obtained by cutting into a predetermined size.

  Next, flip chip bumps were formed in the connection regions of the internal terminals of the produced lead frame. Next, the electrode portion of the semiconductor element and the bump were mounted by the flip chip method, and the semiconductor element and the lead portion were connected. Next, the surface on which the semiconductor element was mounted was sealed with resin. After that, etching processing was performed from the back surface side to individually separate the lead portions.

Finally, the semiconductor device was completed by cutting it into a predetermined size.
[Example 3]
Example 3 is a lead frame for a power semiconductor device in Example 1. The lead section has a control system lead section and a power system lead section, and the power system lead section is a pattern for performing a plurality of flip chip connections for one terminal. The depth of the recess of the control system lead portion was 10 μm, and the depth of the recess of the power system lead portion was 20 μm. The control layer lead portion had a recess of 10 μm. A 20 μm plated layer was formed on the plated layer of the power system lead portion. Others are the same as in the first embodiment.

[Comparative example]
In the comparative example, the step of etching the concave portion in Example 3 was omitted, and in the next plating step, the Ni plating was 5 μm, the Pd plating was 0.01 μm, and the Au plating was about 0.003 μm in this order. Was plated. Others are the same as the embodiment.

  In the lead frame of each example, when the plated layer of the internal terminal portion was confirmed with a stereoscopic microscope, it was confirmed that the plated layer had a hollow shape in Examples 1 to 3.

  Further, regarding Examples 1 to 3 and Comparative Example, the semiconductor element was mounted by the flip chip method in the semiconductor device manufacturing process, and the bonding state was confirmed by a microscope. In Examples 1 to 3, there were no particular problems and the results were good. In the comparative example, during flip chip bonding of the power system lead portion, there was a problem of contact with a solder bump adjacent to a part thereof. In addition, the amount of spread of the solder is larger than that in Examples 1 to 3. It was confirmed that the flip chip regions of Examples 1 to 3 were limited and the effect of suppressing the wetting and spreading in the range was suppressed.

  The preferred embodiments and examples of the present invention have been described above in detail, but the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and Various modifications and substitutions can be made to the embodiment.

10, 10a Metal plate 11, 11a, 12 Lead part 13 Back surface connection metal part 14 Recess area 20, 20a Recessed part 30, 30a, 31 Plating layer 40, 40a Semiconductor element mounting area 50, 50a Lead frame 60, 60a Semiconductor element 70, 70a bump 80, 80a resin 100, 100a semiconductor device

Claims (18)

A lead frame for mounting a semiconductor element made of a metal material,
A lead portion having an internal terminal portion capable of flip-chip connecting a semiconductor element to a predetermined region on the front surface side,
A concave portion formed on the surface of the internal terminal portion of the lead portion, the concave portion having a bottom portion of a substantially flat surface and a curved side surface convex downward.
Possess a plating layer formed on the inner side of the recess, and
A plurality of the lead portions are provided, and the plurality of lead portions include at least one first lead portion having the recess and the plating layer formed on the front surface side, and the recess on the front surface side. And a lead frame including at least one second lead portion having a plurality of the plating layers formed thereon .   The lead frame according to claim 1, wherein the plating layer is formed in the recess, and a peripheral edge portion is formed higher than a central portion.   The lead frame according to claim 1, wherein the peripheral portion of the plating layer is higher than the central portion by 5 μm or more and 20 μm.   The lead frame according to claim 3, wherein the depth of the recess is 5 μm or more and 30 μm or less.   The lead frame according to claim 1, wherein the outermost surface layer of the plating layer is an Au plating layer. The lead frame according to any one of claims 1 to 5 , wherein the plating layer is not formed on the surface side of the lead portion other than inside the recess. The lead portion includes an external device that can be connected an external terminal portion on the back side, lead according to any one of the second plating layer according to claim 1 to 6 are formed on the external terminal portion flame. The lead frame according to claim 7 , wherein a region other than the internal terminal portion on the front surface side of the lead portion has a hollow shape recessed from the internal terminal portion. A lead portion made of a metal material and having an internal terminal portion on the surface side, in which a plating layer is formed inside the recess formed on the surface,
A semiconductor element flip-chip connected to the internal terminal portion via a bump provided on the plating layer in the recess,
A resin for sealing a region including the semiconductor element, the bump, and the front surface side of the lead portion,
A plurality of the lead portions are provided, and the plurality of the lead portions include at least one first lead portion in which only one of the recess and the plating layer is formed on the front surface side,
A plurality of the lead portions are provided, and the plurality of the lead portions includes at least one second lead portion having a plurality of the recesses and the plating layer formed on the front surface side. The semiconductor element is a power transistor having a control input terminal, an input terminal and an output terminal,
The control input terminal is flip-chip connected to the first lead portion,
The semiconductor device according to claim 9 , wherein the input terminal and the output terminal are flip-chip connected to the second lead portion. The semiconductor device according to claim 9 , wherein the lead portion has an external terminal portion on the back surface side that can be connected to an external device, and a second plating layer is formed on the external terminal portion. The lead portion has a columnar shape,
The semiconductor device according to claim 11 , wherein a part of the columnar portion on the back surface side projects from the resin. A method for manufacturing a lead frame for mounting a semiconductor device, comprising a lead portion having an internal terminal portion on a front surface side,
A step of forming a plurality of concave portions having a bottom portion of a substantially flat surface and a downward curved convex-shaped side surface in a predetermined region where the internal terminal portion on the surface side of the metal plate is to be formed;
A step of forming a plating layer inside the recess,
A first lead portion having only one recess in the internal terminal portion and having a predetermined shape; and a second lead portion having a plurality of recess portions in the internal terminal portion and having a predetermined shape. Forming process,
And a method for manufacturing a lead frame. The method of manufacturing a lead frame according to claim 13 , wherein the plating layer is selectively formed only inside the recess on the front surface side. The method of manufacturing a lead frame according to claim 13 or 14 , further comprising forming a second plating layer in a predetermined region on the back surface side of the lead portion where the external terminal portion is formed. 16. The method of manufacturing a lead frame according to claim 15 , further comprising a step of processing a region other than the internal terminal portion on the front surface side of the lead portion into a dent shape by etching. A step of forming bumps on the plating layer in the recess of the lead frame manufactured by the manufacturing method of lead frame according to any one of claims 13 to 16,
A step of flip-chip mounting a semiconductor element on the surface side of the lead portion using the bump;
And a step of sealing the semiconductor element, the bump, and a region other than the front surface of the lead portion on the back surface side with a resin. Forming a bump on the plating layer in the recess of the lead frame manufactured by the method for manufacturing a lead frame according to claim 15 or 16 ;
A step of flip-chip mounting a semiconductor element on the surface side of the lead portion using the bump;
A step of sealing the semiconductor element, the bump, and a region other than the surface of the lead portion on the back surface side with a resin;
A step of performing etching from the back surface side of the lead portion using the second plating layer as a mask to remove the metal plate in a region other than the lead portion, and processing the lead portion into a columnar shape. Device manufacturing method.