JP6138496B2 - Semiconductor device mounting substrate and semiconductor device - Google Patents

Semiconductor device mounting substrate and semiconductor device Download PDF

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JP6138496B2
JP6138496B2 JP2013007325A JP2013007325A JP6138496B2 JP 6138496 B2 JP6138496 B2 JP 6138496B2 JP 2013007325 A JP2013007325 A JP 2013007325A JP 2013007325 A JP2013007325 A JP 2013007325A JP 6138496 B2 JP6138496 B2 JP 6138496B2
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semiconductor element
terminal
element mounting
semiconductor
mounting substrate
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JP2014138155A (en
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英規 加藤
英規 加藤
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SH Materials Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

本発明は、金属板の片面側からハーフエッチング加工を行なって柱状形状を形成した半導体素子搭載用基板とその基板を用いた半導体装置に関する。   The present invention relates to a semiconductor element mounting substrate in which a columnar shape is formed by half-etching from one side of a metal plate and a semiconductor device using the substrate.

近年半導体パッケージには携帯機器向けを中心に小型化への要求がさらに強まっており、様々なパッケージ構造および製造方法の提案がなされている。
これらはＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）と呼ばれ、半導体素子に直接外部接続端子を形成するものや、樹脂基板やリードフレーム等を用いて外部接続端子を形成するものがある。 In recent years, semiconductor packages have been increasingly demanded for downsizing mainly for portable devices, and various package structures and manufacturing methods have been proposed.
These are called CSP (Chip Scale Package), and some of them form an external connection terminal directly on a semiconductor element, and some form an external connection terminal using a resin substrate, a lead frame or the like.

その中でリードフレームを用いるパッケージは多種提案されているが、多ピンに対応できるものとして、例えば特許文献１に開示されるパッケージがある。
特許文献１に記載のパッケージは、銅合金の片面を半導体搭載部や端子部などを残して、それ以外の箇所をハーフエッチングし、半導体搭載部に半導体素子を載せ、外部端子との接続を行って樹脂封止した後、反対側からエッチングを施し、パッケージを完成させるものである。
この方法によれば、端子数が１００ピン以上の半導体を小型パッケージに収めることができる。 Among them, a variety of packages using a lead frame have been proposed, but there is a package disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-151620 as one that can handle multiple pins.
In the package described in Patent Document 1, one surface of a copper alloy is left with a semiconductor mounting portion and a terminal portion, the other portions are half-etched, a semiconductor element is placed on the semiconductor mounting portion, and an external terminal is connected. After sealing with resin, etching is performed from the opposite side to complete the package.
According to this method, a semiconductor having 100 pins or more can be accommodated in a small package.

しかし、この半導体パッケージ用基板の製造工程において、特許文献１にあるような端子側面に凹部のあるモールドロック形状を、通常の半導体素子搭載パッド４１ａで見られる大面積の四辺形で、四隅が円弧で構成されるパターン以外のパターンに付与する事は困難である（図１参照）。
また、一部のパッケージデザインにおいては、図２に示すようなダイパッド４１ｂにモールドロック形状を有さない半導体パッケージ用基板もある。
図１、２において、８は半導体素子、４０ａ、４０ｂは半導体パッケージ、３２ａ、３２ｂは半導体素子搭載用基板、４１ａは半導体素子搭載パッド、４１ｂはダイパッド、４２は接続端子、４３はボンディングパッド、４４は外部接続端子部、１０はボンディングワイヤ、１１は封止樹脂である。 However, in the manufacturing process of the semiconductor package substrate, the mold lock shape having a recess on the side of the terminal as in Patent Document 1 is a large-area quadrilateral that can be seen in the normal semiconductor element mounting pad 41a, and the four corners are arcs. It is difficult to give to patterns other than the pattern constituted by (see FIG. 1).
Further, in some package designs, there is a semiconductor package substrate in which the die pad 41b as shown in FIG. 2 does not have a mold lock shape.
1 and 2, 8 is a semiconductor element, 40a and 40b are semiconductor packages, 32a and 32b are semiconductor element mounting substrates, 41a is a semiconductor element mounting pad, 41b is a die pad, 42 is a connection terminal, 43 is a bonding pad, 44 Are external connection terminal portions, 10 is a bonding wire, and 11 is a sealing resin.

米国特許第６２３８９５２号US Pat. No. 6,238,952

このように、図１や図２に示す従来の半導体パッケージ用基板を用いた半導体パッケージでは、ダイパッド４１ｂの樹脂封止後の端子引き抜き強度が不足し、組み立て後の強度確認試験において、半導体素子８が脱落するなどの問題が生じていた。
そこで、本発明は、上記従来の諸問題である、ダイパッドの樹脂封止後の端子引き抜き強度不足を解消した基板を提供するものである。 Thus, in the semiconductor package using the conventional semiconductor package substrate shown in FIG. 1 or FIG. 2, the terminal pull-out strength after resin sealing of the die pad 41b is insufficient, and in the strength confirmation test after assembly, the semiconductor element 8 There were problems such as falling off.
Accordingly, the present invention provides a substrate that solves the above-described problems of the conventional art and that lacks the terminal pull-out strength after resin sealing of the die pad.

このような状況に鑑み、本発明の第１の発明は、金属板の片面側からハーフエッチング加工を行い、柱状部形状の端子を形成する半導体素子搭載用基板において、その柱状部形状の端子が漏斗状の上部が末広がりの形状で、且つ平面形状が円形もしくは角部が円弧で形成された矩形であり、半導体素子を搭載するパッド部に、その柱状部形状のダミー端子を有することを特徴とする半導体素子搭載用基板である。 In view of such a situation, the first invention of the present invention is a semiconductor element mounting substrate in which half-etching is performed from one side of a metal plate to form a columnar-shaped terminal. The funnel-shaped upper part has a divergent shape, and the planar shape is a circle or a rectangle formed by arcs at the corners, and has a dummy terminal in the shape of a columnar part in a pad part on which a semiconductor element is mounted. This is a substrate for mounting a semiconductor element.

本発明の第２の発明は、第１の発明における柱状部形状のダミー端子が、半導体素子を外囲する配置で設けられ、ダイパッドと連結されていることを特徴とする半導体素子搭載用基板である。 According to a second aspect of the present invention, there is provided a semiconductor element mounting substrate, wherein the columnar portion-shaped dummy terminals according to the first aspect of the present invention are provided so as to surround the semiconductor element and are connected to a die pad. is there.

本発明の第３の発明は、半導体素子搭載側から半導体素子用搭載基板のパッド部に、柱状部形状のダミー端子を形成するハーフエッチング加工が施され、そのハーフエッチング加工された凹部位に封止樹脂が充填されていることを特徴とする半導体装置である。 According to a third aspect of the present invention, a half etching process for forming a columnar dummy terminal is performed on a pad part of a semiconductor element mounting substrate from the semiconductor element mounting side, and the half-etched recessed part is sealed. The semiconductor device is filled with a stop resin.

本発明による基板を用いることによって、半導体素子搭載パッドと封止樹脂との密着力を十分に確保することが可能となり、半導体パッケージ組み立て後の半導体素子脱落不具合を大きく低減する効果を奏する。   By using the substrate according to the present invention, it is possible to sufficiently secure the adhesion between the semiconductor element mounting pad and the sealing resin, and the effect of greatly reducing the problem of dropping off the semiconductor element after assembling the semiconductor package is achieved.

モールドロック形状の半導体素子搭載パッドを有する半導体パッケージ用基板を用いた半導体素子の断面図である。It is sectional drawing of the semiconductor element using the board | substrate for semiconductor packages which has a mold-lock-shaped semiconductor element mounting pad. ダイパッドにモールドロック形状を有さない半導体パッケージ用基板を用いた半導体素子の断面図である。It is sectional drawing of the semiconductor element using the board | substrate for semiconductor packages which does not have a mold lock shape in a die pad. 本発明に係るモールドロック形状端子を備える半導体パッケージ用基板を用いた半導体素子の一例で、ダイパッド部にモールドロック形状を備える場合の断面図である。It is an example of the semiconductor element using the board | substrate for semiconductor packages provided with the mold lock shape terminal which concerns on this invention, and is sectional drawing in the case of providing a mold lock shape in a die pad part. 本発明に係るモールドロック形状端子を備える半導体パッケージ用基板を用いた半導体素子の一例で、ダイパッド部がモールドロック形状を持たない場合の断面図である。It is an example of the semiconductor element using the substrate for semiconductor packages provided with the mold lock shape terminal concerning the present invention, and is a sectional view in case a die pad part does not have a mold lock shape. 本発明の半導体パッケージ用基板の製造工程フロー図である。It is a manufacturing process flowchart of the board | substrate for semiconductor packages of this invention. 本発明の半導体パッケージ用基板の製造工程フロー図である。It is a manufacturing process flowchart of the board | substrate for semiconductor packages of this invention. 本発明の半導体パッケージ用基板の半導体素子周囲のダミーパッド配置と形状の例を示す平面図で（ａ）は平面形が長方形のダミー端子を四方に配した例、（ｂ）は平面形が円形のダミー端子で外囲した例、（ｃ）は平面形が矩形のダミー端子で外囲した例である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view showing an example of dummy pad arrangement and shape around a semiconductor element of a semiconductor package substrate of the present invention. FIG. (C) is an example in which the planar shape is enclosed by a rectangular dummy terminal.

本発明の半導体素子搭載用基板の特徴とするところは、図６の半導体パッケージ用基板の半導体素子周囲のダミーパッド配置と形状を示す平面図に示すような半導体素子８と半導体素子搭載面側のボンディングパッド（図示せず）との間に一定間隔で半導体素子８を外囲するように、例えば図６（ａ）〜（ｃ）に示すような任意の大きさ、形状のダミー端子２１をパターン状に配置し、そのパターン状に配置されたダミー端子２１は、外部接続端子面側のダイパッドパターン（図示せず）にてダイパッド（図示せず）と連結されている。   The semiconductor element mounting substrate of the present invention is characterized in that the semiconductor element 8 and the semiconductor element mounting surface side as shown in the plan view showing the dummy pad arrangement and shape around the semiconductor element of the semiconductor package substrate of FIG. For example, dummy terminals 21 having an arbitrary size and shape as shown in FIGS. 6A to 6C are patterned so as to surround the semiconductor element 8 at regular intervals between bonding pads (not shown). The dummy terminals 21 arranged in a pattern are connected to a die pad (not shown) by a die pad pattern (not shown) on the external connection terminal surface side.

図６のような構造を採ることにより、図３に示すように樹脂封止後のダイパッドの封止樹脂に対するモールドロック力は、半導体素子搭載パッド１ａのモールドロック形状に加えて、その半導体搭載パッド外周部のダイパッド１ｂの領域にパターン状に設けたダミー端子２１のモールドロック形状も半導体素子８と封止樹脂１１との密着性に寄与させることで、封止樹脂からの半導体素子の脱落を防止できる基板構造であり、半導体素子搭載パッド１ａとダミー端子２１が形成する凹部２１ａに、封止樹脂１１が充填された半導体パッケージ２０ａとなっている。   By adopting the structure as shown in FIG. 6, as shown in FIG. 3, the mold locking force of the die pad after resin sealing to the sealing resin is in addition to the mold lock shape of the semiconductor element mounting pad 1a, and the semiconductor mounting pad The mold lock shape of the dummy terminal 21 provided in a pattern in the region of the die pad 1b on the outer peripheral portion also contributes to the adhesion between the semiconductor element 8 and the sealing resin 11, thereby preventing the semiconductor element from falling off the sealing resin. The semiconductor package 20a is a semiconductor package 20a in which the recess 21a formed by the semiconductor element mounting pad 1a and the dummy terminal 21 is filled with the sealing resin 11.

また、図４に見られるようなダイパッド１ｂにモールドロック形状を持たないパッケージにおいても、その周囲にパターン状に設けたモールドロック形状のダミー端子２１及び内部接続端子２２を配置する事で、半導体素子８と封止樹脂１１との密着強度を改善し、封止樹脂からの半導体素子の脱落を防止できる基板構造となっている。
図３、図４において、８は半導体素子、１０はボンディングワイヤ、１１は封止樹脂、１２ａ、１２ｂは半導体素子搭載用基板、２０ａ、２０ｂは半導体パッケージ、２３はボンディングパッド、２４は外部接続端子である。 Further, even in a package that does not have a mold lock shape in the die pad 1b as shown in FIG. 4, by disposing a mold lock shape dummy terminal 21 and an internal connection terminal 22 provided in a pattern around the semiconductor device, 8 has a substrate structure that can improve the adhesion strength between the sealing resin 11 and the sealing resin 11 and prevent the semiconductor element from falling off the sealing resin.
3 and 4, 8 is a semiconductor element, 10 is a bonding wire, 11 is a sealing resin, 12a and 12b are semiconductor element mounting substrates, 20a and 20b are semiconductor packages, 23 is a bonding pad, and 24 is an external connection terminal. It is.

次に、本発明の実施の形態について説明する。
本発明の半導体素子搭載用基板は、板厚１００〜２００μｍの金属板表裏面に所定形状のめっき層を形成し、その表面側に形成しためっき層を覆うレジストマスクを形成し、裏面側はめっきのない部分、特に最終のエッチング時にエッチング速度の遅くなる部分が開口するようにレジストマスクを形成し、両面からハーフエッチング加工を行い、金属板の深さ方向に板を貫通しないように５０〜１００μｍ溶解除去して柱状部を形成するものである。 Next, an embodiment of the present invention will be described.
The substrate for mounting a semiconductor element of the present invention forms a plating layer having a predetermined shape on the front and back surfaces of a metal plate having a thickness of 100 to 200 μm, forms a resist mask covering the plating layer formed on the front surface side, and the back surface side is plated. A resist mask is formed so that there is an opening in a portion having no etching, particularly a portion where the etching rate becomes slow at the time of final etching, and half-etching processing is performed from both sides, and 50 to 100 μm so as not to penetrate the metal plate in the depth direction. The columnar part is formed by dissolution and removal.

金属板としては、一般に銅または銅合金が用いられ、通常のリードフレームで用いられている高強度のものが望ましく、また厚みはハンドリングなどを鑑み、通常１００〜２００μｍの範囲で選択されている。   As the metal plate, copper or a copper alloy is generally used, and a high-strength metal plate used in a normal lead frame is desirable. In view of handling and the like, the thickness is usually selected in the range of 100 to 200 μm.

次に、その製造方法について図５−１、図５−２を参照しながら説明する。
図５−１（１）に示すように、金属板１の両面にドライフィルムレジスト２をラミネートする。
使用するドライフィルムレジスト２の種類、厚みは特に限定されないが、通常感光部が硬化するネガタイプのものを用いる。この他にポジタイプのドライフィルムレジストでも良い。また液状のフォトレジストを塗布することでも良い。
レジストの厚みは、形成するパターンの線幅・線間距離で決定されるが、１５〜４０μｍの範囲を用いることが多い。 Next, the manufacturing method will be described with reference to FIGS.
As shown in FIG. 5A (1), a dry film resist 2 is laminated on both surfaces of the metal plate 1.
The type and thickness of the dry film resist 2 to be used are not particularly limited, but a negative type resist that usually cures the photosensitive portion is used. In addition, a positive type dry film resist may be used. Alternatively, a liquid photoresist may be applied.
The thickness of the resist is determined by the line width and distance between the patterns to be formed, but a range of 15 to 40 μm is often used.

次に、図５−１（２）に示すように、金属板１の両面に所定形状の開口部３が形成されためっき用のレジストマスク２ａを形成する。
先ずドライフィルムレジストに、所定位置で所定形状のめっきを形成するためのパターンを露光する。
露光マスクは、ダイパッド部周囲に樹脂封止後の密着向上のためのモールドロック用の任意形状のダミー端子パターンが配された露光マスクを使用する。
モールドロック用の任意形状のダミー端子上面部にめっきが不要な場合は本工程で使用する露光マスクにモールドロック用の任意形状のダミー端子パターンは不要である。 Next, as shown in FIG. 5A (2), a resist mask 2a for plating in which openings 3 having a predetermined shape are formed on both surfaces of the metal plate 1 is formed.
First, a dry film resist is exposed to a pattern for forming a predetermined shape of plating at a predetermined position.
As the exposure mask, an exposure mask in which a dummy terminal pattern of an arbitrary shape for mold lock for improving adhesion after resin sealing is arranged around the die pad portion is used.
If plating is not required on the upper surface of the dummy terminal having an arbitrary shape for mold lock, an arbitrary shape dummy terminal pattern for mold lock is not required for the exposure mask used in this step.

露光は、一般的な方法で行われる。
先ず、ドライフィルムレジストにパターンを形成したフォトマスクを密着させ、紫外線を照射することでフォトマスクのパターンをドライフィルムレジストに露光する。
照射量は２０〜１００ｍＪ／ｃｍ２程度である。このとき、半導体素子が搭載される面側となる表面側と反対側の外部接続端子となる裏面側が区別される。 The exposure is performed by a general method.
First, a photomask having a pattern formed thereon is brought into close contact with the dry film resist, and the pattern of the photomask is exposed to the dry film resist by irradiating with ultraviolet rays.
The irradiation amount is about 20 to 100 mJ / cm 2 . At this time, the rear surface side which is the external connection terminal on the opposite side to the front surface side which is the surface side on which the semiconductor element is mounted is distinguished.

露光後、現像する。現像には、アルカリ現像型のフォトレジストを用いる場合は通常１％程度の濃度の炭酸ナトリウムを用いる。
このようにして金属板１の両面に所定形状の開口部３が形成されためっき用のレジストマスク２ａが形成される。 Develop after exposure. For the development, when an alkali development type photoresist is used, sodium carbonate having a concentration of about 1% is usually used.
In this way, a resist mask 2a for plating in which openings 3 having a predetermined shape are formed on both surfaces of the metal plate 1 is formed.

次に図５−１（３）に示すように、レジストマスク２ａの開口部３に、めっきを行なう。
めっきの金属は、耐熱性、半導体素子との接続のためのワイヤボンディング性、およびプリント基板実装時の半田ぬれ性などで適宜選択される。
通常は電気めっきで、Ｎｉ、Ｐｄ、Ａｕ、Ａｇのいずれか、若しくは積層となるようにめっきして、めっき層４を形成する。 Next, as shown in FIG. 5A (3), the opening 3 of the resist mask 2a is plated.
The metal for plating is appropriately selected depending on heat resistance, wire bonding property for connection with a semiconductor element, solder wettability when mounted on a printed circuit board, and the like.
Usually, the plating layer 4 is formed by electroplating so as to be any one of Ni, Pd, Au, Ag, or a laminated layer.

その後、レジストマスクを剥離する。
剥離には、アルカリ現像型のフォトレジストを用いている場合は通常４％程度の濃度の水酸化ナトリウムを用いる。
この工程は予めボンディング性や実装性向上のためにめっきが必要な場合に適用するが、エッチング後にめっきする場合、もしくはめっきが必要ない場合は省略しても良い。 Thereafter, the resist mask is peeled off.
For stripping, when an alkali development type photoresist is used, sodium hydroxide having a concentration of about 4% is usually used.
This step is applied in advance when plating is necessary for improving bonding properties and mountability, but may be omitted when plating is performed after etching or when plating is not necessary.

次に図５−１（４）に示すように、表面側は形成しためっき層４より大きなレジストマスク５を形成し、反対面の裏面側は、全面を覆うようにレジストマスク６を形成する
このレジストマスク形成のための露光マスクは、ダイパッド部周囲に樹脂封止後の密着向上のためのモールドロック用任意形状のダミー端子パターンが配された露光マスクを使用する。この方法は前述のラミネート、露光、現像と同様である。
そして、ハーフエッチング処理の後に端子上端部にめっきのバリが出来ないように、エッチング量や露光の位置ズレを考慮した上でめっきより大きいレジストを形成する。 Next, as shown in FIG. 5A (4), a resist mask 5 larger than the formed plating layer 4 is formed on the front surface side, and a resist mask 6 is formed so as to cover the entire back surface side of the opposite surface. As an exposure mask for forming a resist mask, an exposure mask is used in which a dummy terminal pattern having an arbitrary shape for mold lock is provided around the die pad portion to improve adhesion after resin sealing. This method is the same as the above-described lamination, exposure, and development.
Then, a resist larger than the plating is formed in consideration of the etching amount and the positional deviation of the exposure so that the burrs of the plating cannot be formed at the upper end portion of the terminal after the half etching process.

次に図５−１（５）に示すように、表面側のレジストマスク開口部５ａからハーフエッチングを行ない、モールドロック形状の柱状部７を形成する。
エッチング液は、エッチング抑制剤を含んだエッチング液を用いても良い。このエッチング抑制剤としては、例えばアゾール系化合物が挙げられる。
なお、柱状部７のモールドロック形状とは、図３、４のダミー端子２１、内部接続端子２２に示されるような漏斗状の上部が末広がりの形状が望ましい。 Next, as shown in FIG. 5A (5), half-etching is performed from the resist mask opening 5a on the front surface side to form a columnar portion 7 having a mold lock shape.
As the etching solution, an etching solution containing an etching inhibitor may be used. Examples of the etching inhibitor include azole compounds.
The mold lock shape of the columnar portion 7 is preferably a shape in which the funnel-shaped upper portion is widened as shown by the dummy terminal 21 and the internal connection terminal 22 in FIGS.

次に図５−２（６）に示すように、表裏のレジストマスクを剥離することで半導体素子搭載用基板１２が得られる。ここで、７ａ、７ｃ、９は、半導体素子搭載用基板において、それぞれ内部接続端子、外部接続端子、ダイパッド部に設けられたモールドロック形状のダミー端子である。
この得られた半導体素子搭載用基板１２の表面側に半導体素子８を、ダイペースト等を介して搭載し、半導体素子８とモールドロック形状の内部接続端子７ａの端子部（ボンディングパッド７ｂ）をボンディングワイヤ１０によりワイヤボンディングする。
使用するダイペーストは、銀ペーストが用いられることが多く、ワイヤボンディングは、金ワイヤや銅ワイヤなどの直径２０〜４０μｍの太さのワイヤが用いられる。また半導体素子８と内部接続端子７ａとの接続はいわゆるフリップチップでも良い。
そして、次にエポキシ樹脂等の封止樹脂１１を用いて金属材の表面側を樹脂封止する（図５−２（７）参照）。 Next, as shown in FIG. 5-2 (6), the semiconductor element mounting substrate 12 is obtained by peeling the front and back resist masks. Here, 7a, 7c, and 9 are mold lock-shaped dummy terminals provided in the internal connection terminal, the external connection terminal, and the die pad portion, respectively, in the semiconductor element mounting substrate.
The semiconductor element 8 is mounted on the surface side of the obtained semiconductor element mounting substrate 12 via die paste or the like, and the semiconductor element 8 and the terminal portion (bonding pad 7b) of the mold-lock-shaped internal connection terminal 7a are bonded. Wire bonding is performed by the wire 10.
A silver paste is often used as the die paste to be used, and a wire having a diameter of 20 to 40 μm, such as a gold wire or a copper wire, is used for wire bonding. The connection between the semiconductor element 8 and the internal connection terminal 7a may be a so-called flip chip.
Then, the surface side of the metal material is resin-sealed using a sealing resin 11 such as an epoxy resin (see FIG. 5-2 (7)).

樹脂封止後、図５−２（８）に示すように、裏面側に形成しためっきをエッチングマスクとして用い、金属材をエッチング加工して、モールドロック形状の内部接続端子７ａ、ダミー端子９、外部接続端子７ｃの端子部を分離独立させる。
そして、ダイシングなどの方法で個々のパッケージサイズに切断する。
このようにして、ダイパッド部と封止樹脂との密着力が強固な半導体パッケージ２０を得る。 After resin sealing, as shown in FIG. 5-2 (8), using the plating formed on the back side as an etching mask, the metal material is etched to form mold-locked internal connection terminals 7a, dummy terminals 9, The terminal portion of the external connection terminal 7c is separated and independent.
Then, it is cut into individual package sizes by a method such as dicing.
In this manner, the semiconductor package 20 having a strong adhesion between the die pad portion and the sealing resin is obtained.

本発明の半導体素子搭載用基板を、図５−１及び図５−２の製造工程フロー図に従って製造した。
先ず、金属板１に、板厚０．１２５ｍｍの銅系合金材（古河電気工業株式会社製：ＥＦＴＥＣ６４−Ｔ）を用い、その両面にドライフィルムレジスト２（旭化成イーマテリアルズ株式会社製：ＡＱ−２５５８）をラミネートした（図５−１（１）参照）。 The substrate for mounting a semiconductor element of the present invention was manufactured according to the manufacturing process flow charts of FIGS.
First, a copper-based alloy material (Furukawa Electric Co., Ltd .: EFTEC64-T) having a thickness of 0.125 mm is used for the metal plate 1, and dry film resist 2 (Asahi Kasei E-Materials Co., Ltd .: AQ- is used on both sides thereof. 2558) was laminated (see FIG. 5-1 (1)).

ラミネート後、所定パターンで両面に露光、現像を行い、めっきが必要な部分が開口されたレジストマスク２ａを形成した（図５−１（２）参照）。
次に、形成したレジストマスク２ａの開口部３から露出している金属板１に、Ｎｉを厚み１μｍ、Ｐｄを厚み０．０７μｍ、Ａｕを厚み０．００３μｍの順でめっきして、めっき層４を形成する（図５−１（３）参照）。 After laminating, exposure and development were performed on both sides with a predetermined pattern to form a resist mask 2a in which a portion requiring plating was opened (see FIG. 5-1 (2)).
Next, the metal plate 1 exposed from the opening 3 of the formed resist mask 2a is plated with Ni having a thickness of 1 μm, Pd having a thickness of 0.07 μm, and Au having a thickness of 0.003 μm in this order. (See FIG. 5-1 (3)).

次に、レジストマスク２ａを剥離し、めっき層４が形成された金属板１の両面に、前記と同じドライフィルムレジストをラミネートし、半導体素子８が搭載される表面側は、形成しためっき層４より５０μｍ大きいパターンで露光し現像を行い、めっき層より５０μｍ大きいレジストマスク５を形成した。
そして、反対面の裏面側は、裏面全面を保護するレジストマスク６を形成した（図５−１（４）参照）。 Next, the resist mask 2a is peeled off, the same dry film resist as described above is laminated on both surfaces of the metal plate 1 on which the plating layer 4 is formed, and the surface side on which the semiconductor element 8 is mounted is formed on the formed plating layer 4 The resist mask 5 was exposed and developed with a pattern larger by 50 μm, and a resist mask 5 larger by 50 μm than the plating layer was formed.
And the resist mask 6 which protects the back surface whole surface was formed in the back surface side of an other surface (refer FIG. 5-1 (4)).

次に、液温４０℃のエッチング液を用いて、スプレー圧０．１〜０．２ＭＰａで３分間エッチング加工を行い、表面側から約８０μｍの深さまでハーフエッチングを行い、柱状部７を形成した（図５−１（５）参照）。
その後、両面のレジストマスク５、６を剥離することで半導体素子搭載用基板１２が得られた（図５−２（６）参照）。 Next, using an etching solution with a liquid temperature of 40 ° C., etching was performed for 3 minutes at a spray pressure of 0.1 to 0.2 MPa, and half-etching was performed from the surface side to a depth of about 80 μm to form the columnar portion 7. (See FIG. 5-1 (5)).
Thereafter, the resist masks 5 and 6 on both sides were peeled off to obtain a semiconductor element mounting substrate 12 (see FIG. 5-2 (6)).

得られた基板１２に、銀ペーストを用いて半導体素子８を搭載し、直径２０μｍの金のボンディングワイヤ１０を用いて、半導体素子８と内部接続端子７ａの端子部のボンディングパッド７ｂを接続し、エポキシ系の封止樹脂を用い樹脂封止１１をした（図５−２（７）参照）。
樹脂封止後、アルカリ性の銅エッチング液でエッチングした(図５−２（８）参照)。
その後、ダイシング工程にて個々のパッケージサイズに裁断し、半導体パッケージを得た。 The semiconductor element 8 is mounted on the obtained substrate 12 using a silver paste, and the bonding pad 7b of the terminal portion of the internal connection terminal 7a is connected to the semiconductor element 8 using a gold bonding wire 10 having a diameter of 20 μm. Resin sealing 11 was performed using an epoxy-based sealing resin (see FIG. 5-2 (7)).
After the resin sealing, etching was performed with an alkaline copper etchant (see FIG. 5-2 (8)).
Then, it cut | judged to each package size at the dicing process, and obtained the semiconductor package.

本パッケージの組み立て後の端子密着強度確認試験において、ダイパッドの剥がれ、脱落は発生しなかった。   In the terminal adhesion strength confirmation test after the assembly of this package, the die pad was not peeled off or dropped off.

（比較例１）
一方比較例１として、ダイパッド周辺にモールドロック用のダミー端子を有しない基板を用いて組み立てたパッケージにおける端子密着性強度確認試験において、一部の製品にてダイパッドの封止樹脂からの抜けが確認された。 (Comparative Example 1)
On the other hand, as Comparative Example 1, in a terminal adhesion strength confirmation test in a package assembled using a substrate that does not have a mold lock dummy terminal around the die pad, it was confirmed that the die pad was not detached from the sealing resin in some products. It was done.

１ 金属板
１ａ 半導体素子搭載パッド
１ｂ ダイパッド
２ ドライフィルムレジスト
２ａ めっき用レジストマスク
３ めっきレジストマスク開口部
４ めっき層
５、６ レジストマスク
５ａ レジストマスク開口部
７ 柱状部
７ａ 内部接続端子
７ｂ ボンディングパッド
７ｃ 外部接続端子
８ 半導体素子
９ ダイパッド部に設けられたモールドロック形状のダミー端子
１０ ボンディングワイヤ
１１ 封止樹脂
１２、１２ａ、１２ｂ 半導体素子搭載用基板
２０、２０ａ、２０ｂ、４０ａ、４０ｂ 半導体パッケージ
２１ ダミー端子
２１ａ 凹部
２２ 内部接続端子
２３ ボンディングパッド
２４ 外部接続端子
３２ａ、３２ｂ 半導体素子搭載用基板
４１ａ 半導体素子搭載パッド
４１ｂ ダイパッド
４２ 接続端子
４３ ボンディングパッド
４４ 外部接続端子部 DESCRIPTION OF SYMBOLS 1 Metal plate 1a Semiconductor element mounting pad 1b Die pad 2 Dry film resist 2a Plating resist mask 3 Plating resist mask opening part 4 Plating layer 5, 6 Resist mask 5a Resist mask opening part 7 Columnar part 7a Internal connection terminal 7b Bonding pad 7c External Connection terminal 8 Semiconductor element 9 Mold lock-shaped dummy terminal 10 provided in the die pad portion Bonding wire 11 Sealing resin 12, 12a, 12b Semiconductor element mounting substrate 20, 20a, 20b, 40a, 40b Semiconductor package 21 Dummy terminal 21a Recess 22 Internal connection terminal 23 Bonding pad 24 External connection terminals 32a and 32b Semiconductor element mounting substrate 41a Semiconductor element mounting pad 41b Die pad 42 Connection terminal 43 Bonding pad 44 External connection end Part

Claims (3)

金属板の片面側からハーフエッチング加工を行い、柱状部形状の端子を形成する半導体素子搭載用基板において、
前記柱状部形状の端子が、漏斗状の上部が末広がりの形状で、且つ平面形状が円形もしくは角部が円弧で形成された矩形であり、
半導体素子を搭載するパッド部に、前記柱状部形状のダミー端子を有することを特徴とする半導体素子搭載用基板。 In the semiconductor element mounting substrate that performs half-etching from one side of the metal plate and forms the columnar shaped terminal,
The columnar-shaped terminal is a funnel-shaped upper portion having a divergent shape, and a planar shape is a circle or a rectangle having a corner formed by an arc,
A semiconductor element mounting substrate, wherein the pad portion on which the semiconductor element is mounted has the columnar portion-shaped dummy terminal. 前記柱状部形状のダミー端子が、前記半導体素子を外囲する配置で設けられ、前記パッド部と連結されていることを特徴とする請求項１に記載の半導体素子搭載用基板。 2. The semiconductor element mounting substrate according to claim 1, wherein the columnar portion-shaped dummy terminals are provided so as to surround the semiconductor element, and are connected to the pad portion. 半導体素子搭載側から半導体素子用搭載基板のパッド部に、柱状部形状のダミー端子を形成するハーフエッチング加工が施され、前記ハーフエッチング加工された凹部位に封止樹脂が充填されていることを特徴とする半導体装置。 A half-etching process for forming a column-shaped dummy terminal is applied from the semiconductor element mounting side to the pad part of the semiconductor element mounting substrate, and a sealing resin is filled in the half-etched recessed portion. A featured semiconductor device.
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