TWI650051B - Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component - Google Patents

Abstract

The invention includes a first layer (100) and a second layer (200) on one side of the first layer (100). The first layer (100) includes a plurality of first conductor portions (6) and a resin portion (3) disposed between the plurality of first conductor portions (6) and electrically separating the plurality of first conductor portions (6). The second layer (200) includes a plurality of second conductor portions (4), which are connected to each of the plurality of first conductor portions (6) and are electrically separated from each other. The plurality of second conductor portions (4) are respectively connected to the resin portion (3) on a part of the surface on the side of the first layer (100) of the second conductor portion (4).

Description

Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component

The present invention relates to a wiring substrate, a method for manufacturing a wiring substrate, an electronic component, and a method for manufacturing an electronic component.

For example, Non-Patent Document 1 discloses an assembly process of a QFN using a QFN (Quad Flat Non-Leaded Package) assembly tape. In addition, QFN is not a structure in which lead terminals extend to the outside, and is one of non-lead type electronic components. Non-lead-type electronic components are called SON except QFN.

Non-Patent Document 1: Kawai Ki'an, Minger Yeyouhong, "Assembly Tape for QFN", Hitachi Chemical Technology Report, Hitachi Chemical Industry Co., Ltd., July 2002, No. 39, pages 17-20

However, compared with the conventional QFN, it is still desired to easily manufacture high-quality electronic components.

The embodiment disclosed herein includes a first layer and a second layer on one side of the first layer. The first layer includes a plurality of first conductor portions and is disposed on the first layer. The resin portions of the plurality of first conductor portions are electrically separated between the plurality of first conductor portions, and the second layer includes a plurality of second conductor portions that are connected to each of the plurality of first conductor portions and are electrically separated from each other. The plurality of second conductor portions are wiring boards connected to the resin portion on a part of the surface on the first layer side of the second conductor portion, respectively.

The embodiment disclosed herein is a method for manufacturing a wiring substrate, which includes the following processes: removing a part of a resin substrate of a laminated structure including a resin substrate and a conductor layer on the resin substrate; and removing the conductor layer A part of the resin substrate is connected to a part of the resin substrate, and is electrically separated from each other to form a plurality of second conductor portions; and a portion of the resin substrate has been removed to form a plurality of first conductor portions, the first conductor portion and the Each of the plurality of second conductor portions is connected and electrically separated from each other.

The embodiments disclosed herein include the above-mentioned wiring substrate, the wafer on the second layer, leads electrically connected to the wafer, and a sealing material for sealing the wafer and the leads, and the wafer and a part of the plurality of second conductor portions. Bonding, the lead is an electronic component that electrically connects the chip and another portion of the plurality of second conductor portions.

The embodiment disclosed herein includes the following processes: preparing the above-mentioned wiring substrate; bonding a chip to a portion of the plurality of second conductor portions; electrically connecting the chip to another portion of the plurality of second conductor portions by leads; and The wafer and the lead are sealed with a sealing material.

According to the embodiments disclosed herein, compared with the conventional QFN, high-quality electronic components can be easily manufactured.

1,101,1001‧‧‧wiring board

3‧‧‧Resin Department

4‧‧‧Second Conductor

4a‧‧‧Chip joint

4b‧‧‧Wire bonding

5‧‧‧ opening

6‧‧‧ the first conductor

7‧‧‧ opening

8‧‧‧ metal layer

9‧‧‧ notch

10‧‧‧sealing material

11‧‧‧ Lead

12‧‧‧Chip

13‧‧‧ Adhesive Materials

18‧‧‧ protective film

40‧‧‧Frame

41‧‧‧QFN assembly tape

51‧‧‧Inner Lead

52‧‧‧Outer Lead

100‧‧‧ First floor

111‧‧‧ dotted line

180‧‧‧ protective film

200‧‧‧ second floor

300‧‧‧ resin substrate

400‧‧‧conductor layer

500‧‧‧ laminated structure

FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment.

FIG. 2 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

FIG. 3 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

FIG. 4 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

FIG. 5 is a schematic cross-sectional view of a modified example of the wiring substrate according to the embodiment.

Fig. 6 is a schematic cross-sectional view of an electronic component according to an embodiment.

FIG. 7 is a schematic cross-sectional view illustrating an example of a method of manufacturing an electronic component according to an embodiment.

FIG. 8 is a schematic cross-sectional view illustrating an example of a method of manufacturing an electronic component according to an embodiment.

FIG. 9 is a schematic cross-sectional view illustrating an example of a method for manufacturing an electronic component according to an embodiment.

FIG. 10 is a schematic plan view of a modified example of the wiring substrate according to the embodiment.

FIG. 11 is a schematic plan view of the electronic component according to the embodiment shown in FIG. 6. FIG.

FIG. 12 is a schematic plan view of a first layer of a wiring substrate used in the electronic component according to the embodiment of FIG. 6. FIG.

FIG. 13 is a schematic cross-sectional view for explaining the effect of the wiring substrate of the embodiment.

FIG. 14 is a model for explaining the effect of the wiring substrate of the implementation type. Sectional view.

FIG. 15 is a schematic cross-sectional view for explaining the effect of the wiring substrate of the embodiment.

FIG. 16 is a schematic cross-sectional view for explaining the effects of the wiring substrate and the electronic components in the embodiment.

Figures 17 (a1) to 17 (a3) are schematic cross-sectional views illustrating the manufacturing method of the lead frame in the conventional QFN, and Figures 17 (b1) to 17 (b5) are diagrams illustrating this embodiment. A schematic cross-sectional view of an example of a method for manufacturing a wiring board.

Figures 18 (a1) to 18 (a5) are schematic sectional views illustrating the assembly process of the conventional QFN. Figures 18 (b1), 18 (b2), 18 (b4), and 18 ( b5) The figure is a schematic cross-sectional view illustrating an example of a method for manufacturing an electronic component according to the embodiment.

Figures 19 (a6) to 19 (a8) are schematic cross-sectional views illustrating the assembly process of a conventional QFN, and Figures 18 (b1) and 18 (b8) are diagrams illustrating the manufacture of electronic components in this embodiment. A pattern cross-section of one example of the method.

The implementation modes will be described below. In addition, if the drawings used in the description of the implementation type have the same reference symbols, they represent the same or equivalent parts.

<Wiring board>

FIG. 1 is a schematic cross-sectional view of a wiring substrate according to an embodiment. As shown in FIG. 1, the wiring substrate 1 according to the embodiment includes a first layer 100 and a second layer 200 on one side of the first layer 100. The first layer 100 includes a plurality of first conductor portions 6 and a resin portion 3 between the plurality of first conductor portions 6. Adjacent first conductor portions 6 are arranged at intervals. A resin portion 3 is arranged at an interval between adjacent first conductor portions 6. Adjacent first conductor portions 6 have insulating resin portions 3 Electrically separated from each other.

The second layer 200 includes a plurality of second conductor portions 4, and adjacent second conductor portions 4 are disposed with the opening portions 5 opened. No element is arranged in the opening portion 5 between the adjacent second conductor portions 4, and a part of the resin portion 3 of the first layer 100 is exposed. The adjacent second conductor portions 4 are electrically separated from each other by the opening portion 5.

Each of the plurality of second conductor portions 4 is connected to each of the plurality of second conductor portions 4 opposite to each other, and is electrically connected. In addition, each of the plurality of second conductor portions 4 is connected to the resin portion 3 on a part of the surface on the side of the first layer 100 of the second conductor portion 4. In addition, an application example in which the wiring substrate 1 is applied to the wire bonding technology will be described below, but the wiring substrate 1 can also be applied to a flip chip bonding technology.

<Manufacturing method of wiring board>

An example of a manufacturing method of the wiring board 1 according to the embodiment will be described below with reference to the schematic sectional views of FIGS. 2 to 5. First, as shown in FIG. 2, a laminated structure 500 including an insulating resin substrate 300 and a conductive layer 400 provided on one surface of the resin substrate 300 is prepared. As the resin substrate 300, polyimide can be used, and as the conductor layer 400, copper can be used.

Next, as shown in FIG. 3, an opening 7 is formed by removing a part of the resin base material 300. Here, an opening 7 is formed in a region corresponding to the plurality of first conductor portions 6 shown in FIG. 1, and the resin base material 300 becomes the resin portion 3 shown in FIG. 1. A conductive layer 400 is exposed on the opening 7. A part of the resin base material 300 can be removed by a technique such as etching.

Next, as shown in FIG. 4, an opening 5 is formed by removing a part of the conductive layer 400. Here, the opening 5 makes the remaining conductive layer 400 A part is formed by being connected to a part of the resin base material 300. The removed portion of the conductive layer 400 becomes a plurality of second conductive portions 4 shown in FIG. 1. The removal of a part of the conductive layer 400 can be performed by a technique such as etching.

Next, a first conductor portion 6 is formed on the surface of each of the conductor layers 400 exposed at the openings 7 shown in FIG. 4 to produce a wiring board of the embodiment shown in FIG. 1. The first conductor portion 6 can be formed using a technique such as copper plating on the conductor layer 400.

As shown in the schematic sectional view of FIG. 5, it is preferable to form the metal layer 8 on the second conductor portion 4. The metal layer 8 can be formed by a technique such as plating a laminated body of nickel and gold on the second conductor portion 4. The metal layer 8 may be formed in order to improve the connectivity of the wire to be wire-bonded.

In addition, as shown in FIG. 5, the back surface of the first conductor portion 6 (the surface of the first conductor portion 6 opposite to the second conductor portion 4 side) is preferably subjected to an external connection treatment to form the protective film 18. . The protective film 18 can be formed, for example, by plating a layered body of nickel and gold or tin, or by covering the back surface of the first conductor portion 6 with an organic protective film. The formation of the protective film 18 can be used to improve solder wettability with respect to the back surface of the first conductor portion 6 and to suppress oxidation of the back surface of the first conductor portion 6.

<Electronic components>

FIG. 6 is a schematic cross-sectional view of an electronic component according to an embodiment. The plurality of second conductor portions 4 of the wiring substrate 101 of the embodiment used for the non-lead-type electronic component of the embodiment shown in FIG. 6 includes a wafer bonding portion (see FIG. Two conductor portions 4) and a wire bonding portion (second conductor portion 4 other than the second conductor portion 4 in the center of FIG. 6) for bonding the leads 11. In addition, in the following description, it will be described that one electronic component is mounted on one electronic component. The structure of the wafer, but the present invention can mount a plurality of wafers on one electronic component.

In other words, as shown in FIG. 6, the electronic component of the implementation type includes the wiring substrate 101 of the implementation type, and a plurality of second conductor portions 4 electrically connected to the wiring substrate 101 of the implementation type through a conductive adhesive material 13. One portion (the second conductor portion 4 in the center of FIG. 6) of the wafer 12, the electrode 12 and the plurality of second conductor portions 4 (the second conductor portion in the center of FIG. 6) are electrically connected to the electrodes of the wafer 12 through the metal layer 8. The lead 11 of the second conductor portion 4) other than 4 and an insulating sealing material 10 for sealing the lead 11 and the wafer 12. As the lead 11 and the wafer 12, a conventionally known lead and a wafer can be used, respectively. As the sealing material 10, epoxy resin or the like can be used. As the bonding material 13, any conductive material may be used, and silver paste may be used.

A notch 9 is provided between the wafer bonding portion and the wire bonding portion of the second conductor portion 4. In this way, by providing the notch 9 between the wafer bonding portion and the wire bonding portion, when bonding the wafer 12 using the bonding material 13, the bonding material 13 flowing to the outside of the wafer 12 can be prevented by the notch 9. The material can flow out to the outside through the notch 9 and then the material 13.

In addition, the shape of the notch 9 may be a shape that is non-electrically separated from the second conductive portion 4 in the center, as viewed from a plan view shown in a schematic plan view of FIG. 11 described later. With this shape, the notch 9 can be formed by the same procedure as that in which the opening 5 is formed by removing a part of the conductor layer 400 as described using FIG. 4. In addition, in the electronic component shown in FIG. 6, the wiring substrate 1 shown in FIG. 1 or FIG. 5 without the notch 9 may be used instead of the wiring substrate 101 in structure.

<Manufacturing method of electronic components>

An example of a method for manufacturing an electronic component according to an embodiment will be described below with reference to the schematic sectional views of FIGS. 7 to 9. First, the wiring substrate 101 shown in FIG. 6 is prepared. The wiring substrate 101 shown in FIG. 6 includes a metal layer 8 on the second conductor portion 4 as a wire bonding portion, and includes a protective film 18 on a back surface of the first conductor portion 6, and is bonded to a wafer of the second conductor portion 4. The recess 9 is provided between the portion and the wire bonding portion, and has the same structure as that of the wiring board 1 according to the embodiment shown in FIG. 1.

Next, as shown in FIG. 7, the wafer 12 is bonded through the second conductor portion 4 which is the wafer bonding portion of the wiring substrate 101 of the embodiment shown in FIG. 6 through the bonding material 13. Here, the wafer 12 is bonded to the second conductor portion 4 which is a wafer bonding portion between the two notches 9 facing each other.

Next, as shown in FIG. 8, the electrodes of the wafer 12 are electrically connected to the metal layer 8 on the second conductor portion 4 as a wire bonding portion by a wire bonding technique using a wire 11.

Thereafter, as shown in FIG. 9, the sealing member 10 is used to seal the wafer 12 and the lead 11, and thereby the electronic component of the embodiment shown in FIG. 6 can be manufactured.

In addition, the cross-sectional structure of the wiring substrate 101 of the embodiment shown in FIG. 6 may be as shown in the pattern plan view of the tenth embodiment, and it is preferable to use a plurality of wiring boards of the embodiment in which a plurality of embodiments are continuously arranged along the vertical direction and the horizontal direction, respectively. 1001, an electronic component according to the embodiment shown in FIG. 6 is manufactured. On the wiring substrate 1001 of the embodiment shown in FIG. 10, each square surrounded by a dotted line in FIG. 10 has the same structure as the wiring substrate 101 shown in FIG. The structure is repeatedly connected in the horizontal direction and the horizontal direction. In other words In other words, one of the squares enclosed by the dotted line in FIG. 10 is the same as every other square. At least the patterns of the first conductor portion 6 and the second conductor portion 4 are the same. The patterns repeatedly appear in the vertical direction and the horizontal direction, respectively. .

By using the wiring substrate 1001 shown in FIG. 10, the electronic component of the embodiment shown in FIG. 6 can be manufactured more efficiently. In other words, the wafer 12 is bonded to each of the plurality of second conductor portions 4 which are the wafer bonding portions of the wiring substrate 1001 shown in FIG. 10, and the leads 12 are used to pair the wafer 12 with the second conductor portion 4 which is a wire bonding portion. After the wire bonding is performed, a plurality of wafers 12 and leads 11 are assembled and sealed with a sealing material 10. After that, the wiring substrate 1001 is individually separated with the sealing material 10 and cut into individual electronic components, whereby a plurality of electronic components can be manufactured at one time.

FIG. 11 is a schematic plan view showing the electronic component according to the embodiment shown in FIG. 6. FIG. 12 is a schematic plan view of the first layer of the wiring board in a portion surrounded by a dotted line 111 in FIG. 11. The installation position of the wafer bonding portion 4a of the second conductor portion 4 of the electronic component according to the embodiment shown in FIG. 11 corresponds to the position surrounded by the dotted line 4a shown in FIG. The installation position of the wire bonding portion 4b of the second conductor portion 4 of the electronic component according to the embodiment shown in FIG. 11 corresponds to a position surrounded by a dotted line 4b shown in FIG. In addition, in FIG. 12, for convenience of explanation, only the installation position of one wire bonding portion 4 b is shown.

As shown in FIGS. 11 and 12, the die bonding portion 4 a and the wire bonding portion 4 b of the second conductor portion 4 of the electronic component according to the embodiment are connected to the first conductor portion 6 of the first layer of the wiring substrate, respectively, Also connected to the resin portion 3.

<Effects>

In this embodiment, a technique such as an etching method for the resin substrate 300 can be used. The portion of the first conductor portion 6 (the rectangular first conductor portion 6 disposed at the outer periphery of FIG. 12) is formed finely as a terminal. Therefore, compared with the conventional QFN, a narrower pitch (phase The interval between adjacent terminals is less than 0.4 mm) to form terminals. As a result, in this embodiment, compared with the conventional QFN, the number of terminals can be increased and multi-pitch can be obtained. Therefore, the non-lead type electronic component can be miniaturized and high-performance.

In addition, the wiring board of the implementation type is provided with a pattern corresponding to the inner lead 51 and the outer lead 52 shown in FIG. 11 by using a patterning technique, thereby making it possible to eliminate the need to bond the lead 11 to the outer lead 52. In this case, it is bonded to the wire bonding portion 4 b closer to the wafer 12. Thereby, since the length of the lead 11 can be shortened, the reliability of the wire bonding technology can be improved, and the non-lead type electronic component can be guided to high quality.

Further, as shown in the schematic sectional view of FIG. 13, if the resin portion 3 is located directly below the second conductor portion 4 as the wafer bonding portion, it is very difficult to release the heat emitted from the wafer 12 to the outside through the resin portion 3. . However, in this embodiment, as shown in FIG. 6, a first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wafer bonding portion. Therefore, in this embodiment, the heat emitted from the wafer 12 can be easily released to the outside through the second conductor portion 4 as the wafer bonding portion and the first conductor portion 6 directly below it. Therefore, at this point, High-quality electronic components.

In addition, as shown in FIGS. 13 to 15, if the opening 7 is located directly below the second conductor portion 4 as the wire bonding portion, when the wire 11 is wire-bonded, the second conductor is used as the wire bonding portion. The jointability of the portion 4 is reduced by the bouncing effect. However, in this embodiment, as shown in FIG. 16, A first conductor portion 6 connected to the second conductor portion 4 is provided directly below the second conductor portion 4 as a wire bonding portion. Therefore, the strength of the second conductor portion 4 can be reinforced by the first conductor portion 6 directly below the second conductor portion 4. Therefore, when the wire bonding of the lead 11 is performed, the suppression of the second conductor can also be suppressed. The bonding property due to the bouncing action of the portion 4 is reduced.

In addition, as shown in FIGS. 13 to 15, if the opening 7 is located directly below the second conductor portion 4 as the wire bonding portion, when the wire bonding of the lead 11 is performed, it is added to the first wire bonding portion. Damage to the two conductor portions 4 is increased. However, in this embodiment, as shown in FIG. 16, a first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wire bonding portion. Therefore, the strength of the second conductor portion 4 can be reinforced by the first conductor portion 6 directly below the second conductor portion 4. Therefore, when the wire bonding of the lead 11 is performed, the strength of the second conductor portion 4 can be reduced. damage.

In addition, as shown in FIGS. 13 to 15, if the opening 7 is located immediately below the second conductor portion 4 as the wire bonding portion, solder voids may occur when the electronic component is repackaged, which may cause poor packaging. . In addition, in order to make the opening 7 directly below the second conductor portion 4, when the secondary packaging is performed, the solder is detached from the opening 7 and a good fillet cannot be formed. However, in this embodiment, as shown in FIG. 6, the first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wire bonding portion. This prevents problems during secondary packaging.

Figs. 17 (a1) to 17 (a3) are schematic cross-sectional views illustrating a method for manufacturing a frame in a conventional QFN, and Figs. 17 (b1) to 17 (b5) illustrate the present embodiment. Of an example of a manufacturing method of a wiring board Pattern section view. The frame is also called a lead frame.

In the conventional QFN, after openings 5 are provided on a part of the frame 40 shown in FIG. 17 (a1) as shown in FIG. 17 (a2), as shown in FIG. 17 (a3), A metal layer 8 made of silver is formed on a part of the surface of 40. Therefore, on the conventional QFN, the surface of the frame 40 may be oxidized by exposure to the atmosphere, so that there is a problem that the life of the frame 40 becomes short. On the other hand, in this embodiment, as shown in FIG. 17 (b5), by covering the back surface of the first conductor portion 6 with the protective film 18, the first conductor can be effectively suppressed compared to the conventional QFN. The oxidation of the part 6. In addition, in the conventional QFN, when the opening portion 5 is provided as shown in FIG. 17 (a2), in order not to separate the constituent elements of the frame 40, a connecting portion for mechanical connection is formed on the frame 40. on.

In the conventional QFN, it is necessary to process the frame 40 with a thicker wiring substrate in a comparative embodiment. Since microfabrication is difficult, the number of terminals cannot be increased, and multi-pitch is limited. On the other hand, in this embodiment, the terminals can be formed by processing both the thinner resin substrate 300 and the conductive layer 400, so that finer processing is possible, so compared with conventional Known QFN can increase the number of terminals. In addition, Figs. 17 (b1) to 17 (b3) and 17 (b5) correspond to Figs. 2 to 5 respectively, and Fig. 17 (b4) corresponds to Fig. 1, so they are omitted here. Explanation of FIGS. 17 (b1) to 17 (b5).

Figures 18 (a1) to 18 (a5) and Figures 19 (a6) to 19 (a8) are schematic cross-sectional views illustrating the assembly process of the conventional QFN. Figures 18 (b1) Fig. 18 (b2), Fig. 18 (b4), Fig. 18 (b5), and Fig. 19 (b8) are schematic cross-sectional views illustrating an example of a method for manufacturing an electronic component according to this embodiment.

In addition, Figs. 18 (b1), 18 (b2), 18 (b4), and Figures 18 (b5) and 19 (b8) show the eighteenth (a1) and eighteenth (a2) drawings of the assembly process with the conventional QFN in the manufacturing process of an example of the manufacturing method of the electronic component of the implementation type. Figure, Figure 18 (a4), Figure 18 (a5), and Figure 19 (a8).

In the conventional QFN assembly process, as shown in FIG. 18 (a1), after the wafer 12 is bonded to the wafer 12 on the frame 40 through the bonding material 13, as shown in FIG. 18 (a2), the leads are then bonded. 11 Perform wire bonding technology. However, in the conventional QFN assembly process, the tip of the terminal is not fixed to another component, so there is a problem of poor jointability. On the other hand, in this embodiment, since a part of the second conductor portion 4 as the terminal is connected to the resin portion 3, the wire bonding situation is stable and the bondability is improved. Thereby, in this embodiment, a high-quality non-lead-type electronic component can be manufactured.

In the conventional QFN assembly process, as shown in FIG. 18 (a3), it is necessary to use a QFN assembly tape 41. On the other hand, in the present embodiment, it is not necessary to use the QFN assembly tape 41, so that the number of processes can be reduced, and the material cost equivalent to the cost of the QFN assembly tape 41 can be saved. Therefore, in this embodiment, compared with the conventional QFN assembly process, a non-lead electronic component can be manufactured with a simple process and low cost.

In the conventional QFN assembly process, as shown in FIG. 18 (a4), after the sealing process using the sealing material 10 is performed, the marking process for the sealing material 10 shown in FIG. 18 (a5) is performed. However, with the thin QFN assembly tape 41, there is a problem that the sealing resin is leaked during the sealing process shown in FIG. 18 (a4). On the other hand, in this embodiment mode, since the wiring substrate of the embodiment mode is included, such a problem does not occur.

In the conventional QFN assembly process, as shown in FIG. 19 (a6), It is shown that the QFN assembly tape 41 needs to be peeled from the frame 40, and as shown in FIG. 19 (a7), the back surface of the frame 40 is covered with a protective film 180 made of tin. On the other hand, in this embodiment mode, since these processes are not required, the number of processes can be reduced.

In the conventional QFN assembly process, as shown in FIG. 19 (a8), a process of slicing and individualizing each electronic component is performed, but the width of the slicing frame 40 is later widened, so one side is required The frame 40 is cut while being individualized. As a result, burrs may be generated at the cut portion of the frame 40, and the quality of electronic components may be poor. On the other hand, in this embodiment mode, fine processing of the first conductor portion 6 and the second conductor portion 4 is possible. Therefore, the widths of the first conductor portion 6 and the second conductor portion 4 that are cut off are variable. narrow. As a result, when each of the electronic components is individualized, the first conductor portion 6 and the second conductor portion 4 need not be cut, and the cutting is performed by pressing, so that the occurrence of burrs can be reduced. As a result, in this embodiment, a high-quality non-lead-type electronic component can be manufactured compared to a conventional QFN assembly process.

Explanation will be added here. In the conventional QFN, as described above, in order not to separate the constituent elements of the frame 40, a connecting portion for mechanical connection is provided on the frame 40. This connecting portion may be formed at a position corresponding to a portion shown by a dotted line in FIG. 10. In addition, in the manufacturing process of electronic components, a mechanical strength capable of preventing the constituent elements from being separated is required, so the width of the connecting portion is relatively wide. This relatively wide connecting portion can be cut by a cutting technique using a cutting blade, so burrs are easily generated. In addition, the life of consumables used in cutting technology such as a cutting blade is shortened.

On the other hand, in this embodiment, a connecting portion for mechanical connection is basically unnecessary. In addition, if the opening 7 described using FIG. 5 is formed, In the first conductor portion, electroplating technology is used. In order to electrically connect the plurality of conductor layers 400 that are portions of the lead 52 other than that shown in FIG. 11, the boundary portion and the peripheral portion of each wiring substrate 101 in FIG. A portion indicated by a dotted line in FIG. 10) forms a connection portion using the conductor layer 400. In this case, as long as the width of the connection portion can be conducted by plating, it may be narrower. Therefore, even if the narrow connection portion can be cut by a cutting technique using a cutting blade, compared with the conventional QFN, it is difficult to generate burrs. In addition, the life of consumables used for cutting tools such as cutting blades is longer than that of the conventional QFN.

As described above, according to this embodiment, the number of terminals can be increased compared to the conventional QFN. In addition, high-quality electronic components can be manufactured by a simpler process and lower cost than the conventional QFN. In addition, it is possible to easily manufacture electronic components of higher quality than the conventional QFN.

The embodiments have been described as described above, but an invention in which the structures of the above embodiments are appropriately combined is also in a range preset at the beginning.

The implementation form disclosed this time should not be limited by all the exemplified characteristics. The scope of the present invention is not disclosed by the above description, but is disclosed by the scope of patent application. The present invention is also intended to include all changes within the meaning and scope equivalent to the scope of patent application.

Claims (9)

A wiring substrate for manufacturing a QFN type electronic component, comprising: a first layer; and a second layer on one side of the first layer; wherein the first layer includes: a plurality of first conductor portions; and The resin portion is disposed between the plurality of first conductor portions and electrically separates the plurality of first conductor portions. The second layer includes: a plurality of second conductor portions, and each of the plurality of first conductor portions. Are connected and electrically separated from each other; the plurality of second conductor portions are respectively connected to the resin portion on a part of the side of the first layer side of the second conductor portion, and the second conductor portion includes: A wafer bonding portion for bonding a wafer; and a wire bonding portion for bonding a lead, wherein an area of the first conductor portion connecting the wafer bonding portion is larger than a wafer bonding area of the wafer bonding portion connecting the first conductor portion. A plurality of the wafer bonding portions are respectively arranged in two directions staggered with each other, and a plurality of the first conductor portions and the second conductor portion patterns are arranged. For example, the wiring board according to item 1 of the patent application scope, wherein the wire bonding portion further includes a metal layer. For example, the wiring board according to the first patent application scope further includes a protective film on a surface opposite to the second conductor portion side of the first conductor portion. A manufacturing method of a wiring substrate, which is used for manufacturing a wiring substrate for manufacturing a QFN type electronic component, and includes the following processes: removing a part of the resin substrate including a resin substrate and a laminated structure of a conductor layer on the resin substrate; Removing a portion of the conductive layer to form a plurality of second conductor portions connected to a portion of the resin substrate and electrically separated from each other; and forming a plurality of first portions on the portion of the resin substrate that has been removed A conductor portion, the first conductor portion is connected to each of the plurality of second conductor portions, and is electrically separated from each other; in the step of forming the second conductor portion, a wafer bonding portion for bonding a wafer is formed, and The wire bonding portions for bonding the leads are arranged in a plurality of mutually staggered directions, respectively, to form the pattern of the second conductor portion. In the step of forming the first conductor portion, the wafer bonding portions are connected. An area of the first conductor portion is larger than a wafer bonding area of the wafer bonding portion connected to the first conductor portion to form an upper surface A first conductor portion. For example, the manufacturing method of a wiring board according to the fourth item of the patent application, wherein a metal layer is formed on the second conductor portion. For example, the method for manufacturing a wiring board according to the scope of the patent application No. 5 further includes a process for performing external connection processing on at least a part of the plurality of first conductor portions. An electronic component includes: a wiring substrate according to any one of claims 1 to 3 of the scope of patent application; a wafer on the second layer; a lead wire electrically connected to the wafer; and a sealing material for sealing the wafer and the wafer. The lead; wherein the chip is bonded to a portion of the plurality of second conductor portions, and the lead is electrically connected to the chip and another portion of the plurality of second conductor portions. An electronic component manufacturing method includes the following processes: preparing a wiring substrate as in any one of claims 1 to 3 of the scope of patent application; bonding a chip to a part of the plurality of second conductor portions; and electrically connecting the above by a lead wire The chip and another portion of the plurality of second conductor portions; and sealing the chip and the lead with a sealing material. For example, the method for manufacturing an electronic component according to item 8 of the scope of the patent application further includes a process of cutting the wiring substrate to be individualized.