TWI650051B - Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component - Google Patents
Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component Download PDFInfo
- Publication number
- TWI650051B TWI650051B TW106111861A TW106111861A TWI650051B TW I650051 B TWI650051 B TW I650051B TW 106111861 A TW106111861 A TW 106111861A TW 106111861 A TW106111861 A TW 106111861A TW I650051 B TWI650051 B TW I650051B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductor
- wafer
- portions
- layer
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
本發明包括第一層(100)及第一層(100)之其中一面上的第二層(200)。第一層(100)包括複數個第一導體部(6)及配置於複數個第一導體部(6)之間且電性分離複數個第一導體部(6)的樹脂部(3)。第二層(200)包括複數個第二導體部(4),與複數個第一導體部(6)的每一個連接且相互電性分離。複數個第二導體部(4)分別在第二導體部(4)的第一層(100)那側的面的一部分上,與樹脂部(3)連接。 The invention includes a first layer (100) and a second layer (200) on one side of the first layer (100). The first layer (100) includes a plurality of first conductor portions (6) and a resin portion (3) disposed between the plurality of first conductor portions (6) and electrically separating the plurality of first conductor portions (6). The second layer (200) includes a plurality of second conductor portions (4), which are connected to each of the plurality of first conductor portions (6) and are electrically separated from each other. The plurality of second conductor portions (4) are respectively connected to the resin portion (3) on a part of the surface on the side of the first layer (100) of the second conductor portion (4).
Description
本發明是關於一種配線基板、配線基板之製造方法、電子元件以及電子元件之製造方法。 The present invention relates to a wiring substrate, a method for manufacturing a wiring substrate, an electronic component, and a method for manufacturing an electronic component.
例如,在非專利文獻1中,揭示使用一種QFN用(Quad Flat Non-Leaded Package,四方扁平非引線封裝)裝配膠帶的QFN之組裝製程。此外,QFN並非引線端子延伸至外側的構造,為非引線型的電子元件的其中一種。作為非引線型電子元件,在QFN以外都被稱為SON。 For example, Non-Patent Document 1 discloses an assembly process of a QFN using a QFN (Quad Flat Non-Leaded Package) assembly tape. In addition, QFN is not a structure in which lead terminals extend to the outside, and is one of non-lead type electronic components. Non-lead-type electronic components are called SON except QFN.
非專利文獻1:河合紀安、名兒耶友宏,"QFN用裝配膠帶",日立化成技術報告、日立化成工業株式會社,2002年7月,No.39,第17~20頁 Non-Patent Document 1: Kawai Ki'an, Minger Yeyouhong, "Assembly Tape for QFN", Hitachi Chemical Technology Report, Hitachi Chemical Industry Co., Ltd., July 2002, No. 39, pages 17-20
然而,相較於習知的QFN,還是希望能輕易製造出高品質的電子元件。 However, compared with the conventional QFN, it is still desired to easily manufacture high-quality electronic components.
在此所揭示的實施型態包括第一層及第一層的其中一面上的第二層,第一層包括複數個第一導體部及配置於複 數個第一導體部之間且電性分離複數個第一導體部的樹脂部,第二層包括複數個第二導體部,其與複數個第一導體部的每一個連接且相互電性分離,複數個第二導體部為分別在第二導體部的第一層側的面的一部分上與樹脂部連接的配線基板。 The embodiment disclosed herein includes a first layer and a second layer on one side of the first layer. The first layer includes a plurality of first conductor portions and is disposed on the first layer. The resin portions of the plurality of first conductor portions are electrically separated between the plurality of first conductor portions, and the second layer includes a plurality of second conductor portions that are connected to each of the plurality of first conductor portions and are electrically separated from each other. The plurality of second conductor portions are wiring boards connected to the resin portion on a part of the surface on the first layer side of the second conductor portion, respectively.
在此所揭示的實施型態為一種配線基板之製造方法,其包含下列製程:去除包括樹脂基材與樹脂基材上之導體層的積層構造體的樹脂基材的一部分;藉由去除導體層的一部分,與樹脂基材的一部分連接,並且,相互電性分離形成複數個第二導體部;及在樹脂基材已被去除的部分,形成複數個第一導體部,該第一導體部與複數個第二導體部的每一個連接,並且,相互電性分離。 The embodiment disclosed herein is a method for manufacturing a wiring substrate, which includes the following processes: removing a part of a resin substrate of a laminated structure including a resin substrate and a conductor layer on the resin substrate; and removing the conductor layer A part of the resin substrate is connected to a part of the resin substrate, and is electrically separated from each other to form a plurality of second conductor portions; and a portion of the resin substrate has been removed to form a plurality of first conductor portions, the first conductor portion and the Each of the plurality of second conductor portions is connected and electrically separated from each other.
在此所揭示的實施型態包括上述的配線基板、第二層上的晶片、電性連接至晶片的引線及用來密封晶片與上述引線的密封材料,晶片與複數個第二導體部的一部分接合,引線為電性連接晶片與複數個第二導體部的另一部分的電子元件。 The embodiments disclosed herein include the above-mentioned wiring substrate, the wafer on the second layer, leads electrically connected to the wafer, and a sealing material for sealing the wafer and the leads, and the wafer and a part of the plurality of second conductor portions. Bonding, the lead is an electronic component that electrically connects the chip and another portion of the plurality of second conductor portions.
在此所揭示的實施型態包括下列製程:準備上述之配線基板;在複數個第二導體部的一部分上接合晶片;藉由引線電性連接晶片與複數個第二導體部的另一部分;及藉由密封材料密封晶片與引線。 The embodiment disclosed herein includes the following processes: preparing the above-mentioned wiring substrate; bonding a chip to a portion of the plurality of second conductor portions; electrically connecting the chip to another portion of the plurality of second conductor portions by leads; and The wafer and the lead are sealed with a sealing material.
根據在此揭示的實施型態,相較於習知的QFN,可輕易製造出高品質的電子元件。 According to the embodiments disclosed herein, compared with the conventional QFN, high-quality electronic components can be easily manufactured.
1,101,1001‧‧‧配線基板 1,101,1001‧‧‧wiring board
3‧‧‧樹脂部 3‧‧‧Resin Department
4‧‧‧第二導體部 4‧‧‧Second Conductor
4a‧‧‧晶片接合部 4a‧‧‧Chip joint
4b‧‧‧引線接合部 4b‧‧‧Wire bonding
5‧‧‧開口部 5‧‧‧ opening
6‧‧‧第一導體部 6‧‧‧ the first conductor
7‧‧‧開口 7‧‧‧ opening
8‧‧‧金屬層 8‧‧‧ metal layer
9‧‧‧凹口 9‧‧‧ notch
10‧‧‧密封材料 10‧‧‧sealing material
11‧‧‧引線 11‧‧‧ Lead
12‧‧‧晶片 12‧‧‧Chip
13‧‧‧接著材料 13‧‧‧ Adhesive Materials
18‧‧‧保護膜 18‧‧‧ protective film
40‧‧‧框架 40‧‧‧Frame
41‧‧‧QFN用裝配膠帶 41‧‧‧QFN assembly tape
51‧‧‧內引線 51‧‧‧Inner Lead
52‧‧‧外引線 52‧‧‧Outer Lead
100‧‧‧第一層 100‧‧‧ First floor
111‧‧‧虛線 111‧‧‧ dotted line
180‧‧‧保護膜 180‧‧‧ protective film
200‧‧‧第二層 200‧‧‧ second floor
300‧‧‧樹脂基材 300‧‧‧ resin substrate
400‧‧‧導體層 400‧‧‧conductor layer
500‧‧‧積層構造體 500‧‧‧ laminated structure
第1圖為實施型態之配線基板的模式剖面圖。 FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment.
第2圖為圖解實施型態之配線基板之製造方法之一例的模式剖面圖。 FIG. 2 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.
第3圖為圖解實施型態之配線基板之製造方法之一例的模式剖面圖。 FIG. 3 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.
第4圖為圖解實施型態之配線基板之製造方法之一例的模式剖面圖。 FIG. 4 is a schematic cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.
第5圖為實施型態之配線基板之變型例的模式剖面圖。 FIG. 5 is a schematic cross-sectional view of a modified example of the wiring substrate according to the embodiment.
第6圖為實施型態之電子元件的模式剖面圖。 Fig. 6 is a schematic cross-sectional view of an electronic component according to an embodiment.
第7圖為圖解實施型態之電子元件之製造方法之一例的模式剖面圖。 FIG. 7 is a schematic cross-sectional view illustrating an example of a method of manufacturing an electronic component according to an embodiment.
第8圖為圖解實施型態之電子元件之製造方法之一例的模式剖面圖。 FIG. 8 is a schematic cross-sectional view illustrating an example of a method of manufacturing an electronic component according to an embodiment.
第9圖為圖解實施型態之電子元件之製造方法之一例的模式剖面圖。 FIG. 9 is a schematic cross-sectional view illustrating an example of a method for manufacturing an electronic component according to an embodiment.
第10圖為實施型態之配線基板之變形例的模式平面圖。 FIG. 10 is a schematic plan view of a modified example of the wiring substrate according to the embodiment.
第11圖為第6圖所示之實施型態之電子元件的模式平面圖。 FIG. 11 is a schematic plan view of the electronic component according to the embodiment shown in FIG. 6. FIG.
第12圖為第6圖之實施型態之電子元件所使用的配線基板之第一層的模式平面圖。 FIG. 12 is a schematic plan view of a first layer of a wiring substrate used in the electronic component according to the embodiment of FIG. 6. FIG.
第13圖為用來說明實施型態之配線基板之作用效果的模式剖面圖。 FIG. 13 is a schematic cross-sectional view for explaining the effect of the wiring substrate of the embodiment.
第14圖為用來說明實施型態之配線基板之作用效果的模 式剖面圖。 FIG. 14 is a model for explaining the effect of the wiring substrate of the implementation type. Sectional view.
第15圖為用來說明實施型態之配線基板之作用效果的模式剖面圖。 FIG. 15 is a schematic cross-sectional view for explaining the effect of the wiring substrate of the embodiment.
第16圖為用來說明實施型態之配線基板及電子元件之作用效果的模式剖面圖。 FIG. 16 is a schematic cross-sectional view for explaining the effects of the wiring substrate and the electronic components in the embodiment.
第17(a1)圖至第17(a3)圖為圖解習知之QFN中之引線框架之製造方法的模式剖面圖,第17(b1)圖至第17(b5)圖為圖解本實施型態之配線基板之製造方法之一例的模式剖面圖。 Figures 17 (a1) to 17 (a3) are schematic cross-sectional views illustrating the manufacturing method of the lead frame in the conventional QFN, and Figures 17 (b1) to 17 (b5) are diagrams illustrating this embodiment. A schematic cross-sectional view of an example of a method for manufacturing a wiring board.
第18(a1)圖至第18(a5)圖為圖解習知之QFN之組裝製程的模式剖面圖,第18(b1)圖、第18(b2)圖、第18(b4)圖及第18(b5)圖為圖解本實施型態之電子元件之製造方法之一例的模式剖面圖。 Figures 18 (a1) to 18 (a5) are schematic sectional views illustrating the assembly process of the conventional QFN. Figures 18 (b1), 18 (b2), 18 (b4), and 18 ( b5) The figure is a schematic cross-sectional view illustrating an example of a method for manufacturing an electronic component according to the embodiment.
第19(a6)圖至第19(a8)圖為圖解習知之QFN之組裝製程的模式剖面圖,第18(b1)圖、第18(b8)圖為圖解本實施型態之電子元件之製造方法之一例的模式剖面圖。 Figures 19 (a6) to 19 (a8) are schematic cross-sectional views illustrating the assembly process of a conventional QFN, and Figures 18 (b1) and 18 (b8) are diagrams illustrating the manufacture of electronic components in this embodiment. A pattern cross-section of one example of the method.
以下將說明實施型態。此外,實施型態之說明中所使用的圖面中若有同一參照符號,代表同一部分或相當部分。 The implementation modes will be described below. In addition, if the drawings used in the description of the implementation type have the same reference symbols, they represent the same or equivalent parts.
<配線基板> <Wiring board>
在第1圖中,表示實施型態之配線基板的模式剖面圖。如第1圖所示,實施型態之配線基板1包括第一層100及第一層100的其中一面上的第二層200。第一層100包括複數個第一導體部6及複數個第一導體部6之間的樹脂部3。相鄰的第一導體部6空出間隔而配置。在相鄰的第一導體部6之間的間隔配置有樹脂部3。相鄰的第一導體部6藉由絕緣性的樹脂部3 相互電性分離。 FIG. 1 is a schematic cross-sectional view of a wiring substrate according to an embodiment. As shown in FIG. 1, the wiring substrate 1 according to the embodiment includes a first layer 100 and a second layer 200 on one side of the first layer 100. The first layer 100 includes a plurality of first conductor portions 6 and a resin portion 3 between the plurality of first conductor portions 6. Adjacent first conductor portions 6 are arranged at intervals. A resin portion 3 is arranged at an interval between adjacent first conductor portions 6. Adjacent first conductor portions 6 have insulating resin portions 3 Electrically separated from each other.
第二層200包括複數個第二導體部4,相鄰的第二導體部4空出開口部5而配置。在相鄰的第二導體部4之間的開口部5上不配置元件,第一層100的樹脂部3的一部分露出。相鄰的第二導體部4藉由開口部5,相互電性分離。 The second layer 200 includes a plurality of second conductor portions 4, and adjacent second conductor portions 4 are disposed with the opening portions 5 opened. No element is arranged in the opening portion 5 between the adjacent second conductor portions 4, and a part of the resin portion 3 of the first layer 100 is exposed. The adjacent second conductor portions 4 are electrically separated from each other by the opening portion 5.
複數個第二導體部4的每一個與與之相向的複數個第二導體部4的每一個連接,且電性連接。又,複數個第二導體部4的每一個在第二導體部4的第一層100那側的面的一部分上與樹脂部3連接。此外,以下將說明將配線基板1應用於打線接合技術的應用例,但配線基板1也可應用於倒裝晶片接合技術。 Each of the plurality of second conductor portions 4 is connected to each of the plurality of second conductor portions 4 opposite to each other, and is electrically connected. In addition, each of the plurality of second conductor portions 4 is connected to the resin portion 3 on a part of the surface on the side of the first layer 100 of the second conductor portion 4. In addition, an application example in which the wiring substrate 1 is applied to the wire bonding technology will be described below, but the wiring substrate 1 can also be applied to a flip chip bonding technology.
<配線基板之製造方法> <Manufacturing method of wiring board>
以下將參照第2圖至第5圖的模式剖面圖,說明實施型態之配線基板1之製造方法之一例。首先,如第2圖所示,準備包括絕緣性之樹脂基材300且在樹脂基材300之其中一面上具備導體層400的積層構造體500。作為樹脂基材300,可採用聚酰亞胺,作為導體層400,可採用銅。 An example of a manufacturing method of the wiring board 1 according to the embodiment will be described below with reference to the schematic sectional views of FIGS. 2 to 5. First, as shown in FIG. 2, a laminated structure 500 including an insulating resin substrate 300 and a conductive layer 400 provided on one surface of the resin substrate 300 is prepared. As the resin substrate 300, polyimide can be used, and as the conductor layer 400, copper can be used.
接著,如第3圖所示,藉由去除樹脂基材300的一部分,形成開口7。在此,在對應於第1圖所示之複數個第一導體部6所被配置的區域形成開口7,樹脂基材300成為第1圖所示的樹脂部3。開口7上有導體層400露出。樹脂基材300的一部分的去除可藉由例如蝕刻等技術來進行。 Next, as shown in FIG. 3, an opening 7 is formed by removing a part of the resin base material 300. Here, an opening 7 is formed in a region corresponding to the plurality of first conductor portions 6 shown in FIG. 1, and the resin base material 300 becomes the resin portion 3 shown in FIG. 1. A conductive layer 400 is exposed on the opening 7. A part of the resin base material 300 can be removed by a technique such as etching.
接著,如第4圖所示,藉由去除導體層400的一部分,形成開口部5。在此,開口部5使剩餘的導體層400的 一部分與樹脂基材300的一部分連接而形成。導體層400被去除的部分成為第1圖所示的複數個第二導體部4。導體層400的一部分的去除可藉由例如蝕刻等技術來進行。 Next, as shown in FIG. 4, an opening 5 is formed by removing a part of the conductive layer 400. Here, the opening 5 makes the remaining conductive layer 400 A part is formed by being connected to a part of the resin base material 300. The removed portion of the conductive layer 400 becomes a plurality of second conductive portions 4 shown in FIG. 1. The removal of a part of the conductive layer 400 can be performed by a technique such as etching.
接著,藉由在第4圖所示之開口7所在之處露出的導體層400的每一個的表面上形成第一導體部6,製造出第1圖所示的實施型態之配線基板。第一導體部6可使用將銅電鍍於導體層400上等技術來形成。 Next, a first conductor portion 6 is formed on the surface of each of the conductor layers 400 exposed at the openings 7 shown in FIG. 4 to produce a wiring board of the embodiment shown in FIG. 1. The first conductor portion 6 can be formed using a technique such as copper plating on the conductor layer 400.
又,如第5圖的模式剖面圖所示,宜在第二導體部4上形成金屬層8。金屬層8可藉由將鎳與金的積層體鍍於第二導體部4上等技術來形成。金屬層8可為了提高被打線接合的引線的連接性而形成。 As shown in the schematic sectional view of FIG. 5, it is preferable to form the metal layer 8 on the second conductor portion 4. The metal layer 8 can be formed by a technique such as plating a laminated body of nickel and gold on the second conductor portion 4. The metal layer 8 may be formed in order to improve the connectivity of the wire to be wire-bonded.
又,如第5圖所示,宜對第一導體部6的背面(第一導體部6與第二導體部4那側相反的那側的面)施以外部連接用處理以形成保護膜18。保護膜18例如,可藉由電鍍鎳和金的積層體或錫,或藉由使用有機保護膜被覆第一導體部6的背面來形成。保護膜18的形成可用來提高針對第一導體部6背面的焊料潤濕性並且或者抑制第一導體部6背面的氧化。 In addition, as shown in FIG. 5, the back surface of the first conductor portion 6 (the surface of the first conductor portion 6 opposite to the second conductor portion 4 side) is preferably subjected to an external connection treatment to form the protective film 18. . The protective film 18 can be formed, for example, by plating a layered body of nickel and gold or tin, or by covering the back surface of the first conductor portion 6 with an organic protective film. The formation of the protective film 18 can be used to improve solder wettability with respect to the back surface of the first conductor portion 6 and to suppress oxidation of the back surface of the first conductor portion 6.
<電子元件> <Electronic components>
在第6圖中,表示實施型態之電子元件的模式剖面圖。第6圖所示的實施型態之非引線型電子元件所使用的實施型態之配線基板101的複數個第二導體部4包括用來接合晶片12的晶片接合部(第6圖中央的第二導體部4)及用來接合引線11的引線接合部(第6圖中央的第二導體部4以外的第二導體部4)。此外,在以下的說明中,雖然將說明在1個電子元件上搭載1個 晶片的構造,但本發明可在1個電子元件上搭載複數個晶片。 FIG. 6 is a schematic cross-sectional view of an electronic component according to an embodiment. The plurality of second conductor portions 4 of the wiring substrate 101 of the embodiment used for the non-lead-type electronic component of the embodiment shown in FIG. 6 includes a wafer bonding portion (see FIG. Two conductor portions 4) and a wire bonding portion (second conductor portion 4 other than the second conductor portion 4 in the center of FIG. 6) for bonding the leads 11. In addition, in the following description, it will be described that one electronic component is mounted on one electronic component. The structure of the wafer, but the present invention can mount a plurality of wafers on one electronic component.
換言之,如第6圖所示,實施型態之電子元件包括實施型態之配線基板101、透過導電性的接著材料13電性連接至實施型態之配線基板101之複數個第二導體部4之一部分(第6圖中央的第二導體部4)的晶片12、透過金屬層8電性連接晶片12之電極和複數個第二導體部4的另一部分(第6圖中央的第二導體部4以外的第二導體部4)的引線11、用來密封引線11及晶片12的絕緣性密封材料10。作為引線11及晶片12,可分別採用從過去所周知的引線及晶片。作為密封材料10,可採用環氧樹脂等。作為接著材料13,只要是具有導電性的即可,可採用銀漿。 In other words, as shown in FIG. 6, the electronic component of the implementation type includes the wiring substrate 101 of the implementation type, and a plurality of second conductor portions 4 electrically connected to the wiring substrate 101 of the implementation type through a conductive adhesive material 13. One portion (the second conductor portion 4 in the center of FIG. 6) of the wafer 12, the electrode 12 and the plurality of second conductor portions 4 (the second conductor portion in the center of FIG. 6) are electrically connected to the electrodes of the wafer 12 through the metal layer 8. The lead 11 of the second conductor portion 4) other than 4 and an insulating sealing material 10 for sealing the lead 11 and the wafer 12. As the lead 11 and the wafer 12, a conventionally known lead and a wafer can be used, respectively. As the sealing material 10, epoxy resin or the like can be used. As the bonding material 13, any conductive material may be used, and silver paste may be used.
又,在第二導體部4的晶片接合部與引線接合部之間,設有凹口9。如此,藉由在晶片接合部與引線接合部之間設置凹口9,當在接合使用接著材料13的晶片12時,可藉由凹口9阻止流至晶片12之外側的接著材料13,於是可藉由凹口9接著材料13流出至外側。 A notch 9 is provided between the wafer bonding portion and the wire bonding portion of the second conductor portion 4. In this way, by providing the notch 9 between the wafer bonding portion and the wire bonding portion, when bonding the wafer 12 using the bonding material 13, the bonding material 13 flowing to the outside of the wafer 12 can be prevented by the notch 9. The material can flow out to the outside through the notch 9 and then the material 13.
此外,如後述的第11圖的模式平面圖所示的平面視角,凹口9的形狀可為與中央之第二導體部4非電性分離的形狀。若擁有此形狀,則可採用與使用第4圖來說明的藉由和去除導體層400的一部分來形成開口部5相同的步驟,來形成凹口9。又,在第6圖所示的電子元件中,構造上可使用不設有凹口9的第1圖或第5圖所示的配線基板1來取代配線基板101。 In addition, the shape of the notch 9 may be a shape that is non-electrically separated from the second conductive portion 4 in the center, as viewed from a plan view shown in a schematic plan view of FIG. 11 described later. With this shape, the notch 9 can be formed by the same procedure as that in which the opening 5 is formed by removing a part of the conductor layer 400 as described using FIG. 4. In addition, in the electronic component shown in FIG. 6, the wiring substrate 1 shown in FIG. 1 or FIG. 5 without the notch 9 may be used instead of the wiring substrate 101 in structure.
<電子元件之製造方法> <Manufacturing method of electronic components>
以下將參照第7圖至第9圖的模式剖面圖,說明實施型態之電子元件之製造方法之一例。首先,準備第6圖所示的配線基板101。第6圖所示的配線基板101在作為引線接合部之第二導體部4上包括金屬層8,並且,在第一導體部6的背面包括保護膜18,在第二導體部4的晶片接合部與引線接合部之間設有凹口9,除此之外,具有與第1圖所示的實施型態之配線基板1相同的構造。 An example of a method for manufacturing an electronic component according to an embodiment will be described below with reference to the schematic sectional views of FIGS. 7 to 9. First, the wiring substrate 101 shown in FIG. 6 is prepared. The wiring substrate 101 shown in FIG. 6 includes a metal layer 8 on the second conductor portion 4 as a wire bonding portion, and includes a protective film 18 on a back surface of the first conductor portion 6, and is bonded to a wafer of the second conductor portion 4. The recess 9 is provided between the portion and the wire bonding portion, and has the same structure as that of the wiring board 1 according to the embodiment shown in FIG. 1.
接著,如第7圖所示,透過在作為第6圖所示的實施型態之配線基板101之晶片接合部的第二導體部4上透過接著材料13接合晶片12。在此,晶片12在作為相向之2個凹口9之間的晶片接合部的第二導體部4上被接合。 Next, as shown in FIG. 7, the wafer 12 is bonded through the second conductor portion 4 which is the wafer bonding portion of the wiring substrate 101 of the embodiment shown in FIG. 6 through the bonding material 13. Here, the wafer 12 is bonded to the second conductor portion 4 which is a wafer bonding portion between the two notches 9 facing each other.
接著,如第8圖所示,藉由使用引線11的引線接合技術電性連接晶片12的電極與作為引線接合部的第二導體部4上的金屬層8。 Next, as shown in FIG. 8, the electrodes of the wafer 12 are electrically connected to the metal layer 8 on the second conductor portion 4 as a wire bonding portion by a wire bonding technique using a wire 11.
之後,如第9圖所示,使用密封材料10密封晶片12與引線11,藉此,可製造出第6圖所示的實施型態之電子元件。 Thereafter, as shown in FIG. 9, the sealing member 10 is used to seal the wafer 12 and the lead 11, and thereby the electronic component of the embodiment shown in FIG. 6 can be manufactured.
又,第6圖所示的實施型態之配線基板101的剖面構造可如第10的模式平面圖所示,宜使用沿著垂直方向及水平方向分別連續配置了複數個的實施型態之配線基板1001,製造出第6圖所示的實施型態之電子元件。在第10圖所示的實施型態之配線基板1001上,以第10圖之虛線所包圍的每個方形具有與第6圖所示的配線基板101相同的構造,該構造為分別沿著垂直方向及水平方向反覆連結的構造。換言 之,以第10圖之虛線包圍的其中一個方形與其他每一個方形一樣,至少第一導體部6及第二導體部4的圖樣是相同的,該圖樣分別延著垂直方向及水平方向反覆出現。 In addition, the cross-sectional structure of the wiring substrate 101 of the embodiment shown in FIG. 6 may be as shown in the pattern plan view of the tenth embodiment, and it is preferable to use a plurality of wiring boards of the embodiment in which a plurality of embodiments are continuously arranged along the vertical direction and the horizontal direction, respectively. 1001, an electronic component according to the embodiment shown in FIG. 6 is manufactured. On the wiring substrate 1001 of the embodiment shown in FIG. 10, each square surrounded by a dotted line in FIG. 10 has the same structure as the wiring substrate 101 shown in FIG. The structure is repeatedly connected in the horizontal direction and the horizontal direction. In other words In other words, one of the squares enclosed by the dotted line in FIG. 10 is the same as every other square. At least the patterns of the first conductor portion 6 and the second conductor portion 4 are the same. The patterns repeatedly appear in the vertical direction and the horizontal direction, respectively. .
藉由使用第10圖所示的配線基板1001,可更有效率地製造出第6圖所示的實施型態之電子元件。換言之,在作為第10圖所示的配線基板1001之晶片接合部的複數個第二導體部4的每一個上接合晶片12,使用引線11對晶片12與作為引線接合部的第二導體部4進行引線接合後,集合複數個晶片12與引線11並使用密封材料10將之密封起來。之後,伴隨密封材料10將配線基板1001個別化,切斷成一個一個的電子元件,藉此,可一次製造出複數個電子元件。 By using the wiring substrate 1001 shown in FIG. 10, the electronic component of the embodiment shown in FIG. 6 can be manufactured more efficiently. In other words, the wafer 12 is bonded to each of the plurality of second conductor portions 4 which are the wafer bonding portions of the wiring substrate 1001 shown in FIG. 10, and the leads 12 are used to pair the wafer 12 with the second conductor portion 4 which is a wire bonding portion. After the wire bonding is performed, a plurality of wafers 12 and leads 11 are assembled and sealed with a sealing material 10. After that, the wiring substrate 1001 is individually separated with the sealing material 10 and cut into individual electronic components, whereby a plurality of electronic components can be manufactured at one time.
在第11圖中,表示第6圖所示的實施型態之電子元件的模式平面圖。又,第12圖表示以第11圖之虛線111包圍的部分的配線基板的第一層的模式平面圖。第11圖所示的實施型態之電子元件的第二導體部4的晶片接合部4a的設置位置與以第12圖所示之虛線4a包圍的位置對應。又,第11圖所示的實施型態之電子元件的第二導體部4的引線接合部4b的設置位置與以第12圖所示的虛線4b包圍的位置對應。此外,在第12圖中,為了方便說明,僅表示1個引線接合部4b的設置位置。 FIG. 11 is a schematic plan view showing the electronic component according to the embodiment shown in FIG. 6. FIG. 12 is a schematic plan view of the first layer of the wiring board in a portion surrounded by a dotted line 111 in FIG. 11. The installation position of the wafer bonding portion 4a of the second conductor portion 4 of the electronic component according to the embodiment shown in FIG. 11 corresponds to the position surrounded by the dotted line 4a shown in FIG. The installation position of the wire bonding portion 4b of the second conductor portion 4 of the electronic component according to the embodiment shown in FIG. 11 corresponds to a position surrounded by a dotted line 4b shown in FIG. In addition, in FIG. 12, for convenience of explanation, only the installation position of one wire bonding portion 4 b is shown.
如第11圖及第12圖所示,實施型態之電子元件的第二導體部4的晶片接合部4a及引線接合部4b分別連接至配線基板的第一層的第一導體部6,並且也連接至樹脂部3。 As shown in FIGS. 11 and 12, the die bonding portion 4 a and the wire bonding portion 4 b of the second conductor portion 4 of the electronic component according to the embodiment are connected to the first conductor portion 6 of the first layer of the wiring substrate, respectively, Also connected to the resin portion 3.
<作用效果> <Effects>
在本實施型態中,可藉由樹脂基材300的蝕刻法等技術微 細地形成作為端子的第一導體部6的部分(空出間隔配置於第12圖外周的矩形第一導體部6),所以,相較於習知的QFN,可以以更狹窄的間距(相鄰的端子之間的間隔不滿0.4mm)來形成端子。藉此,在本實施型態中,相較於習知的QFN,可使端子數增加,得到多間距化,所以,可使非引線型電子元件微細化及高性能化。 In this embodiment, a technique such as an etching method for the resin substrate 300 can be used. The portion of the first conductor portion 6 (the rectangular first conductor portion 6 disposed at the outer periphery of FIG. 12) is formed finely as a terminal. Therefore, compared with the conventional QFN, a narrower pitch (phase The interval between adjacent terminals is less than 0.4 mm) to form terminals. As a result, in this embodiment, compared with the conventional QFN, the number of terminals can be increased and multi-pitch can be obtained. Therefore, the non-lead type electronic component can be miniaturized and high-performance.
又,在實施型態之配線基板上,採用圖樣化技術設置與第11圖所示之內引線51及外引線52相當的部分,藉此,可在不需要將引線11接合至外引線52的情況下,接合至比晶片12靠近的引線接合部4b。藉此,可縮短引線11的長度,所以,可提高引線接合技術的可靠性,進而將非引線型電子元件導向高品質化。 In addition, the wiring board of the implementation type is provided with a pattern corresponding to the inner lead 51 and the outer lead 52 shown in FIG. 11 by using a patterning technique, thereby making it possible to eliminate the need to bond the lead 11 to the outer lead 52. In this case, it is bonded to the wire bonding portion 4 b closer to the wafer 12. Thereby, since the length of the lead 11 can be shortened, the reliability of the wire bonding technology can be improved, and the non-lead type electronic component can be guided to high quality.
又,可如第13圖的模式剖面圖所示,若作為晶片接合部的第二導體部4的正下方為樹脂部3,透過樹脂部3將晶片12發出的熱釋放至外部將會非常困難。不過,在本實施型態中,可如第6圖所示,在作為晶片接合部的第二導體部4的正下方設置與該第二導體部4連接的第一導體部6。於是,在本實施型態中,可輕易透過作為晶片接合部的第二導體部4及其正下方的第一導體部6將晶片12所發出的熱釋放至外部,所以,此點也可將電子元件導向高品質化。 Further, as shown in the schematic sectional view of FIG. 13, if the resin portion 3 is located directly below the second conductor portion 4 as the wafer bonding portion, it is very difficult to release the heat emitted from the wafer 12 to the outside through the resin portion 3. . However, in this embodiment, as shown in FIG. 6, a first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wafer bonding portion. Therefore, in this embodiment, the heat emitted from the wafer 12 can be easily released to the outside through the second conductor portion 4 as the wafer bonding portion and the first conductor portion 6 directly below it. Therefore, at this point, High-quality electronic components.
又,可如第13圖至第15圖所示,若作為引線接合部的第二導體部4的正下方為開口7,當在對引線11進行引線接合時,作為引線接合部的第二導體部4的接合性會因為彈跳作用而下降。不過,在本實施型態中,可如第16圖所示, 在作為引線接合部的第二導體部4的正下方設置與該第二導體部4連接的第一導體部6。於是,可藉由第二導體部4的正下方的第一導體部6補強該第二導體部4的強度,所以,當在進行引線11的引線接合時,也可抑制因抑制該第二導體部4的彈跳作用而導致的接合性下降。 In addition, as shown in FIGS. 13 to 15, if the opening 7 is located directly below the second conductor portion 4 as the wire bonding portion, when the wire 11 is wire-bonded, the second conductor is used as the wire bonding portion. The jointability of the portion 4 is reduced by the bouncing effect. However, in this embodiment, as shown in FIG. 16, A first conductor portion 6 connected to the second conductor portion 4 is provided directly below the second conductor portion 4 as a wire bonding portion. Therefore, the strength of the second conductor portion 4 can be reinforced by the first conductor portion 6 directly below the second conductor portion 4. Therefore, when the wire bonding of the lead 11 is performed, the suppression of the second conductor can also be suppressed. The bonding property due to the bouncing action of the portion 4 is reduced.
又,可如第13圖至第15圖所示,若作為引線接合部的第二導體部4的正下方為開口7,當進行引線11的引線接合時,加諸於作為引線接合部之第二導體部4的損壞變大。不過,在本實施型態中,可如第16圖所示,在作為引線接合部的第二導體部4的正下方設置與該第二導體部4連接的第一導體部6。於是,可藉由第二導體部4的正下方的第一導體部6補強該第二導體部4的強度,所以,當進行引線11的引線接合時,可減少對該第二導體部4的損壞。 In addition, as shown in FIGS. 13 to 15, if the opening 7 is located directly below the second conductor portion 4 as the wire bonding portion, when the wire bonding of the lead 11 is performed, it is added to the first wire bonding portion. Damage to the two conductor portions 4 is increased. However, in this embodiment, as shown in FIG. 16, a first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wire bonding portion. Therefore, the strength of the second conductor portion 4 can be reinforced by the first conductor portion 6 directly below the second conductor portion 4. Therefore, when the wire bonding of the lead 11 is performed, the strength of the second conductor portion 4 can be reduced. damage.
又,可如第13至15圖所示,若作為引線接合部的第二導體部4的正下方為開口7,當進行電子元件的二次封裝時,會產生焊料空洞而有封裝不良的情況。又,為了使第二導體部4的正下方為開口7,當在進行二次封裝時,焊料會脫離開口7而無法形成良好的圓角。不過,在本實施型態中,可如第6圖所示,在作為引線接合部的第二導體部4的正下方設置與該第二導體部4連接的第一導體部6,所以,可抑制在進行二次封裝時的問題產生。 In addition, as shown in FIGS. 13 to 15, if the opening 7 is located immediately below the second conductor portion 4 as the wire bonding portion, solder voids may occur when the electronic component is repackaged, which may cause poor packaging. . In addition, in order to make the opening 7 directly below the second conductor portion 4, when the secondary packaging is performed, the solder is detached from the opening 7 and a good fillet cannot be formed. However, in this embodiment, as shown in FIG. 6, the first conductor portion 6 connected to the second conductor portion 4 may be provided directly below the second conductor portion 4 as a wire bonding portion. This prevents problems during secondary packaging.
在第17(a1)圖至第17(a3)圖中,表示圖解習知之QFN中之框架之製造方法的模式剖面圖,第17(b1)圖至第17(b5)圖表示圖解本實施型態之配線基板之製造方法之一例的 模式剖面圖。此外,框架也稱為引線框架。 Figs. 17 (a1) to 17 (a3) are schematic cross-sectional views illustrating a method for manufacturing a frame in a conventional QFN, and Figs. 17 (b1) to 17 (b5) illustrate the present embodiment. Of an example of a manufacturing method of a wiring board Pattern section view. The frame is also called a lead frame.
在習知的QFN上,於第17(a1)圖所示的框架40的一部分上如第17(a2)圖所示地設置開口部5之後,如第17(a3)圖所示,在框架40的一部分的表面上形成由銀所構成的金屬層8。因此,在習知的QFN上,框架40的表面會因暴露於大氣而氧化,於是有框架40壽命變短的問題。另一方面,在本實施型態中,如第17(b5)圖所示,藉由用保護膜18被覆第一導體部6的背面,相較於習知的QFN,可有效抑制第一導體部6的氧化。此外,在習知的QFN上,當如第17(a2)圖所示地設置開口部5時,為了不使框架40的各個構成要素分離,將用來作機械連接的連結部形成於框架40上。 In the conventional QFN, after openings 5 are provided on a part of the frame 40 shown in FIG. 17 (a1) as shown in FIG. 17 (a2), as shown in FIG. 17 (a3), A metal layer 8 made of silver is formed on a part of the surface of 40. Therefore, on the conventional QFN, the surface of the frame 40 may be oxidized by exposure to the atmosphere, so that there is a problem that the life of the frame 40 becomes short. On the other hand, in this embodiment, as shown in FIG. 17 (b5), by covering the back surface of the first conductor portion 6 with the protective film 18, the first conductor can be effectively suppressed compared to the conventional QFN. The oxidation of the part 6. In addition, in the conventional QFN, when the opening portion 5 is provided as shown in FIG. 17 (a2), in order not to separate the constituent elements of the frame 40, a connecting portion for mechanical connection is formed on the frame 40. on.
又,在習知的QFN上,需要對比實施型態之配線基板厚的框架40加工,由於微細加工很困難,所以無法使端子數增加,多間距化受到限制。另一方面,在本實施型態中,可藉由對更薄的樹脂基材300及導體層400這兩者的加工來形成端子,所以,更微細的加工是可能的,於是相較於習知的QFN,可使端子數增加。此外,第17(b1)圖至第17(b3)圖及第17(b5)圖分別與第2圖至第5圖對應,第17(b4)圖與第1圖對應,所以,在此省略第17(b1)圖至第17(b5)圖的說明。 In the conventional QFN, it is necessary to process the frame 40 with a thicker wiring substrate in a comparative embodiment. Since microfabrication is difficult, the number of terminals cannot be increased, and multi-pitch is limited. On the other hand, in this embodiment, the terminals can be formed by processing both the thinner resin substrate 300 and the conductive layer 400, so that finer processing is possible, so compared with conventional Known QFN can increase the number of terminals. In addition, Figs. 17 (b1) to 17 (b3) and 17 (b5) correspond to Figs. 2 to 5 respectively, and Fig. 17 (b4) corresponds to Fig. 1, so they are omitted here. Explanation of FIGS. 17 (b1) to 17 (b5).
在第18(a1)圖至第18(a5)圖及第19(a6)圖至第19(a8)圖中,表示圖解習知之QFN之組裝製程的模式剖面圖,在第18(b1)圖、第18(b2)圖、第18(b4)圖、第18(b5)圖及第19(b8)圖中,表示圖解本實施型態之電子元件之製造方法之一例的模式剖面圖。 Figures 18 (a1) to 18 (a5) and Figures 19 (a6) to 19 (a8) are schematic cross-sectional views illustrating the assembly process of the conventional QFN. Figures 18 (b1) Fig. 18 (b2), Fig. 18 (b4), Fig. 18 (b5), and Fig. 19 (b8) are schematic cross-sectional views illustrating an example of a method for manufacturing an electronic component according to this embodiment.
此外,第18(b1)圖、第18(b2)圖、第18(b4)圖、第 18(b5)圖及第19(b8)圖分別在實施型態之電子元件之製造方法之一例之製程中,表示與習知之QFN之組裝製程之第18(a1)圖、第18(a2)圖、第18(a4)圖、第18(a5)圖及第19(a8)圖對應的製成。 In addition, Figs. 18 (b1), 18 (b2), 18 (b4), and Figures 18 (b5) and 19 (b8) show the eighteenth (a1) and eighteenth (a2) drawings of the assembly process with the conventional QFN in the manufacturing process of an example of the manufacturing method of the electronic component of the implementation type. Figure, Figure 18 (a4), Figure 18 (a5), and Figure 19 (a8).
在習知的QFN的組裝製程中,如第18(a1)圖所示,透過接著材料13在框架40上對晶片12進行晶片接合技術之後,如第18(a2)圖所示,再對引線11進行引線接合技術。不過,在習知的QFN的組裝製程中,端子的先端不會固定於另一元件,所以,會有接合性不良好的問題。另一方面,在本實施型態中,作為端子的第二導體部4的一部分與樹脂部3連接,所以,引線接合情況穩定,接合性提高。藉此,在本實施型態中,可製造出高品質的非引線型的電子元件。 In the conventional QFN assembly process, as shown in FIG. 18 (a1), after the wafer 12 is bonded to the wafer 12 on the frame 40 through the bonding material 13, as shown in FIG. 18 (a2), the leads are then bonded. 11 Perform wire bonding technology. However, in the conventional QFN assembly process, the tip of the terminal is not fixed to another component, so there is a problem of poor jointability. On the other hand, in this embodiment, since a part of the second conductor portion 4 as the terminal is connected to the resin portion 3, the wire bonding situation is stable and the bondability is improved. Thereby, in this embodiment, a high-quality non-lead-type electronic component can be manufactured.
又,在習知的QFN的組裝製程中,如第18(a3)圖所示,需要使用QFN用組裝膠帶41。另一方面,在本實施型態中,不需要使用QFN用組裝膠帶41,所以,可使製程數減少,並且,可節省相當於QFN用組裝膠帶41之費用的材料費。藉此,在本實施型態中,相較於習知的QFN的組裝製程,可以簡易的製程和低成本來製造非引線型電子元件。 In the conventional QFN assembly process, as shown in FIG. 18 (a3), it is necessary to use a QFN assembly tape 41. On the other hand, in the present embodiment, it is not necessary to use the QFN assembly tape 41, so that the number of processes can be reduced, and the material cost equivalent to the cost of the QFN assembly tape 41 can be saved. Therefore, in this embodiment, compared with the conventional QFN assembly process, a non-lead electronic component can be manufactured with a simple process and low cost.
又,在習知的QFN的組裝製程中,如第18(a4)圖所示,進行使用密封材料10的密封製程後,進行對第18(a5)圖所示的密封材料10的標記製程,但藉由較薄的QFN用組裝膠帶41,在第18(a4)圖所示的密封製程中會有外洩密封樹脂的問題。另一方面,在本實施型態中,由於包括實施型態之配線基板,所以此種問題不會產生。 In the conventional QFN assembly process, as shown in FIG. 18 (a4), after the sealing process using the sealing material 10 is performed, the marking process for the sealing material 10 shown in FIG. 18 (a5) is performed. However, with the thin QFN assembly tape 41, there is a problem that the sealing resin is leaked during the sealing process shown in FIG. 18 (a4). On the other hand, in this embodiment mode, since the wiring substrate of the embodiment mode is included, such a problem does not occur.
又,在習知的QFN的組裝製程中,如第19(a6)圖所 示,需要將QFN用組裝膠帶41從框架40剝離,並如第19(a7)圖所示,對框架40的背面被覆由錫所構成的保護膜180。另一方面,在本實施型態中,不需要進行這些製程,所以可使製程數減少。 In the conventional QFN assembly process, as shown in FIG. 19 (a6), It is shown that the QFN assembly tape 41 needs to be peeled from the frame 40, and as shown in FIG. 19 (a7), the back surface of the frame 40 is covered with a protective film 180 made of tin. On the other hand, in this embodiment mode, since these processes are not required, the number of processes can be reduced.
又,在習知的QFN的組裝製程中,如第19(a8)圖所示,進行切片使每個電子元件個別化的製程,但進行切片的框架40的寬度後來變寬,所以,需要一邊切削框架40,一邊進行個別化。結果,框架40的切斷部分有毛邊產生,有電子元件品質不良的情況存在。另一方面,在本實施型態中,第一導體部6及第二導體部4的微細加工是可能的,所以,切斷部分的第一導體部6及第二導體部4的寬度可變窄。結果,當將每個電子元件個別化時,在不需要切削第一導體部6及第二導體部4的情況下,藉由加壓來切割,所以,可減少毛邊的產生。結果,在本實施型態中,相較於習知的QFN的組裝製程,可製造出高品質的非引線型電子元件。 In the conventional QFN assembly process, as shown in FIG. 19 (a8), a process of slicing and individualizing each electronic component is performed, but the width of the slicing frame 40 is later widened, so one side is required The frame 40 is cut while being individualized. As a result, burrs may be generated at the cut portion of the frame 40, and the quality of electronic components may be poor. On the other hand, in this embodiment mode, fine processing of the first conductor portion 6 and the second conductor portion 4 is possible. Therefore, the widths of the first conductor portion 6 and the second conductor portion 4 that are cut off are variable. narrow. As a result, when each of the electronic components is individualized, the first conductor portion 6 and the second conductor portion 4 need not be cut, and the cutting is performed by pressing, so that the occurrence of burrs can be reduced. As a result, in this embodiment, a high-quality non-lead-type electronic component can be manufactured compared to a conventional QFN assembly process.
在此將補充說明。在習知的QFN上,如上所述,為了不使框架40的各個構成要素分離,將用來作機械連接的連結部設置於框架40上。此連結部可形成於與第10圖之虛線所示的部分相當的位置。另外,在電子元件之製程作業中,要求能使各個構成要素不分離的機械強度,所以,連結部的寬度比較寬。此寬度比較寬的連結部可藉由使用切割刀片的切割技術來切削,所以,容易產生毛邊。又,切割刀片等切割技術中使用的消耗品的壽命也會變短。 Explanation will be added here. In the conventional QFN, as described above, in order not to separate the constituent elements of the frame 40, a connecting portion for mechanical connection is provided on the frame 40. This connecting portion may be formed at a position corresponding to a portion shown by a dotted line in FIG. 10. In addition, in the manufacturing process of electronic components, a mechanical strength capable of preventing the constituent elements from being separated is required, so the width of the connecting portion is relatively wide. This relatively wide connecting portion can be cut by a cutting technique using a cutting blade, so burrs are easily generated. In addition, the life of consumables used in cutting technology such as a cutting blade is shortened.
另一方面,在本實施型態中,基本上不需要用來作機械連接的連結部。又,若在使用第5圖說明的開口7形成 第一導體部時採用電鍍技術,為了使作為第11圖之外引線52的部分的複數個導體層400電性連接,可在第10圖的各個配線基板101的邊界部分及外周部分(在第10圖中以虛線表示的部分),形成使用導體層400的連結部。在此情況下,連接部的寬度只要可導通電鍍作用即可,所以較窄也無妨。於是,即使此寬度較窄的連結部可藉由使用切割刀片的切割技術切斷,相較於習知的QFN,難以產生毛邊。又,相較於習知的QFN,使用於切割刀片等切割工具的消耗品的壽命變長。 On the other hand, in this embodiment, a connecting portion for mechanical connection is basically unnecessary. In addition, if the opening 7 described using FIG. 5 is formed, In the first conductor portion, electroplating technology is used. In order to electrically connect the plurality of conductor layers 400 that are portions of the lead 52 other than that shown in FIG. 11, the boundary portion and the peripheral portion of each wiring substrate 101 in FIG. A portion indicated by a dotted line in FIG. 10) forms a connection portion using the conductor layer 400. In this case, as long as the width of the connection portion can be conducted by plating, it may be narrower. Therefore, even if the narrow connection portion can be cut by a cutting technique using a cutting blade, compared with the conventional QFN, it is difficult to generate burrs. In addition, the life of consumables used for cutting tools such as cutting blades is longer than that of the conventional QFN.
如上所述,根據本實施型態,相較於習知的QFN,可使端子數增加。又,可藉由比習知的QFN還簡易的製程和低成本製造出高品質的電子元件。又,可輕易製造出品質比習知的QFN還高的電子元件。 As described above, according to this embodiment, the number of terminals can be increased compared to the conventional QFN. In addition, high-quality electronic components can be manufactured by a simpler process and lower cost than the conventional QFN. In addition, it is possible to easily manufacture electronic components of higher quality than the conventional QFN.
如上所述地說明了實施型態,但適當組合上述各實施型態的構造的發明也在一開始預設的範圍內。 The embodiments have been described as described above, but an invention in which the structures of the above embodiments are appropriately combined is also in a range preset at the beginning.
此次揭示的實施型態應該不受所有例示的特性限定。本發明的範圍並非上述的說明而是由申請專利範圍所揭示,本發明也意圖包含在與申請專利範圍相等的意涵及範圍內的所有變更。 The implementation form disclosed this time should not be limited by all the exemplified characteristics. The scope of the present invention is not disclosed by the above description, but is disclosed by the scope of patent application. The present invention is also intended to include all changes within the meaning and scope equivalent to the scope of patent application.
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016136037A JP6333894B2 (en) | 2016-07-08 | 2016-07-08 | Wiring board, wiring board manufacturing method, electronic component, and electronic component manufacturing method |
JP2016-136037 | 2016-07-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201804881A TW201804881A (en) | 2018-02-01 |
TWI650051B true TWI650051B (en) | 2019-02-01 |
Family
ID=60912065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106111861A TWI650051B (en) | 2016-07-08 | 2017-04-10 | Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component |
Country Status (6)
Country | Link |
---|---|
JP (1) | JP6333894B2 (en) |
KR (1) | KR102254999B1 (en) |
CN (1) | CN109478536A (en) |
MY (1) | MY192589A (en) |
TW (1) | TWI650051B (en) |
WO (1) | WO2018008214A1 (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003303859A (en) * | 2002-04-10 | 2003-10-24 | Hitachi Cable Ltd | Tape carrier for semiconductor device and its manufacturing method |
US7164192B2 (en) * | 2003-02-10 | 2007-01-16 | Skyworks Solutions, Inc. | Semiconductor die package with reduced inductance and reduced die attach flow out |
JP2005116909A (en) * | 2003-10-10 | 2005-04-28 | Hitachi Cable Ltd | Electronic device and wiring board used therefor |
JP2011029518A (en) * | 2009-07-28 | 2011-02-10 | Shindo Denshi Kogyo Kk | Flexible printed wiring board, semiconductor device, and method for manufacturing the same |
JP5848976B2 (en) * | 2012-01-25 | 2016-01-27 | 新光電気工業株式会社 | WIRING BOARD, LIGHT EMITTING DEVICE, AND WIRING BOARD MANUFACTURING METHOD |
-
2016
- 2016-07-08 JP JP2016136037A patent/JP6333894B2/en active Active
-
2017
- 2017-04-04 CN CN201780042267.9A patent/CN109478536A/en active Pending
- 2017-04-04 KR KR1020187036756A patent/KR102254999B1/en active IP Right Grant
- 2017-04-04 MY MYPI2019000001A patent/MY192589A/en unknown
- 2017-04-04 WO PCT/JP2017/014101 patent/WO2018008214A1/en active Application Filing
- 2017-04-10 TW TW106111861A patent/TWI650051B/en active
Also Published As
Publication number | Publication date |
---|---|
KR20190025835A (en) | 2019-03-12 |
WO2018008214A1 (en) | 2018-01-11 |
MY192589A (en) | 2022-08-29 |
JP6333894B2 (en) | 2018-05-30 |
CN109478536A (en) | 2019-03-15 |
JP2018006702A (en) | 2018-01-11 |
KR102254999B1 (en) | 2021-05-24 |
TW201804881A (en) | 2018-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9136247B2 (en) | Resin-encapsulated semiconductor device and method of manufacturing the same | |
US6841854B2 (en) | Semiconductor device | |
KR102082941B1 (en) | Resin-encapsulated semiconductor device and method of manufacturing the same | |
JP6840466B2 (en) | Semiconductor package and manufacturing method of semiconductor package | |
JP6863846B2 (en) | Substrate for mounting semiconductor elements and its manufacturing method | |
JP2005057067A (en) | Semiconductor device and manufacturing method thereof | |
KR20150032493A (en) | Semiconductor device and method of manufacturing the same | |
US9184116B2 (en) | Method of manufacturing resin-encapsulated semiconductor device, and lead frame | |
JP7144157B2 (en) | Semiconductor device and its manufacturing method | |
US6716675B2 (en) | Semiconductor device, method of manufacturing semiconductor device, lead frame, method of manufacturing lead frame, and method of manufacturing semiconductor device with lead frame | |
JP6505540B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP2005244035A (en) | Mounting method of semiconductor device, and semiconductor device | |
JP6927634B2 (en) | Substrate for mounting semiconductor elements and its manufacturing method | |
WO2015015850A1 (en) | Module and method for manufacturing same | |
TWI650051B (en) | Wiring substrate, manufacturing method of wiring substrate, electronic component, and manufacturing method of electronic component | |
JP4982664B2 (en) | Electronic device apparatus and manufacturing method thereof | |
JP2017183511A (en) | Semiconductor device manufacturing method | |
JP2019145625A (en) | Semiconductor device | |
JP2013254984A (en) | Semiconductor device | |
JP7145414B2 (en) | Lead frame and its manufacturing method, and semiconductor device and its manufacturing method | |
JP4294034B2 (en) | Semiconductor device | |
WO2015129185A1 (en) | Resin-sealed semiconductor device, production method therefor, and mounting body therefor | |
KR20090088265A (en) | Semiconductor package and method for fabricating of the same |