KR100388291B1 - Structure of semiconductor package - Google Patents
Structure of semiconductor package Download PDFInfo
- Publication number
- KR100388291B1 KR100388291B1 KR10-1999-0021137A KR19990021137A KR100388291B1 KR 100388291 B1 KR100388291 B1 KR 100388291B1 KR 19990021137 A KR19990021137 A KR 19990021137A KR 100388291 B1 KR100388291 B1 KR 100388291B1
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- KR
- South Korea
- Prior art keywords
- circuit board
- semiconductor package
- flexible circuit
- thin film
- metal thin
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 반도체패키지 구조에 관한 것이다.The present invention relates to a semiconductor package structure.
종래의 fBGA반도체패키지는 가요성회로기판(1)이 수지필름(7)이 코팅된 1단(층)의 금속회로패턴(8)으로 구성되어 있기 때문에 반도체패키지의 제조시 발생하는 가요성회로기판(1) 자체의 휨변형 문제를 해결하기 위하여 별도의 캐리어프레임을 사용해 반도체패키지를 제조해 왔었다. 따라서 제조원가의 상승은 물론 반도체패키지의 품질에도 적지 않은 문제점을 야기시켜 왔었다.The conventional fBGA semiconductor package is a flexible circuit board generated in the manufacture of a semiconductor package because the flexible circuit board 1 is composed of a one-layer (layer) metal circuit pattern 8 coated with a resin film 7. (1) The semiconductor package has been manufactured using a separate carrier frame in order to solve the bending deformation problem. Therefore, not only the increase of manufacturing cost but also the quality of semiconductor package has caused a lot of problems.
이에, 본 발명에서는 가요성회로기판(10)에 인쇄되는 금속회로패턴을 2단(층)의 상·하금속회로패턴(12)(11) 구조로 구성하여 가요성회로기판(10)의 강성보강이 이루어질 수 있도록 함으로써 별도의 캐리어프레임의 사용 없이 가요성회로기판만을 사용하여 반도체패키지의 제조가 가능토록하고, 나아가 열방출 능력이 향상된 고품질의 fBGA 반도체패키지를 제공토록 한 것이다.Accordingly, in the present invention, the rigid circuit board 10 is formed by forming a metal circuit pattern printed on the flexible circuit board 10 in a two-layered upper and lower metal circuit patterns 12 and 11 structure. By reinforcing, it is possible to manufacture a semiconductor package using only a flexible circuit board without using a separate carrier frame, and to provide a high quality fBGA semiconductor package with improved heat dissipation capability.
Description
본 발명은 반도체패키지에 대한 것으로, 더욱 상세하게는 가요성회로기판의 저면에 솔더볼을 부착한 fBGA 반도체패키지의 구조에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a structure of an fBGA semiconductor package having a solder ball attached to a bottom surface of a flexible circuit board.
일반적으로, 반도체패키지는 그 내부에 반도체칩을 비롯한 고밀도의 회로를 내장하게 되는 관계로 외부환경(외력, 먼지, 습기, 전기적 열적 부하 등)으로부터 회로를 보호하고 반도체칩의 성능을 극대화하기 위하여 금속재질의 리드프레임이나 회로패턴이 실장된 플라스틱 스트립자재를 이용해 신호의 입출력단자를 형성하고 봉지수단(컴파운드수지에 의한 성형화 또는 코팅화)으로 패키지성형한 납작한 형태의 구조(표면실장형)를 취하게 된다.In general, semiconductor packages have high-density circuits, including semiconductor chips, inside them, so that the circuits are protected from the external environment (external force, dust, moisture, electrical thermal loads, etc.) to maximize the performance of semiconductor chips. Signal input and output terminals are formed by using a lead strip of material or plastic strip material on which circuit patterns are mounted, and a flat structure (surface mount type) packaged by sealing means (molding or coating by compound resin) is taken. Done.
한편, 근자 전자기기의 고성능화와 더불어 휴대용화가 진행됨에 따라 이러한 전자기기에 사용되는 반도체패키지 또한 고집적화, 초경량화, 소형화, 박형화되는 경향으로 이미 패키지의 양측(또는 사방)으로 리드를 형성한 반도체패키지 구조에서 패키지의 하면에 솔더볼(Solder Ball)을 형성한 BGA(Ball Grid Array) 반도체패키지의 출현을 보게 되었다. 통상 BGA반도체패키지는 회로패턴이 인쇄된 플라스틱회로기판을 사용하게 되는데 그 가격이 고가인 관계로 최근에는 수지(PI계열)필름의 가요성회로기판을 이용한 fBGA반도체패키지(Flexible Ball Grid Array)가 많이 사용되고 있다.On the other hand, as high-performance electronic devices become more portable and more portable, semiconductor packages used in such electronic devices also tend to be highly integrated, ultra light, miniaturized, and thin, and have a semiconductor package structure in which leads are formed on both sides (or four sides) of the package. Saw the advent of BGA (Ball Grid Array) semiconductor packages with solder balls on the bottom of the package. In general, BGA semiconductor package uses a plastic circuit board printed with a circuit pattern. Since the price is high, recently, a fBGA semiconductor package (Flexible Ball Grid Array) using a flexible circuit board of a resin (PI series) film is used. It is used.
이 fBGA반도체패키지의 일반적인 구성을 보면, 도1, 도2a, 2b의 예시에서 보는 바와 같이 수지필름(7)에 금속회로패턴(8)을 형성한 가요성회로기판(1)의 상면 중앙에 절연접착제(3)를 사용하여 반도체칩(2)을 부착하고, 이 반도체칩(2)과 가요성회로기판(1)에 인쇄된 금속회로패턴(8)을 와이어(4)로 연결한 후, 컴파운드수지(5)로 성형하고, 상기 가요성회로기판(1)의 저면에 솔더볼(6)을 부착하는 구조로 되어 있음을 볼 수 있다.As a general configuration of this fBGA semiconductor package, as shown in the examples of FIGS. 1, 2A, and 2B, an insulating layer is formed in the center of the upper surface of the flexible circuit board 1 having the metal circuit pattern 8 formed on the resin film 7. The semiconductor chip 2 is attached using an adhesive 3, the metal circuit pattern 8 printed on the semiconductor chip 2 and the flexible circuit board 1 is connected with a wire 4, and then compounded. It can be seen that the molding is made of resin 5 and the solder ball 6 is attached to the bottom surface of the flexible circuit board 1.
그러나, 종래의 fBGA반도체패키지는 가요성회로기판(1)이 수지필름(7)에 금속회로패턴(8)을 1단으로 인쇄한 상태이기 때문에 반도체패키지의 제조공정상에서 가요성회로기판(1) 자체의 휨 변형이 발생하게 됨으로 이러한 제조공정상의 문제를 해결하기 위하여 추가적으로 캐리어프레임을 사용할 수밖에 없으므로 제조원가의 상승은 물론 반도체패키지의 품질에도 적지 않은 문제점을 야기시켜 왔었다.However, since the conventional fBGA semiconductor package is a state in which the flexible circuit board 1 prints the metal circuit pattern 8 on the resin film 7 in one step, the flexible circuit board 1 is manufactured in the manufacturing process of the semiconductor package. Since the bending deformation of its own causes the carrier frame to be additionally used to solve the manufacturing process problem, it has caused a lot of problems in the quality of the semiconductor package as well as the increase in manufacturing cost.
또한 종래의 fBGA 반도체패키지는 가요성회로기판(1)에 반도체칩(2)을 부착함에 있어서 열방출이 불가능한 절연접착제(3)를 사용한 관계로 반도체패키지 제품의 신뢰성을 저하시키는 문제점이 있었다.In addition, the conventional fBGA semiconductor package has a problem of lowering the reliability of semiconductor package products due to the use of an insulating adhesive (3) that is not heat dissipated in attaching the semiconductor chip (2) to the flexible circuit board (1).
이에, 본 발명에서는 가요성회로기판에 인쇄되는 금속회로패턴을 2단으로 구성하여 가요성회로기판의 강성보강이 이루어질 수 있도록 한 것으로, 본 발명의 목적은 별도의 캐리어프레임의 사용없이 가요성회로기판만을 사용하여 반도체패키지의 제조가 가능토록하고, 나아가 열방출 능력이 향상된 고품질의 fBGA 반도체패키지를 제공하는데 있다.Therefore, in the present invention, the metal circuit pattern printed on the flexible circuit board is configured in two stages so that the rigid reinforcement of the flexible circuit board can be achieved. An object of the present invention is to provide a flexible circuit without using a separate carrier frame. The present invention provides a high quality fBGA semiconductor package that enables the manufacture of a semiconductor package using only a substrate and further improves heat dissipation capability.
도 1은 종래 가요성회로기판을 이용한 반도체패키지의 구성도1 is a configuration diagram of a semiconductor package using a conventional flexible circuit board
도 2a는 종래 반도체패키지에 적용된 가요성회로기판의 구성도(평면도)2A is a block diagram (plan view) of a flexible circuit board applied to a conventional semiconductor package.
도 2b는 도2a의 A-A선 확대 단면도(개략도)FIG. 2B is an enlarged sectional view taken along the line A-A of FIG. 2A
도 3은 본 발명의 반도체패키지의 구성도3 is a configuration diagram of a semiconductor package of the present invention
도 4는 본 발명의 반도체패키지에 적용된 가요성회로기판의 단면 구성도4 is a cross-sectional configuration diagram of a flexible circuit board applied to a semiconductor package of the present invention.
도 5는 본 발명의 반도체패키지에 적용된 가요성회로기판의 다른 실시예를 보인 단면도Figure 5 is a cross-sectional view showing another embodiment of a flexible circuit board applied to the semiconductor package of the present invention
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 가요성회로기판 2 : 반도체칩1: flexible circuit board 2: semiconductor chip
3 : 절연접착제 4 : 와이어3: insulation adhesive 4: wire
5 : 컴파운드수지 6 : 솔더볼5: compound resin 6: solder ball
7 : 수지필름(PI 필름) 8 : 금속회로패턴7: Resin film (PI film) 8: Metal circuit pattern
10 : 가용성회로기판 11 : 하단금속회로패턴10: fusible circuit board 11: bottom metal circuit pattern
12 : 상단금속회로패턴 13 : 열전도성절연접착제12: upper metal circuit pattern 13: thermal conductive insulating adhesive
14, 15 : 수지필름(보호막) 16 : 연결패턴14, 15: resin film (protective film) 16: connection pattern
상기와 같은 목적을 달성하기 위한 본 발명의 반도체패키지 구조는 다음과 같은 특징을 제공한다.The semiconductor package structure of the present invention for achieving the above object provides the following features.
금속회로패턴이 인쇄된 가요성회로기판을 사용하는 fBGA 반도체패키지를 구성함에 있어서,중앙에 일정 면적을 가지며 판상으로 하단금속박막(11a)이 형성되고, 상기 하단금속박막(11a)과 일정 거리 이격되어 다수의 하단금속회로패턴(11)이 형성되며, 상기 하단금속박막(11a) 및 하단금속회로패턴(11)의 하면 및 상면에 수지필름(14)(15)이 코팅되고, 상기 상면의 수지필름(15)중 상기 하단금속박막(11a)과 대응되는 영역에 일정 면적을 가지며 판상으로 상단금속박막(12a)이 형성되고, 상기 상단금속박막(12a)과 일정 거리 이격되어 다수의 상단금속회로패턴(12)이 형성되며, 상기 하단금속회로패턴(11)과 상단금속회로패턴(12)을 연결하도록 상기 상면 수지필름(15)을 관통하여 다수의 연결패턴(16)이 형성된 가요성회로기판(10), 상기 가요성회로기판(10)의 상단금속박막(12a)에 열도전성절연접착제(13)로 접착된 반도체칩(2), 상기 반도체칩(2)과 상기 가요성회로기판(1)의 상단금속회로패턴(12)을 연결하는 도전성 와이어(4), 상기 가요성회로기판(10)의 상면에 위치하는 반도체칩(2), 도전성와이어(4)등을 봉지하는 컴파운드수지(5)와, 상기 가요성회로기판(10)의 하면 수지필름(14)을 관통하여 하단금속회로패턴(11) 및 하단금속박막(11a)에 융착된 다수의 솔더볼(6)을 포함하여 이루어진 것을 특징으로 한다.In constructing an fBGA semiconductor package using a flexible circuit board printed with a metal circuit pattern, a bottom metal thin film 11a is formed in a plate shape in the center and spaced apart from the bottom metal thin film 11a by a predetermined distance. A plurality of bottom metal circuit patterns 11 are formed, and resin films 14 and 15 are coated on the bottom and top surfaces of the bottom metal thin film 11a and the bottom metal circuit pattern 11, and the resin on the top surface. The film 15 has a predetermined area in a region corresponding to the bottom metal thin film 11a and the top metal thin film 12a is formed in a plate shape, and is spaced apart from the top metal thin film 12a by a predetermined distance, thereby forming a plurality of top metal circuits. The flexible circuit board is formed with a pattern 12 and a plurality of connection patterns 16 are formed through the upper resin film 15 to connect the lower metal circuit pattern 11 and the upper metal circuit pattern 12. 10, the upper metal foil of the flexible circuit board 10 A semiconductor chip 2 bonded with a thermally conductive insulating adhesive 13 to 12a, and a conductive wire 4 connecting the semiconductor chip 2 and the upper metal circuit pattern 12 of the flexible circuit board 1 to each other. ), A compound resin 5 for encapsulating a semiconductor chip 2, a conductive wire 4, and the like disposed on an upper surface of the flexible circuit board 10, and a bottom resin film of the flexible circuit board 10. 14 and a plurality of solder balls 6 fused to the bottom metal circuit pattern 11 and the bottom metal thin film 11a.
따라서, 본 발명에 의하면 가요성회로기판(10)은 강성이 보강되어 별도의 캐리어프레임이 요구되지 않으면서도 열방출 효과가 뛰어난 고신뢰성의 fBGA 반도체패키지를 제공하는 효과가 있는 것이다.Therefore, according to the present invention, the flexible circuit board 10 has an effect of providing a high reliability fBGA semiconductor package having excellent heat dissipation effect without requiring a separate carrier frame due to the rigidity of the flexible circuit board 10.
(실시예)(Example)
이하, 본 발명을 첨부된 예시도면을 통해 보다 구체적으로 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도3은 본 발명의 fBGA 반도체패키지 구조를 단면도로 보인 것이고, 도4는 본 발명에 적용된 가요성회로기판의 단면 구성을 보인 것이다. 본 발명에 있어서 통상의 일반 fBGA 반도체패키지를 구성하는 구성요소와 그 구조가 같고 같은 기능을 하는 것은 설명의 편의상 동일부호를 사용하였다.FIG. 3 is a cross-sectional view of an fBGA semiconductor package structure of the present invention, and FIG. 4 is a cross-sectional view of a flexible circuit board applied to the present invention. In the present invention, the same constituent elements and the same functions as those of the components of a general fBGA semiconductor package have the same reference numerals for convenience of description.
도3의 예시와 같이, 본 발명의 반도체패키지는 금속회로패턴이 2단으로 구성된 가요성회로기판(10)에 반도체칩(2)을 부착하고 그 상면을 컴파운드수지(5)로 성형한 후 상기 가요성회로기판(10)의 밑면에 솔더볼(6)을 부착하여 이루어지게 되는데,As shown in FIG. 3, the semiconductor package according to the present invention attaches the semiconductor chip 2 to the flexible circuit board 10 having the metal circuit pattern composed of two stages, and the upper surface of the semiconductor package is formed of the compound resin 5, It is made by attaching a solder ball 6 to the bottom of the flexible circuit board 10,
본 발명에 적용되는 가요성회로기판(10)은 도4의 예시와 같이 수지필름(14)에 의해 보호되는 하단금속회로패턴(11)과, 상기 하단금속회로패턴(11)의 상면에 도포된 수지필름(15) 위에 인쇄되는 상단금속회로패턴(12)의 2단 구성으로 이루어져 있다.The flexible circuit board 10 applied to the present invention is applied to the lower metal circuit pattern 11 and the upper surface of the lower metal circuit pattern 11 protected by the resin film 14 as shown in FIG. It consists of a two-stage configuration of the upper metal circuit pattern 12 is printed on the resin film (15).
상기 상·하단금속회로패턴(11)(12)들은 수지필름(15)을 관통하는 연결패턴(16)을 통하여 각기 전기적으로 연결되는 구성을 하고 있다.The upper and lower metal circuit patterns 11 and 12 are electrically connected to each other through a connection pattern 16 penetrating the resin film 15.
그리고, 본 발명을 구성하는 가요성회로기판(10)에 하단금속회로패턴(11)을 형성함에 있어서는 반도체칩(2)이 부착되는 부분(영역)에는 회로패턴을 형성하지 아니 하고 판상(板狀)의 하단금속박막(11a)을 형성하여 효율적인 열방출이 이루어질 수 있도록 할 수 있다. 물론 반도체칩(2)이 부착되는 부분에도 종래와 같이 회로패턴을 형성할 수도 있으나 이는 설계상의 문제라 할 것이다.In forming the lower metal circuit pattern 11 on the flexible circuit board 10 constituting the present invention, the circuit pattern is not formed on the portion (region) to which the semiconductor chip 2 is attached, and is formed in a plate shape. By forming the bottom metal thin film (11a) of the) can be made efficient heat dissipation. Of course, the circuit pattern may be formed on the portion where the semiconductor chip 2 is attached as in the prior art, but this will be referred to as a design problem.
한편, 본 발명에서는 도5를 통하여 다른 실시예를 보여 주고 있다.On the other hand, the present invention shows another embodiment through FIG.
이 가요성회로기판(10)의 구조는 하단금속회로패턴(11)의 상면에 도포된 수지필름(15) 위에 상단금속회로패턴(12)을 인쇄함에 있어서 반도체칩(2)이 부착되는 부분의 수지필름(15) 상면에 판상의 상단 금속박막(12a)이 그대로 부착된 경우를 나타낸 것으로, 동 구조에 의하면 가요성회로기판(10)의 강성을 보다 보강해 줄 수 있게 된다.The structure of the flexible circuit board 10 has a structure in which the semiconductor chip 2 is attached in printing the upper metal circuit pattern 12 on the resin film 15 coated on the upper surface of the lower metal circuit pattern 11. The upper plate metal thin film 12a is attached to the upper surface of the resin film 15 as it is. According to the structure, the rigidity of the flexible circuit board 10 can be further reinforced.
상기 상·하단금속회로패턴(12)(11)은 전기와 열에 대한 전도성이 우수한 금속(예; 구리 등)판을 애칭처리하여 구성되며, 상기 상·하단금속회로패턴(12)(11)의 사이와 하단금속회로패턴(11)에 코팅된 수지필름(15)(14)은 빛을 쪼여 가공할 수 있는 감광수지가 이용된다.The upper and lower metal circuit patterns 12 and 11 are formed by etching a metal (eg, copper) plate having excellent electrical and thermal conductivity, and the upper and lower metal circuit patterns 12 and 11 Resin films 15 and 14 coated on the bottom and the metal circuit pattern 11 between and the photoresist that can be processed by shining light is used.
이와 같은 구성으로 이루어지는 본 발명의 fBGA 반도체패키지는 반도체칩(2)과 솔더볼(6)이 부착되는 가요성회로기판(10)이 2단의 구성을 갖는 상·하단금속회로패턴(12)(11)으로 이루어지기 때문에 가요성회로기판(10) 자체의 강성을 보강할 수 있을 뿐만 아니라 많은 수의 입출력단자를 증설할 수 있으며, 또한 반도체칩(2)이 부착되는 부분의 금속판을 접지단자로 공용할 수 있는 이점이 있다.The fBGA semiconductor package of the present invention having such a configuration includes the upper and lower metal circuit patterns 12 and 11 having the two-stage configuration of the flexible circuit board 10 to which the semiconductor chip 2 and the solder ball 6 are attached. ), Not only can the rigidity of the flexible circuit board 10 itself be reinforced, but also a large number of input / output terminals can be added, and the metal plate of the part where the semiconductor chip 2 is attached is shared as the ground terminal. There is an advantage to this.
이와 같이, 본 발명에 의하면 가요성회로기판(10)의 자체 강성이 보강되어 있기 때문에 별도의 캐리어프레임 없이 가요성회로기판(10)만을 사용하여 fBGA 반도체패키지의 제조가 가능하므로 제조원가를 절감할 수 있고, 나아가 열방출 효과가 뛰어난 고신뢰성의 fBGA 반도체패키지를 제공할 수 있는 것이다.As described above, according to the present invention, since the self-rigidity of the flexible circuit board 10 is reinforced, it is possible to manufacture the fBGA semiconductor package using only the flexible circuit board 10 without a separate carrier frame, thereby reducing the manufacturing cost. In addition, it is possible to provide a highly reliable fBGA semiconductor package with excellent heat dissipation effect.
이상에서 설명한 것은 본 발명에 의한 반도체패키지 구조를 설명하기 위한 하나의 실시예에 불과한 것이며, 본 발명은 상기한 실시예에 한정하지 않고 이하의 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.What has been described above is only one embodiment for explaining the structure of the semiconductor package according to the present invention, the present invention is not limited to the above-described embodiment without departing from the gist of the invention claimed in the following claims Anyone of ordinary skill in the art to which the invention pertains may make various changes.
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| KR10-1999-0021137A KR100388291B1 (en) | 1999-06-08 | 1999-06-08 | Structure of semiconductor package |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
| JPH0883865A (en) * | 1994-09-14 | 1996-03-26 | Citizen Watch Co Ltd | Resin sealed semiconductor device |
| JPH0997860A (en) * | 1995-06-12 | 1997-04-08 | Citizen Watch Co Ltd | Semiconductor device |
| JPH104151A (en) * | 1996-06-17 | 1998-01-06 | Citizen Watch Co Ltd | Semiconductor device and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
| JPH0883865A (en) * | 1994-09-14 | 1996-03-26 | Citizen Watch Co Ltd | Resin sealed semiconductor device |
| JPH0997860A (en) * | 1995-06-12 | 1997-04-08 | Citizen Watch Co Ltd | Semiconductor device |
| JPH104151A (en) * | 1996-06-17 | 1998-01-06 | Citizen Watch Co Ltd | Semiconductor device and its manufacture |
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