KR940022756A - Semiconductor package - Google Patents

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Publication number
KR940022756A
KR940022756A KR1019930003274A KR930003274A KR940022756A KR 940022756 A KR940022756 A KR 940022756A KR 1019930003274 A KR1019930003274 A KR 1019930003274A KR 930003274 A KR930003274 A KR 930003274A KR 940022756 A KR940022756 A KR 940022756A
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KR
South Korea
Prior art keywords
semiconductor
package
semiconductor package
leads
semiconductor chips
Prior art date
Application number
KR1019930003274A
Other languages
Korean (ko)
Other versions
KR960004090B1 (en
Inventor
안승호
김재준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930003274A priority Critical patent/KR960004090B1/en
Publication of KR940022756A publication Critical patent/KR940022756A/en
Application granted granted Critical
Publication of KR960004090B1 publication Critical patent/KR960004090B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

이 발명은 2개의 동일한 메모리용 반도체 칩이 하나의 패키지 몸체에 실장되는 반도체 패키지에 관한 것이다. 여기에서 다이패드가 형성되어 있지 않고 리이드들만 형성되어 있는 리이드 프레임을 사용하여 상기 리이드의 일측상하부에 제1 및 제2반도체 칩을 실장하였다. 이때 제1반도체 칩은 상기 리이드의 일측상부에 실장하여 상기 리이드와 와이어 본딩으로 연결하였으며, 제2반도체 칩은 상하방향으로만 전기적으로 도통되는 이방성 도전층으로 실장하여 상기 리이드와 연결하였다. 그다음 상기 제1 및 제2반도체 칩과 와이어 등을 감싸 보호하도록 몰딩부재로 패키지 몸체를 형성하였다.The present invention relates to a semiconductor package in which two identical memory semiconductor chips are mounted in one package body. Here, the first and second semiconductor chips were mounted on one side of the lead by using a lead frame having no die pad and only leads. In this case, the first semiconductor chip is mounted on one side of the lead and connected to the lead by wire bonding, and the second semiconductor chip is mounted with an anisotropic conductive layer electrically connected only in the up and down direction to connect with the lead. Then, the package body was formed of a molding member to surround and protect the first and second semiconductor chips and wires.

따라서 동일한 두 개의 메모리용 반도체 칩을 하나의 반도체 패키지에 실장하므로 별도의 밀러 칩이 필요치 않아 패키지의 연구 및 생산에 필요한 시간 및 경비를 절감할 수 있으며, 용이하게 메모리 용량을 증가시킬 수 있다.Therefore, since the same two semiconductor chips for memory are mounted in a single semiconductor package, a separate Miller chip is not required, thereby reducing the time and cost required for research and production of the package, and easily increasing the memory capacity.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 수지봉지형 반도체 패키지의 일부 단면을 포함하는 사시도.1 is a perspective view including a partial cross section of a general resin-encapsulated semiconductor package.

제2도는 종래 적층형 반도체 패키지의 실시예의 단면도.2 is a cross-sectional view of an embodiment of a conventional stacked semiconductor package.

제3도는 이 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도.3 is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

제4도는 이 발명에 따른 반도체 패키지의 다른 실시예를 나타내는 단면도이다.4 is a cross-sectional view showing another embodiment of a semiconductor package according to the present invention.

Claims (6)

두 개의 반도체 칩을 하나의 패키지 몸체내에 수용하는 반도체 패키지에 있어서, 일정간격으로 형성되어 일측의 상부에 제1반도체 칩의 배면이 실장되어 있는 리이드들과, 상기 제1반도체 칩의 본딩패드들과 리이드를 연결하는 와이어들과, 상기 제1반도체 칩이 실장되어 있는 리이드들의 하부에 접착되어 상하 방향으로만 전기적으로 도통되는 이방성 도전층과, 상기 제1반도체 칩과 대응되도록 형성되어 상기 이방성 도전층의 하부에 정면이 실장되어 있는 제2반도체 칩과, 상기 제1 및 제2반도체 칩과 와이어를 보호하는 패키지 몸체를 구비하여 되는 반도체 패키지.In a semiconductor package that accommodates two semiconductor chips in one package body, leads are formed at a predetermined interval and the back surface of the first semiconductor chip is mounted on an upper side of the semiconductor package, bonding pads of the first semiconductor chip, and Wires connecting the leads, anisotropic conductive layers that are electrically attached to the lower portions of the leads on which the first semiconductor chips are mounted, and are electrically conductive only in the vertical direction, and are formed to correspond to the first semiconductor chips, and thus form the anisotropic conductive layers. And a second semiconductor chip having a front surface mounted on a lower portion thereof, and a package body protecting the first and second semiconductor chips and wires. 제1항에 있어서, 상기 제1반도체 칩이 폴리 이미드등과 같은 재질의 절연테이프상에 실장되어 상기 리이드들의 일측상부에 실장되는 반도체 패키지.The semiconductor package of claim 1, wherein the first semiconductor chip is mounted on an insulating tape made of a material such as polyimide to be mounted on one side of the leads. 제1항에 있어서, 상기 이방성 도전층이 신축성을 갖는 주재료와 도전물질의 분말이 배합되어 고르게 분포되어 있는 층으로 형성되어 있는 반도체 패키지.The semiconductor package according to claim 1, wherein the anisotropic conductive layer is formed of a layer in which the main material having elasticity and the powder of the conductive material are mixed and evenly distributed. 제1항에 있어서, 상기 이방성 도전층은 상기 제2반도체 칩의 본딩패드에 대응되는 부분에 관통공이 형성되어 있는 절연박막과 상기 관통공의 내부 및 외부에 상하 방향으로 도통되도록 형성되어 있는 도전기등을 구비하여 되는 반도체 패키지.The method of claim 1, wherein the anisotropic conductive layer is an insulating thin film having a through hole formed in a portion corresponding to the bonding pad of the second semiconductor chip, and a conductive device which is formed to be conducted in the vertical direction to the inside and the outside of the through hole. The semiconductor package is provided. 제4항에 있어서, 상기 도전기둥은 신축성을 갖는 기둥의 외부표면에 도전층이 도포되어 있는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 4, wherein the conductive pillar is coated with a conductive layer on an outer surface of the elastic pillar. 제1항에 있어서, 상기 패키지 몸체가 에폭시 몰딩 컴파운드로 수지 성형되어 형성되어 있는 반도체 패키지.The semiconductor package of claim 1, wherein the package body is formed by resin molding with an epoxy molding compound. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003274A 1993-03-05 1993-03-05 Semiconductor package KR960004090B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003274A KR960004090B1 (en) 1993-03-05 1993-03-05 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003274A KR960004090B1 (en) 1993-03-05 1993-03-05 Semiconductor package

Publications (2)

Publication Number Publication Date
KR940022756A true KR940022756A (en) 1994-10-21
KR960004090B1 KR960004090B1 (en) 1996-03-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930003274A KR960004090B1 (en) 1993-03-05 1993-03-05 Semiconductor package

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Publication number Publication date
KR960004090B1 (en) 1996-03-26

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