KR0163524B1 - Ball grid array package formed conducting pattern on the inner face of cap type package body - Google Patents
Ball grid array package formed conducting pattern on the inner face of cap type package body Download PDFInfo
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- KR0163524B1 KR0163524B1 KR1019950040242A KR19950040242A KR0163524B1 KR 0163524 B1 KR0163524 B1 KR 0163524B1 KR 1019950040242 A KR1019950040242 A KR 1019950040242A KR 19950040242 A KR19950040242 A KR 19950040242A KR 0163524 B1 KR0163524 B1 KR 0163524B1
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- Prior art keywords
- package body
- grid array
- ball grid
- lid
- circuit board
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 덮개형 패키지 몸체의 양측 말단부가 연쇄회로기판과 접착되어 있고, 그 덮개형 패키지 몸체의 내측면에 도전성 패턴들이 형성되어 있으며, 반도체 칩과 인쇄회로기판이 전기적 연결이 덮개형 패키지 몸체의 내측면에 형성된 도전성 패턴들로 전기적 연결된 볼 그리드 어레이 패키지를 제공함으로써, 덮개형 패키지 몸체를 이용한 볼 그리드 어레이 패키지 제조공정중에서 와이어 본딩공정과 덮개형 패키지 몸체로 봉지하는 공정을 동시에 실시하여 공정을 단순화하는 효과를 나타낸다.According to an embodiment of the present invention, both ends of the lid package body are bonded to the circuit board, and conductive patterns are formed on the inner surface of the lid package body, and the semiconductor chip and the printed circuit board are electrically connected to each other. By providing a ball grid array package electrically connected with conductive patterns formed on the inner surface, the wire bonding process and the encapsulation process are performed simultaneously during the ball grid array package manufacturing process using the cover type package body to simplify the process. It shows the effect.
Description
제1도는 종래 기술에 따른 금속덮개형 패키지 몸체를 갖는 볼 그리드 어레이(Ball Grid Array)패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a ball grid array package having a metal lid-shaped package body according to the prior art.
제2도는 본 발명에 따른 금속덮개형 패키지 몸체를 갖는 볼 그리드 어레이 패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a ball grid array package having a metal lid package body according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 인쇄회로기판 12,13,94 : 도전성 패턴10: printed circuit board 12, 13, 94: conductive pattern
14 : 본딩패턴 20 : 접착제14: bonding pattern 20: adhesive
30 : 반도체 칩 32 : 본딩패드30: semiconductor chip 32: bonding pad
40 : 금선 50,80 : 금속덮개형 패키지 몸체40: gold wire 50,80: metal cover type package body
60 : 에폭시 봉지재 70 : 솔더 볼60: epoxy encapsulant 70: solder ball
72 : 솔더 레지스트 90 : 플랙시블 써킷(flexible circuit)72 solder resist 90 flexible circuit
92 : 폴리이미드 비전도성 소재92: polyimide non-conductive material
본 발명은 볼 그리드 어레이 패키지에 관한 것으로, 더욱 상세하게는 와이어 본딩과 덮개형 패키지 몸체 부착이 동시에 가능하도록 하기 위하여 덮개형 패키지 몸체의 내측면에 도전성 패턴이 형성되어 있으며, 그 도전성 패턴에 의해 반도체 칩과 인쇄회로기판의 전기적인 연결이 이루어지는 볼 그리드 어레이 패키지에 관한 것이다.The present invention relates to a ball grid array package, and more particularly, a conductive pattern is formed on the inner surface of the lid-shaped package body in order to enable wire bonding and the lid-shaped package body to be attached at the same time. The present invention relates to a ball grid array package in which electrical connection between a chip and a printed circuit board is made.
최근에 볼 그리드 어레이(Ball Grid Array)라 불리어지는 새로운 플라스틱 패키지는 고집적 또는 리드프레임이 없는 실장 패키지로서 각광을 받고 있다. 볼 그리드 어레이 반도체 패키지는 랜드 패턴 등과 같은 풋프린트(Footpring) 영역이 작기 때문에 고집적 실장이 가능하고, 외부단자와 연결되는 리드 대신 솔더 (Solder Ball)을 사용함으로써, 리드의 휨 또는 비틀림 등으로 인한 수율 손실이 적고, 반복적인 조립 공정 및 큰 배치 공차로 인하여 제품의 생산량을 증가시킬 수 있으며, 종래의 실장 장치를 사용함으로써, 장비의 추가적인 도입이 요구되지 않는 장점이 있다.Recently, a new plastic package called Ball Grid Array has been in the spotlight as a highly integrated or leadframe-free package. The ball grid array semiconductor package has a small footprint area such as a land pattern, which enables high-density mounting, and the use of solder balls instead of leads connected to external terminals, resulting in bending or twisting of leads. It is advantageous in that the losses are low, the production of products can be increased due to repetitive assembly processes and large batch tolerances, and by using a conventional mounting apparatus, additional introduction of equipment is not required.
또한 기계적 강도와 열전도도를 향상하기 위하여 에폭시 성형 수지로 패키지 몸체를 형성하지 않고 덮개 형태의 패키지 몸체를 갖는 볼 그리드 어레이 패키지에 대한 연구가 활발히 진행되고 있으며, 그 덮개 형태의 패키지 몸체는 금속이 사용되어지는 것이 일반적이다.Also, in order to improve the mechanical strength and thermal conductivity, research on the ball grid array package having a cover body without forming the package body with epoxy molding resin is actively conducted, and the cover body package is made of metal. It is common to be.
제1도는 종래의 금속덮개형 패키지 몸체를 갖는 볼 그리드 어레이 패키지의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a ball grid array package having a conventional metal lid package body.
제1도를 참조하면, 인쇄회로기판(10)의 내부에 다층으로 도전성 패턴(12)들이 형성되어 있으며, 그 인쇄회로기판(10)의 상부면에는 반도체 칩(30)과의 전기적 연결을 위한 본딩 패턴(14)들이 형성되어 있고 하부면에는 외부로의 전기적 연결을 위하여 도전성 패턴(13)이 형성되어 있다. 그 인쇄회로기판(10)의 상부면에는 반도체 칩(30)이 접착제(20)로 접착되어 있으며, 그 반도체 칩(30)의 상면의 본딩패드(32)가 형성되어 있다. 그 본딩패드(32)와 인쇄회로기판(10)의 상부면에 형성된 본딩패턴(14)들은 금선(40)으로 와이어 본딩(wire bonding)되어 있다. 인쇄회로기판(10)의 상부면에는형상의 금속덮개형 패키지 몸체(50)가 그 양측 말단부가 에폭시 봉지재(60)로 인쇄회로기판(10)의 상부면에 접착되어 있다. 인쇄회로기판(10)의 하부면에 형성된 도전성 패턴(13)을 보호하기 위하여 솔더 레지스트(solder resist; 72)가 그 인쇄회로기판(10)의 하부면상에 솔더 볼(70)의 접착을 위한 영역을 제외하여 도포되어 있다. 반도체 칩(30)과 외부장치와의 전기적 연결을 위하여 솔더 볼(7)이 그 인쇄회로기판(10)의 하부면상의 도전성 패턴(13)과 전기적으로 연결되도록 부착되어 있다.Referring to FIG. 1, conductive patterns 12 are formed in a multilayered manner in a printed circuit board 10, and an upper surface of the printed circuit board 10 is used for electrical connection with a semiconductor chip 30. Bonding patterns 14 are formed and a conductive pattern 13 is formed on the lower surface for electrical connection to the outside. The semiconductor chip 30 is bonded to the upper surface of the printed circuit board 10 with an adhesive 20, and a bonding pad 32 on the upper surface of the semiconductor chip 30 is formed. The bonding pads 32 and the bonding patterns 14 formed on the upper surface of the printed circuit board 10 are wire bonded with gold wires 40. The upper surface of the printed circuit board 10 Both ends of the metal lid-shaped package body 50 having a shape are bonded to the upper surface of the printed circuit board 10 by an epoxy encapsulant 60. In order to protect the conductive pattern 13 formed on the lower surface of the printed circuit board 10, a solder resist 72 is an area for bonding the solder balls 70 to the lower surface of the printed circuit board 10. It is applied except. In order to electrically connect the semiconductor chip 30 and an external device, a solder ball 7 is attached to be electrically connected to the conductive pattern 13 on the lower surface of the printed circuit board 10.
상기와 같은 구조를 갖는 볼 그리드 어레이 패키지는 와이어 본딩공정과 덮개형 패키지 몸체로 봉지되는 공정이 분리되어 실시되고 있으나 대량생산에 따른 공정의 단순화의 필요성이 더욱 증가되고 실정에 있어서 보다 공정을 단순화할 수 있는 또 다른 방안의 개발이 필요한 실정이다.In the ball grid array package having the above structure, the wire bonding process and the encapsulation process are encapsulated separately, but the necessity of simplification of the process due to mass production is further increased and the process may be simplified. There is a need for the development of another plan.
따라서 본 발명의 목적은 기존의 덮개형 패키지 몸체를 이용한 볼 그리드 어레이 패키지 제조공정중에서 와이어 본딩공정과 덮개형 패키지 몸체로 봉지하는 공정을 동시에 진행함으로써 공정의 단순화가 가능한 볼 그리드 어레이 패키지를 제공하는 것이다.Accordingly, an object of the present invention is to provide a ball grid array package capable of simplifying the process by simultaneously performing a wire bonding process and a process of encapsulating with a cover type package body in a ball grid array package manufacturing process using a conventional cover type package body. .
이와 같은 목적을 달성하기 위한 본 발명의 특징은 덮개형 패키지 몸체의 양측 말단부가 인쇄회로기판과 접착되어 있고, 그 덮개형 패키지 몸체의 내측면에 도전성 패턴들이 형성되어 있으며, 반도체 칩과 인쇄회로기판이 덮개형 패키지 몸체의 내측면에 형성된 도전성 패턴들로 전기적으로 연결된 것을 특징으로 한다.Features of the present invention for achieving the above object is that both ends of the lid-shaped package body is bonded to the printed circuit board, the conductive patterns are formed on the inner surface of the lid-shaped package body, the semiconductor chip and the printed circuit board It is characterized in that it is electrically connected to the conductive patterns formed on the inner side of the lid-shaped package body.
이하, 첨부 도면을 참조하여 본 발명에 의한 덮개형 패키지 몸체의 내측면에 도전성 패턴이 형성된 덮개형 볼 그리드 어레이 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a cover type ball grid array package having a conductive pattern formed on an inner surface of the cover type package body according to the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 의한 금속덮개형 패키지 몸체를 갖는 볼 그리드 어레이 패키지의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a ball grid array package having a metal lid package body according to the present invention.
제2도를 참조하면, 반도체 칩(30)이 접착제(20)로 인쇄회로기판(10)의 상면에 접착되어 있다. 그 인쇄회로기판(10)의 내부에는 다층의 도전성 패턴(12)이 형성되어 있고 상부면에는 반도체 칩(30)과의 전기적 접속을 위하여 본딩패턴(14)이 형성되어 있으며, 하부면에는 솔더 볼(70)과의 접착을 위한 도전성 패턴(13)이 형성되어 있으며, 그 도전성 패턴(13)에 솔더 볼(7)이 접착되어 있다. 인쇄회로기판(10)의 하부면에는 도전성 패턴(12)들을 보호하기 위하여 솔더 볼(70)이 접착되는 영역을 제외하여 솔더 레지스트(72)가 도포되어 있다.Referring to FIG. 2, the semiconductor chip 30 is adhered to the upper surface of the printed circuit board 10 with an adhesive 20. The multilayer conductive pattern 12 is formed in the printed circuit board 10, and a bonding pattern 14 is formed on the upper surface for electrical connection with the semiconductor chip 30. A conductive pattern 13 for bonding with 70 is formed, and a solder ball 7 is bonded to the conductive pattern 13. A solder resist 72 is applied to the lower surface of the printed circuit board 10 except for a region to which the solder balls 70 are bonded to protect the conductive patterns 12.
반도체 칩(30)의 상부에 형성된 본딩패드(32)가 인쇄회로기판(10)의 상부면에 금선(도시 안됨)으로 와이어 본딩된 후 와이어 절단장치(도시 안됨)를 이용하여 본딩패드(32)와 접착된 금선(도시 안됨)의 목 부위가 절단되어 금주(金柱; stud;16)가 형성되어 있다. 폴리이미드 비전도성 소재(92)의 내부에 도전성 패턴(94)을 갖는 플랙시블 써킷(flexible circuit; 90)이 내측면에 부착된 금속덮개형 패키지 몸체(80)를 본딩패드(32) 상면에 형성된 금주(16)와 인쇄회로기판(10)의 본딩패턴(14)과 각각 대응하도록 하여 금속덮개형 패키지 몸체(80)의 가장자리 부분이 에폭시 봉지재(60)로 인쇄회로기판(10)에 접착되어 있다. 상기 플랙시블 써킷(90)은 유연성과 접착성을 가지고 있어서 덮개형 패키지 몸체(80)의 내측면의 절곡부위에 용이하게 접착될 수 있다. 덮개형 패키지 몸체(80)는 인쇄회로기판(10)에 부착될 때 그 플랙시블 써킷(90)의 양측 말단부의 도전성 패턴(94)이 반도체 칩(30)의 금주(16)와 인쇄회로기판(30)의 본딩패턴(13)에 각각 대응하여 접착될 수 있도록 하는 형상을 가지고 있다.The bonding pad 32 formed on the semiconductor chip 30 is wire-bonded to the upper surface of the printed circuit board 10 with gold wires (not shown), and then the bonding pads 32 are formed using a wire cutting device (not shown). The neck portion of the gold wire (not shown) bonded with the slit is cut to form a stud 16. A metal circuit package body 80 having a flexible circuit 90 having a conductive pattern 94 inside the polyimide nonconductive material 92 attached to an inner side thereof is formed on the upper surface of the bonding pad 32. The edge portions of the metal lid package body 80 are bonded to the printed circuit board 10 by the epoxy encapsulant 60 so as to correspond to the bonding patterns 14 of the abutment 16 and the printed circuit board 10, respectively. have. The flexible circuit 90 has flexibility and adhesiveness, so that the flexible circuit 90 can be easily bonded to the bent portion of the inner surface of the lid-shaped package body 80. When the lid-shaped package body 80 is attached to the printed circuit board 10, the conductive patterns 94 at both ends of the flexible circuit 90 may have the tab 16 of the semiconductor chip 30 and the printed circuit board ( Each of the bonding patterns 13 of FIG. 30 has a shape so as to be bonded to each other.
이상 설명한 것처럼 본 발명은 도전성 패턴을 패키지 몸체 내측면에 형성 시키고 그 도전성 패턴을 비전도성 재료로 둘러싸도록 하여 패키지 몸체 내측면에 형성시킴으로써, 덮개형 패키지 몸체로 봉지공정을 진행시 와이어 본딩까지 동시에 진행될 수 있다.As described above, the present invention forms a conductive pattern on the inner surface of the package body and surrounds the conductive pattern with a non-conductive material to form the inner surface of the package body, thereby simultaneously proceeding to wire bonding during the encapsulation process with the lid type package body. Can be.
상기 덮개형 패키지 몸체의 내측면에 형성된 도전성 패턴은 비전도성 소재의 외부로 노출되도록 도전성 패턴이 형성되어 있는 것을 기술하였으나 플랙시블 써킷의 도전성 패턴 일측이 반도체 칩상의 본딩패드와 대응하고 다른 일측이 인쇄회로기판의 도전성 패턴과 대응하도록 전기적으로 연결되는 범위에서 그 변형이 가능하다. 또한 패키지 몸체의 형상은 그 내측면에 부착된 플랙시블 써킷의 도전성 패턴의 양측 말단부가 각각 반도체 칩과 인쇄회로기판의 본딩패턴에 대응하도록 하는 범위에서 변형 실시될 수 있다.The conductive pattern formed on the inner surface of the lid package body is described that the conductive pattern is formed so as to be exposed to the outside of the non-conductive material, but one side of the conductive circuit of the flexible circuit corresponds to the bonding pad on the semiconductor chip and the other side is printed The modification is possible in the range electrically connected to correspond to the conductive pattern of the circuit board. In addition, the shape of the package body may be modified in a range such that both ends of the conductive pattern of the flexible circuit attached to the inner surface thereof correspond to the bonding pattern of the semiconductor chip and the printed circuit board, respectively.
따라서, 본 발명에 의한 덮개형 패키지 몸체의 내측에 도전성 패턴이 형성된 덮개형 반도체 칩 패키지에 따르면, 금속덮개형 패키지 몸체를 이용한 반도체 칩 패키지 제조공정중에서 와이어 본딩공정과 금속덮개형 패키지 몸체로 봉지하는 공정을 동시에 실시하여 공정의 단순화가 가능한 이점(利點)이 있다.Therefore, according to the lid type semiconductor chip package in which the conductive pattern is formed inside the lid type package body according to the present invention, the semiconductor chip package manufacturing process using the metal lid type package body is encapsulated with the wire bonding process and the metal lid type package body. There is an advantage that the process can be performed simultaneously to simplify the process.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950040242A KR0163524B1 (en) | 1995-11-08 | 1995-11-08 | Ball grid array package formed conducting pattern on the inner face of cap type package body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950040242A KR0163524B1 (en) | 1995-11-08 | 1995-11-08 | Ball grid array package formed conducting pattern on the inner face of cap type package body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970030532A KR970030532A (en) | 1997-06-26 |
| KR0163524B1 true KR0163524B1 (en) | 1999-02-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950040242A KR0163524B1 (en) | 1995-11-08 | 1995-11-08 | Ball grid array package formed conducting pattern on the inner face of cap type package body |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0163524B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100112753A (en) * | 2009-04-10 | 2010-10-20 | 삼성전자주식회사 | Solid state drive, device for mounting solid state drives and computing system |
-
1995
- 1995-11-08 KR KR1019950040242A patent/KR0163524B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100112753A (en) * | 2009-04-10 | 2010-10-20 | 삼성전자주식회사 | Solid state drive, device for mounting solid state drives and computing system |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970030532A (en) | 1997-06-26 |
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