KR100525091B1 - semiconductor package - Google Patents
semiconductor package Download PDFInfo
- Publication number
- KR100525091B1 KR100525091B1 KR10-2001-0087262A KR20010087262A KR100525091B1 KR 100525091 B1 KR100525091 B1 KR 100525091B1 KR 20010087262 A KR20010087262 A KR 20010087262A KR 100525091 B1 KR100525091 B1 KR 100525091B1
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- South Korea
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- chip
- semiconductor chip
- conductive tape
- lead frame
- bonding wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
본 발명은 리드프레임을 칩패드의 위치에 관계없이 모든 타입의 반도체 칩에 적용할 수 있는 반도체 패키지에 관해 개시한다.The present invention discloses a semiconductor package that can be applied to all types of semiconductor chips regardless of the position of the chip pad.
개시된 본 발명의 반도체 패키지는 상면에 다수개의 칩패드를 가진 반도체 칩과, 칩패드와 전기적으로 연결되는 리드프레임과, 반도체 칩 및 리드프레임의 사이에 개재되어 반도체 칩과 리드프레임을 전기적으로 연결시키는 도전 테이프와, 반도체 칩 및 도전 테이프를 감싸는 몰딩체를 포함한다.The disclosed semiconductor package includes a semiconductor chip having a plurality of chip pads on an upper surface thereof, a lead frame electrically connected to the chip pads, and interposed between the semiconductor chip and the lead frame to electrically connect the semiconductor chip and the lead frame. A conductive tape, and a molding body surrounding the semiconductor chip and the conductive tape are included.
Description
본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 리드프레임을 칩패드의 위치에 관계없이 모든 타입의 반도체 칩에 적용할 수 있는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly to a semiconductor package that can be applied to all types of semiconductor chips regardless of the position of the chip pad.
도 1 및 도 2는 종래의 제 1실시예를 설명하기 위한 도면으로, 칩 패드가 반도체 칩의 센터 부분에 배열된 구조를 가진 엘오씨(Lead On Chip) 타입의 반도체 패키지의 평면도 및 단면도이다.1 and 2 are views for explaining a first exemplary embodiment, which is a plan view and a cross-sectional view of a lead-on-chip type semiconductor package having a structure in which chip pads are arranged at a center portion of a semiconductor chip.
종래의 제 1실시예에 따른 반도체 패키지는, 도 1 및 도 2에 도시된 바와 같이, 칩패드(12)가 센터 부분에 배열된 반도체 칩(10)과, 칩패드(12)와 전기적으로 연결되는 리드프레임(16)과, 칩패드(12)와 리드프레임(16)을 연결시키는 본딩와이어(14)와, 상기 반도체 칩(10) 및 본딩와이어(14)를 감싸는 몰딩체(20)로 구성된다.As shown in FIGS. 1 and 2, the semiconductor package according to the first exemplary embodiment may be electrically connected to the semiconductor chip 10 having the chip pads 12 arranged at a center portion thereof, and to the chip pads 12. A lead frame 16, a bonding wire 14 connecting the chip pad 12 and the lead frame 16, and a molding body 20 surrounding the semiconductor chip 10 and the bonding wire 14. do.
도 3 및 도 4는 종래의 제 2실시예를 설명하기 위한 도면으로, 칩 패드가 반도체 칩의 가장자리 부분에 배열된 반도체 패키지의 평면도 및 단면도이다.3 and 4 are diagrams for explaining a second embodiment of the present invention, which is a plan view and a cross-sectional view of a semiconductor package in which chip pads are arranged at edge portions of a semiconductor chip.
종래의 제 2 실시예에 따른 반도체 패키지는, 도 3 및 도 4에 도시된 바와 같이, 다수개의 칩패드(32)가 가장자리 부분에 배열된 반도체 칩(30)과, 칩패드(32)와 전기적으로 연결되는 리드프레임(36)과, 칩패드(32)와 리드프레임(36)을 연결시키는 본딩와이어(34)와, 상기 반도체 칩(30) 및 본딩와이어(34)를 감싸는 몰딩체(40)로 구성된다. 도면부호 38은 반도체 칩의 안착부를 도시한 것이다.In the semiconductor package according to the second embodiment of the present invention, as illustrated in FIGS. 3 and 4, the semiconductor chip 30 having a plurality of chip pads 32 arranged at an edge portion thereof, and the chip pads 32 electrically connected to each other. A lead wire 36 connected to the lead frame, a bonding wire 34 connecting the chip pad 32 and the lead frame 36, and a molding body 40 surrounding the semiconductor chip 30 and the bonding wire 34. It consists of. Reference numeral 38 shows a mounting portion of the semiconductor chip.
그러나, 종래의 제 1실시예에서의 리드프레임은 최초 성형 시부터 패드가 센터 부분에 배열된 반도체 칩만이 적용가능하도록 제작된 것이며, 종래의 제 2실시예에서의 리드프레임은 칩패드가 가장자리 부분에 배열된 반도체 칩만이 적용가능하도록 제작된 것이다. 따라서, 반도체 칩의 칩패드가 센터 부분에 배열되는지 또는 가장자리 부분에 배열되는 지 등의 반도체 칩 다지인에 따라 각기 다른 리드프레임을 적용해야 했다. 따라서, 반도체 칩의 디자인에 따라 매번 새로운 리드프레임을 제작해야 하기 때문에 패키지 제작 비용이 상승되고 번거로운 문제점이 있었다.However, the lead frame in the first embodiment of the present invention is manufactured so that only a semiconductor chip in which the pads are arranged in the center portion is applicable to the lead frame from the first molding. Only semiconductor chips arranged in the above are manufactured to be applicable. Therefore, different lead frames have to be applied depending on the semiconductor chip design, such as whether the chip pads of the semiconductor chip are arranged at the center part or the edge part. As a result, a new leadframe has to be manufactured every time according to the design of the semiconductor chip, thereby increasing the package manufacturing cost and the cumbersome problem.
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이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 리드프레임과 반도체 칩 사이에 도전 테이프를 개재시키고, 반도체 칩과 도전테이프를 연결하는 제 1본딩와이어 및 리드프레임과 도전테이프를 연결하는 제 2본딩와이어를 포함하여, 결과적으로 도전테이프를 매개로 리드프레임과 반도체 칩을 연결시킨 구조를 가짐으로써, 칩패드가 반도체 칩 상면 센터 부분에 배열되던지 그 가장자리 부분에 배열되던지 배열 위치에 상관없이 모든 반도체 칩에 적용가능한 반도체 패키지를 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the first bonding wire for connecting the semiconductor chip and the conductive tape and the conductive tape interposed between the lead frame and the semiconductor chip, and connecting the lead frame and the conductive tape. Including a second bonding wire, as a result, the structure of connecting the lead frame and the semiconductor chip through the conductive tape, the chip pad is arranged in the center portion of the upper surface of the semiconductor chip, or arranged at the edge portion thereof It is an object of the present invention to provide a semiconductor package that can be applied to any semiconductor chip regardless.
상기 목적을 달성하기 위해, 본 발명의 반도체 패키지는 리드프레임과, 리드프레임의 하부에 배치되며 상면 센터부분에 다수개의 칩패드를 가진 반도체 칩과, 리드프레임과 반도체 칩 사이에 개재되며 칩패드를 노출시키는 도전 테이프와, 칩패드와 도전테이프를 전기적으로 연결시키는 제 1본딩와이어와, 도전테이프와 리드프레임을 전기적으로 연결시키는 제 2본딩와이어와, 반도체 칩, 도전 테이프, 제 1본딩와이어 및 제 2본딩와이어를 감싸는 몰딩체를 포함하여 구성되는 것을 특징으로 한다. 본 발명의 반도체 패키지는 리드프레임과, 리드프레임 상부에 배치되며 상면 가장자리 부분에 다수개 배열된 칩패드를 가진 반도체 칩과, 리드프레임과 반도체 칩 사이에 개재된 도전 테이프와, 칩패드와 상기 도전 테이프를 전기적으로 연결시키는 제 1본딩와이어와, 도전 테이프와 상기 리드프레임을 전기적으로 연결시키는 제 2본딩와이어와, 반도체 칩, 도전 테이프, 제 1본딩와이어 및 제 2본딩와이어를 감싸는 몰딩체를 포함한 것을 특징으로 한다.In order to achieve the above object, the semiconductor package of the present invention is a semiconductor chip having a lead frame, a semiconductor chip having a plurality of chip pads disposed in a lower portion of the lead frame and interposed between the lead frame and the semiconductor chip. An exposed conductive tape, a first bonding wire electrically connecting the chip pad and the conductive tape, a second bonding wire electrically connecting the conductive tape and the lead frame, a semiconductor chip, a conductive tape, a first bonding wire, and a first bonding wire. It characterized in that it comprises a molding body surrounding the two bonding wires. The semiconductor package of the present invention includes a semiconductor chip having a lead frame, a chip pad disposed on the lead frame and arranged in a plurality of upper edges thereof, a conductive tape interposed between the lead frame and the semiconductor chip, the chip pad and the conductive material. A first bonding wire electrically connecting the tape, a second bonding wire electrically connecting the conductive tape and the lead frame, and a molding body surrounding the semiconductor chip, the conductive tape, the first bonding wire, and the second bonding wire. It is characterized by.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 5및 6은 본 발명의 제 1실시예에 따른 반도체 패키지의 평면도 및 단면도로서, 센터 부분에 칩패드가 배열된 반도체 칩을 적용한 경우를 예로 하여 설명한다. 본 발명의 제 1실시예에 따른 반도체 패키지는, 도 5 및 도 6에 도시된 바와 같이, 리드프레임(160)과, 리드프레임(160)의 하부에 배치되며 상면 센터부분에 다수개의 칩패드(미도시)를 가진 반도체 칩(100)과, 리드프레임(150)과 반도체 칩(100) 사이에 개재되며 칩패드를 노출시키는 도전 테이프(150)와, 칩패드와 도전테이프(150)를 전기적으로 연결시키는 제 1본딩와이어(140)와, 도전테이프(150)와 리드프레임(160)을 전기적으로 연결시키는 제 2본딩와이어(142)와, 반도체 칩(100), 도전 테이프(150), 제 1본딩와이어(140) 및 제 2본딩와이어(142)를 감싸는 몰딩체(120)를 포함하여 구성된다. 상기 도전 테이프(150)로는 탭(tap)테이프를 사용하며, 여기서, 도전테이프(150) 대신에 PCB(Printed Circuit Board)를 사용할 수도 있다. 상기 도전테이프(150)와 리드프레임(160) 사이에 접착제(152)를 개재시켜 이들 간의 접착력을 향상시킬 수도 있다. 5 and 6 are a plan view and a cross-sectional view of a semiconductor package according to a first embodiment of the present invention, which will be described using an example in which a semiconductor chip in which chip pads are arranged in a center portion is applied. As shown in FIGS. 5 and 6, the semiconductor package according to the first embodiment of the present invention includes a lead frame 160 and a plurality of chip pads disposed at a lower portion of the lead frame 160 and disposed at an upper center portion thereof. The semiconductor chip 100 having the semiconductor chip 100, the conductive tape 150 interposed between the lead frame 150 and the semiconductor chip 100 and exposing the chip pads, and the chip pads and the conductive tape 150 are electrically connected to each other. The first bonding wire 140 to be connected, the second bonding wire 142 to electrically connect the conductive tape 150 and the lead frame 160, the semiconductor chip 100, the conductive tape 150, the first It is configured to include a molding body 120 surrounding the bonding wire 140 and the second bonding wire 142. A tap tape is used as the conductive tape 150, and instead of the conductive tape 150, a printed circuit board (PCB) may be used. An adhesive 152 may be interposed between the conductive tape 150 and the lead frame 160 to improve adhesion between the conductive tape 150 and the lead frame 160.
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도 5및 도 6은 상면 센터 부분에 다수개의 칩패드가 배열된 반도체 칩을 적용한 경우로서, 반도체 칩(100)과 리드프레임(160) 사이에 도전테이프(150)가 개재되되 반도체 칩(100)이 도전테이프(150)의 하부에 배치되며, 제 1본딩와이어(140)에 의해 반도체 칩(100)의 칩패드와 도전 테이프(150)가 연결되고, 또한 제 2본딩 와이어(142)에 의해 도전 테이프(150)와 리드프레임(160)이 연결된 구조를 가진다. 한편, 도 5및 도 6에서는, 상면 센터 부분에 다수개의 칩패드가 배열된 반도체 칩을 예로 하였으나, 가장자리 부분에 칩패드가 배열된 반도체 칩을 적용할 수도 있다. 즉, 가장자리 부분에 칩패드가 배열된 반도체 칩을 적용한 경우, 도면에 도시되지는 않았지만, 도전테이프 상부에 반도체 칩이 배치되고, 제 1본딩와이어에 의해 반도체 칩의 칩패드와 도전 테이프가 연결되고, 또한 제 2본딩 와이어에 의해 도전 테이프와 리드프레임이 연결된 구조를 가진다. 상술한 바와 같이, 본 발명의 제 1실시예에서는, 도전테이프를 매개로 리드프레임과 반도체 칩을 연결시킨 패키지 구조를 가짐으로써, 칩패드가 반도체 칩 상면 센터 부분에 배열되던지 그 가장자리 부분에 배열되던지 배열 위치에 상관없이 모든 반도체 칩에 적용가능하다.5 and 6 illustrate a case in which a semiconductor chip in which a plurality of chip pads are arranged in an upper center portion is formed, and a conductive tape 150 is interposed between the semiconductor chip 100 and the lead frame 160, but the semiconductor chip 100 is disposed. The lower portion of the conductive tape 150 is disposed, the chip pad of the semiconductor chip 100 and the conductive tape 150 are connected by the first bonding wire 140, and are electrically conductive by the second bonding wire 142. The tape 150 and the lead frame 160 have a structure connected thereto. Meanwhile, in FIGS. 5 and 6, a semiconductor chip in which a plurality of chip pads are arranged in an upper surface center part is taken as an example, but a semiconductor chip in which chip pads are arranged in an edge part may be used. That is, in the case of applying a semiconductor chip in which the chip pads are arranged at the edges, although not shown in the drawing, the semiconductor chip is disposed on the conductive tape, and the chip pad of the semiconductor chip and the conductive tape are connected by the first bonding wire. In addition, the conductive tape has a structure in which the lead frame is connected by the second bonding wire. As described above, in the first embodiment of the present invention, by having a package structure in which a lead frame and a semiconductor chip are connected through a conductive tape, the chip pads are arranged at the center portion of the upper surface of the semiconductor chip or at the edge portion thereof. It is applicable to all semiconductor chips regardless of the arrangement position.
도 7 및 도 8은 본 발명의 제 2실시예에 따른 반도체 패키지의 평면도 및 단면도로서, 가장자리 부분에 칩패드가 배열된 반도체 칩을 적용한 경우를 예로 하여 설명한다. 본 발명의 제 2실시예에 따른 반도체 패키지는, 도 7 및 도 8에 도시된 바와 같이, 리드프레임(260)과, 리드프레임(260) 상부에 배치되며 상면 가장자리 부분에 다수개 배열된 칩패드를 가진 반도체 칩(200)과, 리드프레임(260)과 반도체 칩(200) 사이에 개재된 도전 테이프(250)와, 칩패드와 도전 테이프(250)를 전기적으로 연결시키는 제 1본딩와이어(240)와, 도전 테이프(250)와 리드프레임(260)을 전기적으로 연결시키는 제 2본딩와이어(242)와, 반도체 칩(200), 도전 테이프(250), 제 1본딩와이어(240) 및 제 2본딩와이어(242)를 감싸는 몰딩체(220)를 포함하여 구성된다. 상기 도전 테이프(250)로는 탭테이프를 사용하며, 여기서, 도전 테이프(250) 대신에 PCB를 사용할 수도 있다. 본 발명의 제 2실시예에서는 상면 가장자리에 다수개의 칩패드가 배열된 반도체 칩을 적용한 경우로, 제 1본딩와이어에 반도체 칩의 가장자리 부분에 배열된 칩패드와 도전 테이프를 연결시키고, 또한 제 2본딩 테이프에 의해 도전 테이프와 리드프레임을 연결시킨 구조를 가진다. 도 7및 도 8은 가장자리 부분에 다수개의 칩패드가 배열된 반도체 칩을 적용한 경우로서, 반도체 칩(200)과 리드프레임(260) 사이에 도전테이프(250)가 개재되되, 본 발명의 제 1실시예와는 달리, 반도체 칩(200)이 도전테이프(250) 상부에 배치되며, 제 1본딩와이어(240)에 의해 반도체 칩(200)의 칩패드와 도전 테이프(250)가 연결되고, 또한 제 2본딩 와이어(242)에 의해 도전 테이프(250)와 리드프레임(260)이 연결된 구조를 가진다. 한편, 도 7및 도 8에서는, 가장자리 부분에 다수개의 칩패드가 배열된 반도체 칩을 예로 하였으나, 상면 센터 부분에 칩패드가 배열된 반도체 칩을 적용할 수도 있다. 즉, 센터 부분에 칩패드가 배열된 반도체 칩을 적용한 경우, 도면에 도시되지는 않았지만, 리드프레임과 반도체 칩 사이에 도전 테이프가 개재되고, 제 1본딩와이어에 의해 반도체 칩의 칩패드와 도전 테이프가 연결되고, 또한 제 2본딩 와이어에 의해 도전 테이프와 리드프레임이 연결된 구조를 가진다. 상술한 바와 같이, 본 발명의 제 2실시예에서는, 도전테이프를 매개로 리드프레임과 반도체 칩을 연결시킨 패키지 구조를 가짐으로써, 칩패드가 반도체 칩 상면 센터 부분에 배열되던지 그 가장자리 부분에 배열되던지 배열 위치에 상관없이 모든 반도체 칩에 적용가능하다.7 and 8 are a plan view and a cross-sectional view of a semiconductor package according to a second embodiment of the present invention, which will be described using the case where a semiconductor chip in which chip pads are arranged at an edge portion is used as an example. As illustrated in FIGS. 7 and 8, the semiconductor package according to the second embodiment of the present invention includes a lead pad 260 and chip pads disposed on the lead frame 260 and arranged in a plurality of upper edges thereof. A first bonding wire 240 electrically connecting the semiconductor chip 200 having the semiconductor chip 200, the conductive tape 250 interposed between the lead frame 260 and the semiconductor chip 200, and the chip pad and the conductive tape 250. ), A second bonding wire 242 electrically connecting the conductive tape 250 and the lead frame 260, the semiconductor chip 200, the conductive tape 250, the first bonding wire 240, and the second bonding wire 242. It is configured to include a molding body 220 surrounding the bonding wire 242. A tap tape is used as the conductive tape 250, and a PCB may be used instead of the conductive tape 250. In the second embodiment of the present invention, a semiconductor chip in which a plurality of chip pads are arranged on the upper edge is applied, and the chip pad and the conductive tape arranged on the edge of the semiconductor chip are connected to the first bonding wire, The bonding tape has a structure in which the conductive tape and the lead frame are connected. 7 and 8 illustrate a case in which a semiconductor chip in which a plurality of chip pads are arranged at an edge portion thereof is applied, and a conductive tape 250 is interposed between the semiconductor chip 200 and the lead frame 260. Unlike the exemplary embodiment, the semiconductor chip 200 is disposed on the conductive tape 250, and the chip pad of the semiconductor chip 200 and the conductive tape 250 are connected by the first bonding wire 240. The conductive tape 250 and the lead frame 260 are connected by the second bonding wire 242. In FIGS. 7 and 8, a semiconductor chip in which a plurality of chip pads are arranged at an edge portion is taken as an example, but a semiconductor chip in which chip pads are arranged at an upper center portion may be used. That is, in the case where the semiconductor chip in which the chip pads are arranged in the center portion is applied, although not shown in the drawing, a conductive tape is interposed between the lead frame and the semiconductor chip, and the chip pad and the conductive tape of the semiconductor chip are formed by the first bonding wire. Is connected, and the conductive tape and the lead frame are connected by the second bonding wire. As described above, in the second embodiment of the present invention, by having a package structure in which a lead frame and a semiconductor chip are connected through a conductive tape, the chip pads are arranged at the center portion of the upper surface of the semiconductor chip or at the edge portion thereof. It is applicable to all semiconductor chips regardless of the arrangement position.
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이상에서와 같이, 본 발명에서는 도전테이프를 매개로 리드프레임과 반도체 칩을 연결시킨 패키지 구조를 가짐으로써, 칩패드가 반도체 칩의 상면 센터 부분과 가장자리 부분에 배열된 모든 경우에 적용가능하다.As described above, in the present invention, by having a package structure in which a lead frame and a semiconductor chip are connected through a conductive tape, the chip pad is applicable to all cases in which the chip pads are arranged at the top center and the edge of the semiconductor chip.
따라서, 본 발명은 반도체 칩에서의 칩패드 위치에 따라, 별도로 리드프레임을 제조할 필요가 없으므로, 패키지 제작 비용이 절감될 뿐만 아니라 패키지 제조 공정을 간편하게 진행할 수 있다.Therefore, according to the present invention, since the lead frame does not need to be manufactured separately according to the position of the chip pad in the semiconductor chip, the package manufacturing cost can be reduced and the package manufacturing process can be easily performed.
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기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1 및 도 2는 종래의 제 1실시예로, 칩 패드가 반도체 칩의 센터 부분에 배열된 구조를 가진 엘오씨(Lead On Chip) 타입의 반도체 패키지의 평면도 및 단면도.1 and 2 are a plan view and a cross-sectional view of a semiconductor package of a lead on chip type having a structure in which chip pads are arranged in a center portion of a semiconductor chip in a first conventional embodiment.
도 3 및 도 4는 종래의 제 2실시예로, 칩 패드가 반도체 칩의 가장자리 부분에 배열된 반도체 패키지의 평면도 및 단면도.3 and 4 are a plan view and a sectional view of a semiconductor package in which a chip pad is arranged at an edge portion of a semiconductor chip in a second conventional embodiment.
도 5 및 도 6은 본 발명의 제 1실시예로, 칩 패드가 반도체 칩의 센터 부분에 배열된 구조를 가진 반도체 패키지의 평면도 및 단면도.5 and 6 are a plan view and a cross-sectional view of a semiconductor package having a structure in which chip pads are arranged in a center portion of a semiconductor chip in a first embodiment of the present invention.
도 7 및 도 8은 본 발명의 제 2실시예로, 칩 패드가 반도체 칩의 센터 부분에 배열된 구조를 가진 반도체 패키지의 평면도 및 단면도.7 and 8 are a plan view and a cross-sectional view of a semiconductor package having a structure in which chip pads are arranged in a center portion of a semiconductor chip in a second embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
100. 반도체 칩 102. 칩패드100. Semiconductor chip 102. Chip pad
120. 몰딩체 140,142. 본딩와이어120. Molded bodies 140,142. Bonding Wire
150. 도전 테이프 152. 접착제150. Conductive Tape 152. Adhesive
160. 리드프레임160. Leadframe
Claims (4)
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| KR10-2001-0087262A KR100525091B1 (en) | 2001-12-28 | 2001-12-28 | semiconductor package |
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| KR10-2001-0087262A KR100525091B1 (en) | 2001-12-28 | 2001-12-28 | semiconductor package |
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| KR100525091B1 true KR100525091B1 (en) | 2005-11-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960038722U (en) * | 1995-05-02 | 1996-12-18 | Semiconductor chip | |
| KR0167292B1 (en) * | 1995-12-15 | 1998-12-15 | 문정환 | Semiconductor multipin package and method of making the same |
| KR19990010762A (en) * | 1997-07-18 | 1999-02-18 | 윤종용 | Semiconductor device package |
| KR0135890Y1 (en) * | 1995-12-18 | 1999-02-18 | 김주용 | Lead on chip package |
| KR100227120B1 (en) * | 1997-02-28 | 1999-10-15 | 윤종용 | Semiconductor chip package having combinational structure of lead-on-chip leads and standard normal leads |
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2001
- 2001-12-28 KR KR10-2001-0087262A patent/KR100525091B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960038722U (en) * | 1995-05-02 | 1996-12-18 | Semiconductor chip | |
| KR0167292B1 (en) * | 1995-12-15 | 1998-12-15 | 문정환 | Semiconductor multipin package and method of making the same |
| KR0135890Y1 (en) * | 1995-12-18 | 1999-02-18 | 김주용 | Lead on chip package |
| KR100227120B1 (en) * | 1997-02-28 | 1999-10-15 | 윤종용 | Semiconductor chip package having combinational structure of lead-on-chip leads and standard normal leads |
| KR19990010762A (en) * | 1997-07-18 | 1999-02-18 | 윤종용 | Semiconductor device package |
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