KR0167292B1 - Semiconductor multipin package and method of making the same - Google Patents
Semiconductor multipin package and method of making the same Download PDFInfo
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- KR0167292B1 KR0167292B1 KR1019950050641A KR19950050641A KR0167292B1 KR 0167292 B1 KR0167292 B1 KR 0167292B1 KR 1019950050641 A KR1019950050641 A KR 1019950050641A KR 19950050641 A KR19950050641 A KR 19950050641A KR 0167292 B1 KR0167292 B1 KR 0167292B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 다핀 패키지에 관한 것으로, 종래의 LOC 및 컨밴셔널 패키지는 주어진 패키지에서 다핀화를 실현하는데 한계가 있는 문제점이 있었던 바, 본 발명 반도체 다핀 패키지는 반도체 칩(20)의 중앙에 일렬로 다수개의 중앙패드(21)를 형성하고, 상기 반도체 칩(20)의 상면 가장자리에 다수개의 주변패드(26)를 형성하여 상, 하부 리드 프레임(22)(28)의 상, 하부 인너 리드(23)(29)와 각각 상, 하부 와이어(24)(30)로 연결시킴으로써 고집적화된 반도체 패키지의 다핀화가 실현되는 효과가 있다.The present invention relates to a semiconductor multi-pin package, the conventional LOC and the conventional package has a problem that there is a limit in realizing the multi-pinning in a given package, the semiconductor multi-pin package of the present invention in a line in the center of the semiconductor chip 20 A plurality of center pads 21 are formed, and a plurality of peripheral pads 26 are formed at upper edges of the semiconductor chip 20 to form upper and lower inner leads 23 of upper and lower lead frames 22 and 28. (29) and the upper and lower wires 24 and 30, respectively, have the effect that the pinning of the highly integrated semiconductor package is realized.
Description
제1도는 종래 LOC 패키지의 내부구성을 보인 사시도.1 is a perspective view showing the internal structure of a conventional LOC package.
제2도는 종래 컨밴셔널 패키지의 구성을 보인 종단면도.Figure 2 is a longitudinal sectional view showing the configuration of a conventional conventional package.
제3도는 본 발명 반도체 다핀 패키지의 구성을 보인 종단면도.Figure 3 is a longitudinal cross-sectional view showing the configuration of the semiconductor multi-pin package of the present invention.
제4도는 본 발명 반도체 다핀 패키지의 패드형성공정을 보인 평면도.4 is a plan view showing a pad forming process of the semiconductor multi-pin package of the present invention.
제5도는 본 발명 반도체 다핀 패키지의 1차 와이어 본딩공정을 보인 것으로, (a)는 평면도, (b)는 종단면도.Figure 5 shows the primary wire bonding process of the semiconductor multi-pin package of the present invention, (a) is a plan view, (b) is a longitudinal cross-sectional view.
제6도는 본 발명 반도체 다핀 패키지의 2차 와이어 본딩공정을 보인 것으로, (a)는 평면도, (b)는 종단면도.Figure 6 shows a secondary wire bonding process of the semiconductor multi-pin package of the present invention, (a) is a plan view, (b) is a longitudinal cross-sectional view.
제7도는 본 발명 반도체 다핀 패키지의 몰딩공정을 보인 종단면도.Figure 7 is a longitudinal cross-sectional view showing a molding process of the semiconductor multi-pin package of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 반도체 칩 21 : 중앙패드20: semiconductor chip 21: center pad
22,28 : 상, 하부 리드 프레임 23,29 : 상, 하부 인너 리드22,28: upper, lower lead frame 23,29: upper, lower inner lead
24,30 : 상, 하부 와이어 25,31 : 상, 하부 아웃 리드24,30: upper, lower wire 25,31: upper, lower out lead
26 : 주변패드 27 : 패들26: peripheral pad 27: paddle
본 발명은 반도체 다핀 패키지 및 그 제조방법에 관한 것으로, 패키지의 외부단자가 되는 아웃 리드의 수를 증가시키도록 하는데 적합한 반도체 다핀 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor multi-pin package and a method of manufacturing the same, and more particularly, to a semiconductor multi-pin package and a method of manufacturing the same, for increasing the number of out leads which become external terminals of the package.
제1도는 종래 LOC 패키지의 내부구성을 보인 사시도로서, 도시된 바와 같이, 종래 LOC 패키지는 반도체 칩(1)의 상면 중앙에 일렬로 다수개의 패드(2)가 형성되어 있고, 그 다수개의 패드(2)는 리드 프레임(3)의 인너 리드(4)와 각각 와이어(5)로 연결되어 있으며, 그 인너 리드(4)에는 몰딩부(6)의 외부로 아웃 리드(7)가 연장 형성되어 있는 구조로 되어 있다.FIG. 1 is a perspective view showing the internal structure of a conventional LOC package. As shown in the drawing, in the conventional LOC package, a plurality of pads 2 are formed in a line at the center of an upper surface of the semiconductor chip 1, and the plurality of pads ( 2) is connected to the inner lead 4 of the lead frame 3 by wires 5, respectively, and the inner lead 4 has an out lead 7 extending to the outside of the molding part 6. It is structured.
제2도는 종래 컨밴셔널 패키지의 구성을 보인 종단면도로서, 도시된 바와 같이, 종래 컨밴셔널(CONVENTIONAL) 패키지는 패들(10)의 상면에 반도체 칩(11)이 부착되어 있고, 그 반도체 칩(11)의 상면 가장자리에 형성되어 있는 다수개의 패드(12)와 리드 프레임(13)의 인너 리드(14)는 와이어(15)로 연결되어 있으며, 상기 반도체 칩(11), 와이어(15), 인너 리드(14)를 포함하는 일정면적이 에폭시로 몰딩된 몰딩부(16)가 형성되어 있을 뿐 아니라, 상기 인너 리드(14)에 연장하여 상기 몰딩부(16)의 외부로 아웃 리드(17)가 형성되어 있다.FIG. 2 is a longitudinal cross-sectional view showing a configuration of a conventional conventional package. As shown in the drawing, the conventional conventional package has a semiconductor chip 11 attached to an upper surface of the paddle 10, and the semiconductor chip 11 is shown in FIG. A plurality of pads 12 and inner leads 14 of the lead frame 13 formed at the upper edge of the upper surface of the lead frame 13 are connected by a wire 15, and the semiconductor chip 11, the wire 15, and the inner lead are connected to each other. In addition to the molding portion 16 formed by epoxy molding a predetermined area including the 14, it extends to the inner lead 14 to form the outer lead 17 to the outside of the molding portion 16 It is.
그러나, 상기와 같은 종래의 LOC 패키지와 컨밴셔널 패키지는 주어진 패키지에서 다수개의 아웃 리드(7)(17)를 설치하는데 한계가 있는 문제점이 있었다.However, the conventional LOC package and the conventional package as described above have a limitation in installing a plurality of out leads 7 and 17 in a given package.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 주어진 패키지에서 다수개의 아웃 리드를 설치하여 다핀화를 실현할 수 있는 반도체 다핀 패키지 및 그 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a semiconductor multi-pin package and a method of manufacturing the same, which can realize multi-pinning by installing a plurality of out leads in a given package.
상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩의 상면 중앙에 일렬로 형성되어 있는 다수개의 중앙패드와 상기 반도체 칩의 상면까지 연장 형성된 상부 리드 프레임의 상부 인너 리드가 상부 와이어로 각각 연결되고, 상기 상부 인너 리드에는 상부 아웃 리드가 연장 형성되며, 상기 반도체 칩의 상면 가장자리에 형성되어 있는 다수개의 주변패드와 상기 반도체 칩의 하면에 부착된 패들의 양측에 나열 설치되어 있는 하부 리드 프레임의 하부 인너 리드는 각각 하부 와이어로 연결되며, 상기 하부 인너 리드에 연장하여 하부 아웃 리드가 연장 형성되고, 상기 반도체 칩, 상, 하부 와이어, 상, 하부 인너리드를 포함한 일정면적이 에폭시로 몰딩된 몰딩부가 형성되어서 구성된 것을 특징으로 하는 반도체 다핀 패키지가 제공된다.In order to achieve the object of the present invention as described above, a plurality of center pads formed in a row at the center of the upper surface of the semiconductor chip and the upper inner lead of the upper lead frame extending to the upper surface of the semiconductor chip are connected to the upper wire, respectively. An upper out lead is formed in the upper inner lead, and a plurality of peripheral pads formed on the upper edge of the semiconductor chip and a lower inner of the lower lead frame are arranged on both sides of paddles attached to the lower surface of the semiconductor chip. Leads are connected to lower wires, respectively, and extend to the lower inner leads to extend lower out leads, and a molding part in which a predetermined area including the semiconductor chip, upper, lower wires, upper and lower inner leads is molded with epoxy. Provided is a semiconductor multi-pin package, characterized in that configured.
또한, 반도체 칩의 상면 중앙에 일렬로 다수개의 중앙패드를 형성하고, 상기 반도체 칩의 상면 가장자리에 다수개의 주변패드를 형성하는 패드형성공정을 수행하는 단계와, 상기 중앙패드와 상부 리드 프레임의 상부 인너 리드를 상부 와이어로 연결하는 1차 와이어 본딩공정을 수행하는 단계와, 상기 반도체 칩을 패들의 상면에 부착하고 상기 주변패드와 하부 리드 프레임의 하부 인너 리드를 하부 와이어로 연결하는 2차 와이어 본딩공정을 수행하는 단계와, 상기 반도체 칩, 상, 하부 인너 리드, 상, 하부 와이어를 포함하는 일정면적을 에폭시로 몰딩하여 몰딩부를 형성하는 몰딩공정을 수행하는 단계와, 상기 상부 리드 프레임의 불필요한 댐바부분을 제거하는 트리밍공정을 수행하는 단계와, 상기 상부 리드 프레임을 소정의 형태로 절곡하는 포밍공정을 수행하는 단계와, 상기 몰딩부의 하면을 그라인딩하여 하부 리드 프레임의 하부 아웃 리드를 외부로 노출시키는 그라인딩공정을 수행하는 단계의 순서로 제조되는 것을 특징으로 하는 반도체 다핀 패키지의 제조방법이 제공된다.The method may further include forming a plurality of center pads in a row at the center of the upper surface of the semiconductor chip, and forming a plurality of peripheral pads at the upper edge of the semiconductor chip, and forming an upper portion of the center pad and the upper lead frame. Performing a primary wire bonding process of connecting the inner lead to the upper wire, and attaching the semiconductor chip to the upper surface of the paddle and connecting the peripheral pad and the lower inner lead of the lower lead frame to the lower wire. Performing a process, and molding a predetermined area including the semiconductor chip, upper and lower inner leads, upper and lower wires with epoxy to form a molding part, and unnecessary dam bars of the upper lead frame. Performing a trimming process of removing a portion, and forming the upper lead frame by bending the upper lead frame into a predetermined shape There is provided a method of manufacturing a semiconductor multi-fin package, characterized in that the step of performing the grinding, and the grinding step of grinding the lower surface of the molding portion to expose the lower out lead of the lower lead frame to the outside. .
이하, 상기와 같이 구성되어 있는 본 발명 반도체 다핀 패키지의 실시례를 첨부된 도면을 참고로 하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings an embodiment of the semiconductor multi-pin package of the present invention configured as described above in more detail as follows.
제3도는 본 발명 반도체 다핀 패키지의 구성을 보인 종단면도로서, 도시된 바와 같이, 본 발명의 다핀 패키지는 반도체 칩(20)의 상면 중앙에 일렬로 형성되어 있는 다수개의 중앙패드(21)와 상기 반도체 칩(20)의 상면까지 연장 형성된 상부 리드 프레임(22)의 상부 인너 리드(23)는 상부 와이어(24)로 각각 연결되고, 상기 상부 인너 리드(23)에는 상부 아웃 리드(25)가 연장 형상되며, 상기 반도체 칩(20)의 상면 가장자리에 형성되어 있는 다수개의 주변패드(26)와 상기 반도체 칩(20)의 하면에 부착된 패들(27)의 양측에 나열 설치되어 있는 하부 리드 프레임(28)의 하부 인너 리드(29)는 각각 하부 와이어(30)로 연결되며, 상기 하부 인너 리드(29)에 연장하여 하부 아웃 리드(31)가 연장 형성되고, 상기 반도체 칩(20), 상, 하부 와이어(24)(29), 상, 하부 인너 리드(23)(28)를 포함한 일정면적을 에폭시로 몰딩한 몰딩부(32)를 형성하여서 구성된 것이다.3 is a longitudinal cross-sectional view showing the configuration of the semiconductor multi-pin package of the present invention, as shown, the multi-pin package of the present invention is a plurality of central pads 21 formed in a row in the center of the upper surface of the semiconductor chip 20 and the The upper inner leads 23 of the upper lead frame 22 extending to the upper surface of the semiconductor chip 20 are connected to the upper wires 24, respectively, and the upper out leads 25 extend to the upper inner leads 23. A lower lead frame having a plurality of peripheral pads 26 formed at the upper edge of the semiconductor chip 20 and paddles 27 attached to the lower surface of the semiconductor chip 20. The lower inner leads 29 of the 28 are connected to the lower wires 30, respectively, and the lower inner leads 29 extend to the lower inner leads 29, and the semiconductor chip 20, the upper, Lower wires 24, 29, upper, lower inner leads 23, 28 A certain area to be configured hayeoseo form the molded molding section 32 with an epoxy.
그리고, 이와 같이 구성되어 있는 본 발명 반도체 다핀 패키지의 제조방법을 제4도 내지 제7도를 참고하여 설명하면 다음과 같다.In addition, the method of manufacturing the semiconductor multi-pin package according to the present invention configured as described above will be described with reference to FIGS. 4 to 7.
제4도의 (a)(b)에 도시한 바와 같이, 반도체 칩(20)의 상면 중앙에 일렬로 다수개의 중앙패드(21)를 형성하고, 상기 반도체 칩(20)의 상면 가장자리에 다수개의 주변패드(26)를 형성하는 패드형성공정을 수행하는 단계와, 제5도의 (a)(b)에 도시한 바와 같이, 상기 반도체 칩(20)의 상면 중앙에 일렬로 형성된 다수개의 중앙패드(21)와 상부 리드 프레임(22)의 상부 인너 리드(23)를 상부 와이어(24)로 연결하는 1차 와이어 본딩공정을 수행하는 단계와, 제6도의 (a)(b)와 같이, 상기 반도체 칩(20)을 패들(27)의 상면에 부착하고 상기 주변패드(26)와 하부 리드 프레임(28)의 하부 인너 리드(29)를 하부 와이어(30)로 연결하는 2차 와이어 본딩공정을 수행하는 단계와, 제7도와 같이 상기 반도체 칩(20), 상, 하부 인너 리드(23)(29), 상, 하부 와이어(24)(30)를 포함하는 일정면적을 에폭시로 몰딩하여 몰딩부(32)를 형성하는 몰딩공정을 수행하는 단계와, 상기 상부 리드 프레임(22)의 불필요한 댐바부분을 제거하는 트리밍(TRIMING)공정를 수행하는 단계와, 상기 상부 리드 프레임(22)을 소정의 형태로 절곡하는 포밍(FORMMING)공정을 수행하는 단계와, 상기 몰딩부(32)의 하면을 그라인딩(GRINDING)하여 하부 리드 프레임(28)의 하부 아웃 리드(31)를 외부로 노출시키는 그라인딩공정을 수행하는 단계의 순서로 제조되는 것이다.As shown in (a) and (b) of FIG. 4, a plurality of center pads 21 are formed in a line at the center of the top surface of the semiconductor chip 20, and a plurality of peripheral pads are formed at the top edge of the semiconductor chip 20. Performing a pad forming process for forming the pads 26 and a plurality of central pads 21 arranged in a line at the center of the upper surface of the semiconductor chip 20, as shown in FIG. ) And a primary wire bonding process for connecting the upper inner lead 23 of the upper lead frame 22 to the upper wire 24, and as shown in FIG. 6 (a) (b), the semiconductor chip Attaching 20 to the upper surface of the paddle 27 and performing the secondary wire bonding process of connecting the peripheral pad 26 and the lower inner lead 29 of the lower lead frame 28 with the lower wire 30 And a predetermined area including the semiconductor chip 20, upper and lower inner leads 23 and 29, and upper and lower wires 24 and 30, as shown in FIG. Performing a molding process of forming a molding part 32 by molding a mold, performing a trimming process of removing unnecessary dam bar portions of the upper lead frame 22, and the upper lead frame 22. Performing a forming process of bending the mold in a predetermined form, and grinding the lower surface of the molding part 32 to expose the lower out lead 31 of the lower lead frame 28 to the outside. It is manufactured in the order of performing the grinding process.
상기 몰딩공정시 하부 아웃 리드(31)가 외부로 돌출되도록 몰딩부(32)를 형성하여 후공정인 그라인딩공정을 생략할 수도 있다.In the molding process, the molding part 32 may be formed so that the lower out lead 31 protrudes to the outside, and thus, the grinding process may be omitted.
이상에서 상세히 설명한 바와 같이 본 발명 반도체 다핀 패키지는 반도체 칩의 중앙에 일렬로 다수개의 중앙패드를 형성하고, 상기 반도체 칩의 상면 가장자리에 다수개의 주변패드를 형성하여 상, 하부 리드 프레임의 상, 하부 인너 리드와 각각 와이어로 연결시킴으로써 고집적화된 반도체 패키지의 다핀화가 실현되는 효과가 있다.As described in detail above, the semiconductor multi-pin package of the present invention forms a plurality of central pads in a row at the center of the semiconductor chip, and a plurality of peripheral pads are formed at the top edge of the semiconductor chip, and the upper and lower upper and lower lead frames are formed. By connecting the inner lead and the wire, respectively, there is an effect that the pinning of the highly integrated semiconductor package is realized.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050641A KR0167292B1 (en) | 1995-12-15 | 1995-12-15 | Semiconductor multipin package and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050641A KR0167292B1 (en) | 1995-12-15 | 1995-12-15 | Semiconductor multipin package and method of making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053631A KR970053631A (en) | 1997-07-31 |
| KR0167292B1 true KR0167292B1 (en) | 1998-12-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050641A KR0167292B1 (en) | 1995-12-15 | 1995-12-15 | Semiconductor multipin package and method of making the same |
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| Country | Link |
|---|---|
| KR (1) | KR0167292B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100401536B1 (en) * | 1997-12-31 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip |
| KR100525091B1 (en) * | 2001-12-28 | 2005-11-02 | 주식회사 하이닉스반도체 | semiconductor package |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001339029A (en) * | 2000-05-26 | 2001-12-07 | Shinko Electric Ind Co Ltd | Multilayered lead frame and semiconductor device using the same |
-
1995
- 1995-12-15 KR KR1019950050641A patent/KR0167292B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100401536B1 (en) * | 1997-12-31 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip |
| KR100525091B1 (en) * | 2001-12-28 | 2005-11-02 | 주식회사 하이닉스반도체 | semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053631A (en) | 1997-07-31 |
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