KR200163131Y1 - structure of semiconductor - Google Patents
structure of semiconductor Download PDFInfo
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- KR200163131Y1 KR200163131Y1 KR2019970001651U KR19970001651U KR200163131Y1 KR 200163131 Y1 KR200163131 Y1 KR 200163131Y1 KR 2019970001651 U KR2019970001651 U KR 2019970001651U KR 19970001651 U KR19970001651 U KR 19970001651U KR 200163131 Y1 KR200163131 Y1 KR 200163131Y1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 고안은 반도체소자의 구조를 개선하여 본딩패드 배열 위치 및 패드 수의 제약성을 해소하여 한정된 크기의 반도체소자에서의 패드 집적도를 향상시킬 수 있도록 한 것이다.The present invention is to improve the structure of the semiconductor device to solve the constraints of the bonding pad arrangement position and the number of pads to improve the pad integration in a limited size semiconductor device.
이를 위해, 본 고안은 와이어 본딩시 1차본딩이 이루어지는 본딩패드(2)를 구비한 반도체소자(1)에 있어서; 상기 반도체소자(1)를 2단으로 단차지게 형성함과 더불어, 상기 반도체소자(1)의 최상면(11) 및 단차부 상면(12)에 본딩패드(2)를 형성한 반도체소자의 칩 구조가 제공된다.To this end, the present invention is a semiconductor device 1 having a bonding pad (2) is the first bonding is made at the time of wire bonding; The chip structure of the semiconductor device in which the semiconductor device 1 is formed in two steps and the bonding pads 2 are formed on the top surface 11 and the top surface 12 of the semiconductor device 1 is formed in steps. Is provided.
Description
본 고안은 반도체소자에 관한 것으로서, 더욱 상세하게는 반도체소자의 구조를 개선하여 본딩패드 배열 위치 및 패드 수의 제약성을 해소하여 한정된 크기의 반도체소자에서의 패드 집적도를 향상시킬 수 있도록 한 것이다.The present invention relates to a semiconductor device, and more particularly, to improve the structure of a semiconductor device, thereby eliminating constraints of bonding pad arrangement positions and the number of pads, thereby improving pad integration in a limited size semiconductor device.
일반적으로, 반도체 패키지 제조 공정은 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication Process)을 완료한 후, 웨이퍼 상에 만들어진 각 칩(반도체소자)을 서로 분리시키는 다이싱(Dicing), 분리된 각 칩을 리드 프레임(Lead Frame)의 다이패드(die pad)에 안착시키는 칩 본딩(Chip Bonding), 칩 위의 본딩 패드(Bonding pad)와 리드 프레임의 인너리드(Inner Lead)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행한다.In general, a semiconductor package manufacturing process is a process of dicing and separating each chip (semiconductor device) made on a wafer after completion of a FAB process (fabrication process) for forming an integrated circuit on a wafer. Chip bonding to seat the die on the die pad of the lead frame, wire bonding to electrically connect the bonding pad on the chip and the inner lead of the lead frame. (Wire Bonding) is performed sequentially.
그 후, 칩 및 본딩된 골드 와이어를 감싸 보호하기 위한 몰딩(Molding)을 수행하게 된다.Thereafter, molding to wrap and protect the chip and the bonded gold wire is performed.
또한, 몰딩 공정을 수행한 후에는 리드 프레임의 타이 바(Tie Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Triming) 및, 아웃터리드(Outer Lead)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 된다.In addition, after the molding process, trimming to cut tie bars and dam bars of the lead frame, and forming the outer lead to a predetermined shape In turn.
트리밍 및 포밍 완료 후에는 최종적으로 솔더링(Soldering)을 실시하므로써 반도체 패키지 공정을 완료하게 된다.After trimming and forming, the soldering process is finally performed to complete the semiconductor package process.
도 1a와 도 1b는 종래 반도체소자를 도시한 것으로서, 반도체소자(1)는 육면체 형태로서 그 상면은 평면을 이루고 있으며, 그 상부면의 가장자리에는 전기적인 특성을 외부로 전달하는 본딩패드(2)가 다수개 형성되어 있고, 이 본딩패드(2)는 리드프레임(3)의 인너리드(4)와 골드 와이어(5)에 의해 전기적으로 연결된다.1A and 1B illustrate a conventional semiconductor device. The semiconductor device 1 has a hexahedron shape, the upper surface of which is a flat surface, and a bonding pad 2 that transmits electrical characteristics to the outside at an edge of the upper surface. A plurality of bond pads are formed, and the bonding pads 2 are electrically connected by the inner lead 4 and the gold wire 5 of the lead frame 3.
특히, 상기 본딩패드(2)의 배열은 패키지의 와이어 본드 공정과 밀접한 관계를 가지고 있으며, 이를 규정하는 규칙에 의해 소정의 형태로 배열된다.In particular, the arrangement of the bonding pads 2 is closely related to the wire bonding process of the package, and is arranged in a predetermined form by a rule for defining the bonding pad 2.
예를 들어, 반도체소자(1) 가장자리에서 중앙으로의 거리, 어느 하나의 본딩패드(2)와 그에 인접한 다른 본딩패드(2)와의 거리인 피치(pitch), 또는 패드의 크기 등의 설계 조건에 따라 반도체소자(1)에 형성되는 패드의 개수와 배열구조가 달라지게 되며, 이는 패키지의 와이어(5) 본드 공정의 수행 가능성과 공정 수율에 가장 큰 영향을 미치게 된다.For example, design conditions such as the distance from the edge of the semiconductor element 1 to the center, the pitch between one bonding pad 2 and another bonding pad 2 adjacent thereto, or the size of the pad, or the like may be used. Accordingly, the number and arrangement of pads formed in the semiconductor device 1 are changed, which has the greatest influence on the performance and the process yield of the wire 5 bonding process of the package.
또한, 상기 반도체소자(1)에 형성된 본딩패드(2)는 각기 다른 특성을 나타내므로, 와이어 본드 공정 수행시 인접한 와이어(5)와 접촉되지 않도록 인너리드(4)와 연결되어야 한다.In addition, since the bonding pads 2 formed on the semiconductor device 1 have different characteristics, the bonding pads 2 should be connected to the inner lead 4 so as not to contact the adjacent wires 5 when the wire bonding process is performed.
한편, 상기 반도체소자(1)는 각 본딩패드(2)와 인너리드(4)의 기능의 다양성을 향상시키기 위해, 본딩패드(2)의 수를 늘리고 있는 추세이다.On the other hand, the semiconductor device 1 is increasing the number of bonding pads (2) in order to improve the diversity of the function of each bonding pad (2) and inner lead (4).
그러나, 상기와 같은 종래의 반도체소자(1)는 그 구조상, 본딩패드(2)의 수를 늘리기가 곤란하다.However, in the conventional semiconductor device 1 as described above, it is difficult to increase the number of bonding pads 2 due to its structure.
즉, 반도체소자(1)의 상면이 평면적인 구조에서는 본딩패드(2)의 수를 무리하게 증가시킬 경우, 각 패드에 연결되는 와이어(5)간의 접촉으로 인해 쇼트가 발생하게 되는 문제점이 있다.That is, when the number of bonding pads 2 is excessively increased in the structure where the upper surface of the semiconductor device 1 is planar, there is a problem that short occurs due to contact between the wires 5 connected to each pad.
특히, 도 2a 및 도 2b에서와 같이 스태거드 와이어 본드(staggered wire bond) 방식(본딩패드(2)를 반도체소자(1) 상면에 복수개의 열로 배열하고 각열의 패드위치가 서로 엇갈리게 배열하는 방식)일 경우, 각 열의 와이어(5) 높이차를 차별화하는 배선 방법을 사용하는데, 이 경우에도 각 와이어(5)간의 접촉에 의해 쇼트가 발생하는 문제점이 있었다.In particular, as shown in FIGS. 2A and 2B, a staggered wire bond method (a method in which the bonding pads 2 are arranged in a plurality of rows on the upper surface of the semiconductor device 1 and the pad positions of the columns are staggered with each other). ), A wiring method for differentiating the height difference of the wires 5 in each row is used. In this case, a short occurs due to contact between the wires 5.
본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체소자의 구조를 개선하여 패드 배열 위치 및 수의 제약성을 해소하여 한정된 크기의 반도체소자에서의 본딩패드 집적도를 향상시킬 수 있도록 한 반도체소자를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, to provide a semiconductor device that can improve the bonding pad integration in a limited size semiconductor device by removing the constraints of the pad arrangement position and number by improving the structure of the semiconductor device Its purpose is to.
도 1a은 종래 반도체소자를 도시한 평면도1A is a plan view showing a conventional semiconductor device
도 1b는 도 1a의 측면도FIG. 1B is a side view of FIG. 1A
도 2a는 종래 반도체 소자의 다른 예를 도시한 평면도2A is a plan view showing another example of a conventional semiconductor device
도 2b는 도 2a의 측면도FIG. 2B is a side view of FIG. 2A
도 3은 본 고안에 따른 반도체소자를 도시한 평면도3 is a plan view showing a semiconductor device according to the present invention
도 4는 도 3의 측면도4 is a side view of FIG. 3
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
2 : 본딩패드 10 : 단차부2: bonding pad 10: stepped portion
6 : 메탈 패턴 11 : 소자 최상면6: metal pattern 11: element top surface
12 : 단차부 상면 13 : 단차부 측면12: stepped top surface 13: stepped side
상기한 목적을 달성하기 위해, 본 고안은 와이어 본딩시 1차본딩이 이루어지는 본딩패드를 구비한 반도체소자에 있어서; 상기 반도체소자를 2단으로 단차지게 형성함과 더불어, 상기 반도체소자의 최상면 및 단차부 상면에 본딩패드를 형성한 것을 특징으로 하는 반도체소자의 칩 구조가 제공된다.In order to achieve the above object, the present invention is a semiconductor device having a bonding pad that is the first bonding when the wire bonding; In addition to forming the semiconductor device in two steps, the chip structure of the semiconductor device is characterized in that a bonding pad is formed on the top surface of the semiconductor device and the top surface of the stepped portion.
이하, 본 고안의 일실시예를 첨부도면 도 3 및 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.
도 3은 본 고안에 따른 반도체소자를 도시한 평면도이고, 도 4는 도 3의 측면도로서, 본 고안은 와이어 본딩시 1차본딩이 이루어지는 본딩패드(2)를 구비한 반도체소자(1)에 있어서; 상기 반도체소자(1)를 2단으로 단차지게 형성함과 더불어, 상기 반도체소자(1)의 최상면(11) 및 단차부 상면(12)에 본딩패드(2)를 형성한 것이다.3 is a plan view illustrating a semiconductor device according to the present invention, and FIG. 4 is a side view of FIG. 3. In the present invention, a semiconductor device 1 including a bonding pad 2 in which primary bonding is performed during wire bonding is illustrated. ; The semiconductor device 1 is formed in two steps, and the bonding pads 2 are formed on the top surface 11 and the top surface 12 of the semiconductor device 1.
이 때, 상기 단차부 측면(13)은 상부로 갈수록 내측으로 경사지게 형성된다.At this time, the stepped side surface 13 is formed to be inclined inwardly toward the top.
이와 같이 구성된 본 고안의 반도체소자(1)의 제작과정 및 작용은 다음과 같다.The manufacturing process and operation of the semiconductor device 1 of the present invention configured as described above are as follows.
먼저, 본 고안의 반도체소자(1)는 계단형상으로 단차가공한 후, FAB 공정에서 각 단차면에 본딩패드(2)를 형성하게 된다.First, the semiconductor device 1 of the present invention is stepped in step shape, and then the bonding pads 2 are formed on each step surface in the FAB process.
한편, 본 고안의 반도체 소자는 2단으로 단차지게 형성되며, 상기 반도체소자(1)의 최상면(11)과 단차부 상면(12) 가장자리를 따라 각각 복수개의 본딩패드(2)가 형성된다.Meanwhile, the semiconductor device of the present invention is formed in two steps, and a plurality of bonding pads 2 are formed along edges of the top surface 11 and the top surface 12 of the stepped portion of the semiconductor device 1, respectively.
따라서, 와이어 본딩시에는 상기 반도체소자(1)의 최상면(11)과 단차부 상면(12) 가장자리를 따라 각각 복수개의 본딩패드(2)와 인너리드(4)의 선단부를 골드 와이어(5)를 이용하여 본딩하게 된다.Accordingly, when wire bonding, the leading ends of the plurality of bonding pads 2 and the inner lead 4 are formed along the edges of the top surface 11 and the stepped top surface 12 of the semiconductor device 1. Bonding.
이 때, 상기 와이어(5)의 루프는 서로 다르게 형성됨은 물론이다.At this time, the loop of the wire 5 is formed differently, of course.
한편, 상기 반도체소자(1)의 최상면(11) 및 단차부 상면(12)에는 한줄의 패드군을 형성하게 되는데, 본딩패드(2)의 개수를 최대치가 되도록 디자인하여도 반도체소자(1)에 형성된 단차로 인해 본딩패드(2) 상호간의 이격거리가 충분히 유지되므로, 본 고안의 반도체소자는 본딩패드(2)의 개수를 늘리는데 매우 유리하다.On the other hand, a single row of pad groups is formed on the top surface 11 and the top surface 12 of the semiconductor device 1, even if the number of bonding pads 2 is designed to be the maximum value. Since the separation distance between the bonding pads 2 is sufficiently maintained due to the formed step, the semiconductor device of the present invention is very advantageous for increasing the number of the bonding pads 2.
또한, 본 고안의 반도체소자(1)는 단차부 측면(13)이 상부로 갈수록 내측으로 경사지게 형성되므로 인해, 최상면(11)에 형성된 본딩패드(2)와 단차부 상면(12)에 형성된 본딩패드(2)를 메탈패턴(6)으로 연결시킴에 있어, 직각으로 꺽인 경우에 비해 메탈패턴 연결 공정이 용이하게 수행될 수 있게 된다.In addition, since the semiconductor device 1 of the present invention is formed to be inwardly inclined toward the upper side of the stepped portion 13, the bonding pads 2 formed on the top surface 11 and the bonding pads formed on the top surface 12 of the stepped portion are formed. In connecting (2) to the metal pattern 6, the metal pattern connection process can be easily performed as compared to the case bent at a right angle.
이상에서와 같이, 본 고안은 반도체소자의 구조를 2단으로 단차진 새로운 구조로 개선한 것이다.As described above, the present invention improves the structure of the semiconductor device into a new structure with two steps.
이에 따라, 본 고안은 본딩패드 배열 위치 및 패드 수의 제약성을 해소할 수 있으므로 인해, 한정된 크기의 반도체소자에서의 패드 집적도를 향상시킬 수 있게 되는 효과를 가져오게 된다.Accordingly, the present invention can solve the constraints of the bonding pad arrangement position and the number of pads, thereby bringing an effect of improving pad integration in a limited size semiconductor device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970001651U KR200163131Y1 (en) | 1997-02-04 | 1997-02-04 | structure of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970001651U KR200163131Y1 (en) | 1997-02-04 | 1997-02-04 | structure of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980057437U KR19980057437U (en) | 1998-10-15 |
| KR200163131Y1 true KR200163131Y1 (en) | 1999-12-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970001651U KR200163131Y1 (en) | 1997-02-04 | 1997-02-04 | structure of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200163131Y1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000063735A (en) * | 2000-08-01 | 2000-11-06 | 홍영희 | Highly concentrated pad |
| KR100708049B1 (en) * | 2001-04-11 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
-
1997
- 1997-02-04 KR KR2019970001651U patent/KR200163131Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980057437U (en) | 1998-10-15 |
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