KR0140458B1 - Leadframe for semiconductor package - Google Patents

Leadframe for semiconductor package

Info

Publication number
KR0140458B1
KR0140458B1 KR1019940034165A KR19940034165A KR0140458B1 KR 0140458 B1 KR0140458 B1 KR 0140458B1 KR 1019940034165 A KR1019940034165 A KR 1019940034165A KR 19940034165 A KR19940034165 A KR 19940034165A KR 0140458 B1 KR0140458 B1 KR 0140458B1
Authority
KR
South Korea
Prior art keywords
pad
common terminal
semiconductor package
lead
installation position
Prior art date
Application number
KR1019940034165A
Other languages
Korean (ko)
Other versions
KR960026708A (en
Inventor
류연철
김기정
박두현
Original Assignee
황인길
아남산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업주식회사 filed Critical 황인길
Priority to KR1019940034165A priority Critical patent/KR0140458B1/en
Publication of KR960026708A publication Critical patent/KR960026708A/en
Application granted granted Critical
Publication of KR0140458B1 publication Critical patent/KR0140458B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 패키지를 구성하는 리드프레임에 관한 것으로, 패드(P)에 인접하여 배열된 다수개의 내부리드(L)중 특정내부리드(L1)를 연결하여 공통단자(a)를 구비한 반도체 패키지 제품용 리드프레임에 있어서, 공통단자(a)가 연장 설치되는 특정내부리드(L1)의 끝단을 절곡(다운셋)하여 상기 공통단자(a)의 설치위치가 타이바(TB)에 연결 설치되는 패드(P)의 설치위치보다 높게 설치되도록 함으로써 패드 가장자리면과 공통단자(a)의 높이차가 현격히 유지되는 관계로 공통단자(a)와 반도체칩(C)간의 와이어(W) 연결시 와이어(W)가 패드(P)에 접촉되는 단락사고를 미연에 방지하게 되는 것이며, 나아가 제조 완성되는 반도체 패키지 제품의 품질을 획기적으로 향상시킬 수 있게 되는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame constituting a semiconductor package. A semiconductor having a common terminal (a) by connecting specific internal leads (L 1 ) among a plurality of internal leads (L) arranged adjacent to a pad (P). In the lead frame for a packaged product, the end of the specific inner lead (L 1 ) in which the common terminal (a) is extended is bent (downset) so that the installation position of the common terminal (a) is connected to the tie bar (TB). Since the height difference between the pad edge surface and the common terminal (a) is significantly maintained by installing higher than the installation position of the pad (P) to be installed, the wire at the time of connecting the wire (W) between the common terminal (a) and the semiconductor chip (C) The short circuit accident in which (W) is in contact with the pad (P) is prevented in advance, and further, the quality of the semiconductor package product to be manufactured can be significantly improved.

Description

반도체 패키지 제조용 리드프레임Leadframes for Semiconductor Package Manufacturing

제 1 도는 종래 리드프레임 구성도(부분단면도)1 is a conventional lead frame configuration diagram (partial cross-sectional view)

제 2 도는 본 발명의 리드프레임 평면 구성도2 is a plan view of the leadframe of the present invention

제 3 도는 제 2 도의 A-A선 단면 구성도3 is a cross-sectional view taken along the line A-A of FIG.

제 4 도는 제 2도의 B-B선 단면 확대도4 is an enlarged cross-sectional view taken along the line B-B of FIG.

제 5 도는 패드와 타이바의 연결상태를 나타낸 것으로,5 is a view showing a connection state of a pad and a tie bar.

(a)는 한번 절곡된 상태도(a) is a state of bending once

(b)는 두번 절곡된 상태도(b) is the state of being bent twice

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

P는 패드L은 내부리드L1특정내부리드P is pad L is internal lead L 1 Specific internal lead

C는 반도체칩a는 공통단자C is semiconductor chip a is common terminal

TB는 타이바DT1,DT2,DL1은 절곡부TB is tie bar DT 1 , DT 2 , DL 1 is bend

θ1,θ2는 절곡각도ℓ1은 타이바에 형성된 절곡부(DT1)의 길이θ 1 , θ 2 is the bending angle ℓ 1 is the length of the bent portion DT 1 formed on the tie bar

ℓ2는 특정내부리드에 형성된 절곡부(DL1)의 길이ℓ 2 is the length of the bend DL 1 formed in the specific inner lead.

본 발명은 반도체 패키지를 구성하는 리드프레임에 관한 것이다.The present invention relates to a lead frame constituting a semiconductor package.

일반적으로 반도체 패키지를 구성하는 리드프레임은 단자역할을 하는 다수개의 리드(L)와 반도체칩(C)이 탑재되는 패드(P)로 구성이 되는데, 상기 패드(P)는 타이바(TB)를 통해서 리드프레임(LF)에 연결되는 구성을 취하고 있다.In general, a lead frame constituting a semiconductor package is composed of a plurality of leads (L) serving as a terminal and a pad (P) on which the semiconductor chip (C) is mounted. The pad (P) is a tie bar (TB). It takes a configuration that is connected to the lead frame (LF) through.

그런데, 상기 패드(P) 위에 일정두께를 갖는 반도체칩(C)을 탑재(부착)함에 있어서 패키지 성형시 몰드효율을 높이기 위하여 통상 패드(P)를 연결하고 있는 타이바(TB)의 일정부위를 절곡(다운셋)시킴으로써 리드(L)와 반도체칩(반도체칩두께+패드두께)간의 센타균형이 이루어지도록 하고 있다.However, in mounting (attaching) the semiconductor chip C having a predetermined thickness on the pad P, a predetermined portion of the tie bar TB connecting the pad P is usually connected to increase mold efficiency during package molding. By bending (downset) the center balance between the lead L and the semiconductor chip (semiconductor chip thickness + pad thickness) is achieved.

한편, 최근들어 특정리드(L1; 특정내부리드)의 끝단을 길게 연장하여 공통단자(a)를 형성한 리드프레임 구조가 출현함으로써 반도체칩(C)과의 와이어본딩시 파워라인이나 접지라인을 구성함에 있어서 편의성을 제공하게 되었다.On the other hand, in recent years, a lead frame structure in which a common terminal (a) is formed by extending the end of a specific lead (L 1 ; specific internal lead) has emerged, so that a power line or a ground line may be removed during wire bonding with the semiconductor chip (C). Convenience has been provided in the construction.

그러나, 종래에는 파워라인이나 접지라인을 구성하기 위해 리드(L)의 끝단에 공통단자(a)을 연장 설치하되 그 높이를 패드(P)의 높이와 같게 구성함으로써 반도체칩(C)과 공통단자(a)를 와이어(W)로 본딩 연결하는 과정에서 자칫 와이어(W)가 공통단자(a)에 인접한 패드(P)의 가장자리면에 접촉되어 제품의 불량을 야기시키게 되는 문제점이 있었다.However, conventionally, the common terminal (a) is extended to the end of the lead (L) in order to form a power line or a ground line, but the height is made the same as the height of the pad (P) by the semiconductor chip (C) and the common terminal In the process of bonding (a) to the wire (W), there is a problem that the wire (W) is in contact with the edge surface of the pad (P) adjacent to the common terminal (a) to cause a defect of the product.

이에 본 발명에서는 특정리드(이하, 내부리드라 칭함)에서 연장되어 내부리드와 패드 사이에 위치하게 되는 공통단자(a)의 설치높이를 패드보다 다소 높게 위치시킴으로써 와이어(W)가 패드에 접촉되는 문제를 해결하게 된 것이다.Therefore, in the present invention, the wire (W) is in contact with the pad by placing the installation height of the common terminal (a), which is extended from a specific lead (hereinafter referred to as internal lid) and positioned between the internal lead and the pad, slightly higher than the pad. Will be solved.

이하, 본 발명을 첨부된 예시도면을 참고로 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

본 발명은 공통단자(a)가 연장 설치되는 특정내부리드(L1)의 끝단을 절곡(다운셋)하여 상기 공통단자(a)의 설치위치가 타이바(TB)에 연결 설치되는 패드(P)의 설치위치보다 높게 설치되도록 함으로써 반도체칩(C)과 공통단자(a)간의 와이어본딩이 보다 안전하게 실시될 수 있도록 한 것으로 그 구체적인 실시예를 통해 설명하면,The present invention bends (downsets) the end of a specific inner lead L 1 extending from the common terminal a to be installed (downset), and the pad P at which the installation position of the common terminal a is connected to the tie bar TB is installed. The wire bonding between the semiconductor chip (C) and the common terminal (a) can be carried out more safely by being installed higher than the installation position of the).

실시예 1Example 1

패드(P)를 연결하고 있는 타이바(TB)와 공통단자(a)를 연결하고 있는 특정내부리드(L1)에 1회의 하향절곡부(DT1)(DL1)를 형성하되, 타이바(TB)에 형성된 절곡부(DT1)의 길이(ℓ1)보다 특정내부리드(L1)에 형성된 절곡부(DL1)의 길이(ℓ2)를 짧게 하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 함으로써 와이어(W)가 패드(P)의 가장자리면에 접촉되지 않도록 할 수가 있다.But the pad tie bars connecting the (P) (TB) and a common terminal of a specific inner lead connecting the (a) (L 1) to form a single downwardly bent portion (DT 1) (DL 1) , tie bars Mounting positions of the bent part (DT 1) the length (ℓ 1) shorter than the common terminal (a) the length (ℓ 2) of the bent section (DL 1) formed in particular inner lead (L 1) of the formed (TB) Can be made to be somewhat higher than the installation position of the pad P, so that the wire (W) is not in contact with the edge surface of the pad (P).

실시예 2Example 2

패드(P)를 연결하고 있는 타이바(TB)와 공통단자(a)를 연결하고 있는 특정내부리드(L1)에 동일크기의 하향절곡부(DT1)(DL1)를 형성하되, 타이바(TB)의 절곡각도(θ1)보다 특정내부리드(L1)의 절곡각도(θ2)를 작게 하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 함으로써 와이어(W)가 패드(P)의 가장자리면에 접촉되지 않도록 할 수가 있다.But connected to the pad (P) to form the tie bars (TB) and the common terminal (a) downwardly bent portion of the same size, a particular inner lead (L 1) connecting the (DT 1) (DL 1) in, tie so than the bending angle (θ 1) of the bar (TB) reducing the bending angle (θ 2) of the specific inner lead (L 1) to the installation position of the common terminal (a) little greater configuration than the installation position of the pad (P) As a result, the wire W can be prevented from contacting the edge surface of the pad P. FIG.

실시예 3Example 3

패드(P)를 연결하고 있는 타이바(TB)에는 2회의 하향절곡부(DT1)(DT2)를 다단으로 형성하고, 특정내부리드(L1)에는 1회의 하향절곡부(DL1)를 형성하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 함으로써 와이어(W)가 패드(P)의 가장자리면에 접촉되지 않도록 할 수가 있다.Tie bars (TB), the portion twice downwardly bent connecting the pad (P) (DT 1), the unit single downwardly bent (DT 2) the formation in multiple stages, and a particular inner lead (L 1) (DL 1) By forming a so that the installation position of the common terminal (a) is somewhat higher than the installation position of the pad (P) it can be prevented that the wire (W) is in contact with the edge surface of the pad (P).

따라서, 본 발명에서와 같은 공통단자(a)의 설치구조에 의하면 특정내부리드(L1)에 연장 설치되는 공통단자(a)가 패드(P)의 설치위치보다 높게 설치되는 관계로 공통단자(a)와 반도체칩(C)을 와이어(W)로 연결시 패드 가장자리면과 공통단자(a)의 높이차가 현격하여 와이어(W)에 접촉되는 단락사고를 미연에 예방할 수가 있는 것이며, 나아가 제조 완성되는 반도체 패키지 제품의 품질을 획기적으로 향상시킬 수 있게 되는 것이다.Therefore, according to the installation structure of the common terminal (a) as in the present invention, the common terminal (a) extending to the specific inner lead (L 1 ) is installed higher than the installation position of the pad (P) common terminal ( When the a) and the semiconductor chip C are connected by the wire W, the height difference between the pad edge surface and the common terminal a is remarkable so that a short-circuit accident in contact with the wire W can be prevented in advance. It is possible to dramatically improve the quality of semiconductor package products.

Claims (4)

패드(P)에 인접하여 배열된 다수개의 내부리드(L)중 특정내부리드(L1)를 연장하여 공통단자(a)를 구비한 반도체 패키지 제품용 리드프레임에 있어서,A lead frame for a semiconductor package product having a common terminal (a) by extending a specific inner lead (L 1 ) among a plurality of inner leads (L) arranged adjacent to a pad (P), 공통단자(a)가 연장 설치되는 특정내부리드(L1)의 끝단을 절곡(다운셋)하여 상기 공통단자(a)의 설치위치가 타이바(TB)에 연결 설치되는 패드(P)의 설치위치보다 다소 높게 설치되도록 함을 특징으로 하는 반도체 패키지 제조용 리드프레임.Installation of the pad P in which the installation position of the common terminal a is connected to the tie bar TB by bending (downset) the end of the specific internal lead L 1 in which the common terminal a is extended. Lead frame for manufacturing a semiconductor package, characterized in that it is installed slightly higher than the position. 제 1 항에 있어서, 패드(P)를 연결하고 있는 타이바(TB)와 공통단자(a)를 연결하고 있는 특정내부리드(L1)에 1회의 하향절곡부(DT1)(DL1)를 형성하되, 타이바(TB)에 형성된 절곡부(DT1)의 길이(ℓ1)보다 특정내부리드(L1)에 형성된 절곡부(DL1)의 길이(ℓ2)를 짧게 하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 하을 특징으로 하는 반도체 패키지 제조용 리드프레임.According to claim 1, Tie bar (TB) connecting to the pad (P) and the one down bent portion (DT 1 ) (DL 1 ) to a specific internal lead (L 1 ) connecting the common terminal (a). To form a common terminal by shortening the length (L 2 ) of the bent portion (DL 1 ) formed on the specific inner lead (L 1 ) than the length (L 1 ) of the bent portion (DT 1 ) formed on the tie bar (TB). Lead frame for manufacturing a semiconductor package, characterized in that the installation position of (a) is configured to be somewhat higher than the installation position of the pad (P). 제 1 항에 있어서, 패드(P)를 연결하고 있는 타이바(TB)와 공통단자(a)를 연결하고 있는 특정내부리드(L1)에 동일크기의 하향절곡부(DT1)(DL1)를 형성하되, 타이바(TB)의 절곡각도(θ1)보다 특정내부리드(L1)의 절곡각도(θ2)를 작게 하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 함을 특징으로 하는 반도체 패키지 제조용 리드프레임.The method of claim 1, wherein the tie bar (TB) connecting the pad (P) and the downwardly bent portion (DT 1 ) (DL 1 ) of the same size to a specific internal lead (L 1 ) connecting the common terminal (a) ) installation of the bending angle (θ 1) than the smaller to the common terminal (a), the pad (P) installed position of the bending angle (θ 2) of the specific inner lead (L 1), the tie bars (TB) to form a A leadframe for manufacturing a semiconductor package, characterized in that it is configured slightly higher than the position. 제 1 항에 있어서, 패드(P)를 연결하고 있는 타이바(TB)에는 2회의 하향절곡부(DT1)(DT2)를 다단으로 형성하고, 특정내부리드(L1)에는 1회의 하향절곡부(DL1)를 형성하여 공통단자(a)의 설치위치가 패드(P)의 설치위치보다 다소 높게 구성되도록 함을 특징으로 하는 반도체 패키지 제조용 리드프레임.The method of claim 1, wherein the tie bar TB connecting the pad P is formed with two downward bends DT 1 and DT 2 in multiple stages, and the specific inner lead L 1 is provided with one downward. Lead frame for manufacturing a semiconductor package, characterized in that the bent portion (DL 1 ) is formed so that the installation position of the common terminal (a) is configured slightly higher than the installation position of the pad (P).
KR1019940034165A 1994-12-14 1994-12-14 Leadframe for semiconductor package KR0140458B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6765284B2 (en) 2002-02-25 2004-07-20 Rf Micro Devices, Inc. Leadframe inductors
KR100781149B1 (en) * 2001-12-21 2007-11-30 삼성테크윈 주식회사 Lead-frame strip and process for manufacturing semiconductor packages using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781149B1 (en) * 2001-12-21 2007-11-30 삼성테크윈 주식회사 Lead-frame strip and process for manufacturing semiconductor packages using the same
US6765284B2 (en) 2002-02-25 2004-07-20 Rf Micro Devices, Inc. Leadframe inductors

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